Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044178
O. Saadat, T. Palacios
Gate dielectrics are of great interest in AlGaN/GaN transistors to increase the Ion/Ioff ratios and to reduce gate leakage. However, integrating gate dielectrics with recessed gates require low temperature dielectric depositions where the gate photoresist is patterned and the gate is recessed before dielectric deposition. This study aims to characterize gate insulators deposited by low temperature atomic layer deposition (ALD) processes. HfO2 and Al2O3 were deposited at temperatures ranging from 80 °C to 120 °C and annealed under different ambient and temperature conditions. MIS-HEMTs with HfO2 gates showed excellent Ion/Ioff ratios of over 109 and subthreshold slopes of 71 mV/dec, which is superior to reference transistors with Schottky gates. Therefore, low temperature gate dielectrics promise to be an enabling technology for MIS-HEMTs with both recessed and insulating gates.
{"title":"Low temperature gate dielectric deposition for recessed AlGaN/GaN MIS-HEMTs","authors":"O. Saadat, T. Palacios","doi":"10.1109/ESSDERC.2011.6044178","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044178","url":null,"abstract":"Gate dielectrics are of great interest in AlGaN/GaN transistors to increase the I<inf>on</inf>/I<inf>off</inf> ratios and to reduce gate leakage. However, integrating gate dielectrics with recessed gates require low temperature dielectric depositions where the gate photoresist is patterned and the gate is recessed before dielectric deposition. This study aims to characterize gate insulators deposited by low temperature atomic layer deposition (ALD) processes. HfO<inf>2</inf> and Al<inf>2</inf>O<inf>3</inf> were deposited at temperatures ranging from 80 °C to 120 °C and annealed under different ambient and temperature conditions. MIS-HEMTs with HfO<inf>2</inf> gates showed excellent I<inf>on</inf>/I<inf>off</inf> ratios of over 10<sup>9</sup> and subthreshold slopes of 71 mV/dec, which is superior to reference transistors with Schottky gates. Therefore, low temperature gate dielectrics promise to be an enabling technology for MIS-HEMTs with both recessed and insulating gates.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124649279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044225
R. Jeyasingh, Marissa Caldwell, D. Milliron, H. Wong
We present the first demonstration of a functional Phase Change Memory (PCM) device fabricated using solution processed GeTe phase change nanoparticle. The device shows the characteristic memory behavior of crystallization and threshold switching. The cycling endurance of the device is up to 100 cycles. The cells are currently the best performing solution processed phase change material based memory devices reported so far.
{"title":"First demonstration of phase change memory device using solution processed GeTe nanoparticles","authors":"R. Jeyasingh, Marissa Caldwell, D. Milliron, H. Wong","doi":"10.1109/ESSDERC.2011.6044225","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044225","url":null,"abstract":"We present the first demonstration of a functional Phase Change Memory (PCM) device fabricated using solution processed GeTe phase change nanoparticle. The device shows the characteristic memory behavior of crystallization and threshold switching. The cycling endurance of the device is up to 100 cycles. The cells are currently the best performing solution processed phase change material based memory devices reported so far.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128157442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044235
P. Bradley
Wireless medical implant technology has been revolutionized in the last 10 years with the introduction of the world-wide Medical Implant Communication Service (MICS 402–405 MHz) and more recently MedRadio (401–406) MHz band. This has enabled the growth of remote monitoring with improved patient care. Recent advances and future developments in this growth area are presented.
{"title":"Wireless medical implant technology — Recent advances and future developments","authors":"P. Bradley","doi":"10.1109/ESSDERC.2011.6044235","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044235","url":null,"abstract":"Wireless medical implant technology has been revolutionized in the last 10 years with the introduction of the world-wide Medical Implant Communication Service (MICS 402–405 MHz) and more recently MedRadio (401–406) MHz band. This has enabled the growth of remote monitoring with improved patient care. Recent advances and future developments in this growth area are presented.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132073304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a two-stage trigger (TST) scheme is proposed to implement a low-capacitance and zero-ohm input resistance electrostatic-discharge (ESD) protection device for nanometer technologies. This scheme includes two different kinds of trigger devices. The diode string is the first trigger device, which provides the substrate current to trigger the output transistor on. As the output transistor is turned on, the source begins to inject the electrons. Thus, some of the electrons are collected to the anode of the silicon-controller rectifier (SCR) for driving it into the latch-up state. With the additional trigger device, the dimension of the main trigger device can be reduced to minimize its capacitance. Moreover, the output transistor can connect to the pad directly without any resistor since the diode string can be turned on before the output transistor is turned on.
{"title":"Two-stage trigger silicon-controller rectifier (SCR) for radio-frequency (RF) ESD protection in the nanometer technologies","authors":"Jian-Hsing Lee, Shao-Chang Huang, Yu-Huei Lee, Ke-Horng Chen","doi":"10.1109/ESSDERC.2011.6044155","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044155","url":null,"abstract":"In this paper, a two-stage trigger (TST) scheme is proposed to implement a low-capacitance and zero-ohm input resistance electrostatic-discharge (ESD) protection device for nanometer technologies. This scheme includes two different kinds of trigger devices. The diode string is the first trigger device, which provides the substrate current to trigger the output transistor on. As the output transistor is turned on, the source begins to inject the electrons. Thus, some of the electrons are collected to the anode of the silicon-controller rectifier (SCR) for driving it into the latch-up state. With the additional trigger device, the dimension of the main trigger device can be reduced to minimize its capacitance. Moreover, the output transistor can connect to the pad directly without any resistor since the diode string can be turned on before the output transistor is turned on.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129767726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044217
L. Silvestri, S. Reggiani, V. Passi, F. Ravaux, E. Dubois, J. Raskin, S. Clavaguera, A. Carella, C. Celle, J. Simonato
An extensive simulation analysis of silicon-nanoribbon field-effect transistors for the detection of chemical warfare agents has been performed through investigation of the physical behavior of the device. An accurate modeling of the nanoribbon interfaces has been carried out before and after gas exposure by combining simulation, characterization techniques and validation against experiments. A quantitative description of the physical mechanisms involved in the gas detection has been obtained.
{"title":"TCAD study of the detection mechanisms in silicon nanoribbon-based gas sensors","authors":"L. Silvestri, S. Reggiani, V. Passi, F. Ravaux, E. Dubois, J. Raskin, S. Clavaguera, A. Carella, C. Celle, J. Simonato","doi":"10.1109/ESSDERC.2011.6044217","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044217","url":null,"abstract":"An extensive simulation analysis of silicon-nanoribbon field-effect transistors for the detection of chemical warfare agents has been performed through investigation of the physical behavior of the device. An accurate modeling of the nanoribbon interfaces has been carried out before and after gas exposure by combining simulation, characterization techniques and validation against experiments. A quantitative description of the physical mechanisms involved in the gas detection has been obtained.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129622231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-11DOI: 10.1109/ESSDERC.2011.6044228
D. Roy, J. Klootwijk, D. Gravesteijn, R. Wolters
In this article we report on the change in contact resistance of TiW to doped-Sb2Te in the 5nm–50nm thickness range of the PCM layer. This interface is characterized both in the amorphous and in crystalline state of doped-Sb2Te. The nature of the interface is characterized by electrical contact resistance measurements and is expressed in terms of specific contact resistance, ρC. Results from the measurements on these structures with illumination indicated the existence of a space-charge region at the metal amorphous doped-Sb2Te interface.
{"title":"Contact resistance of TiW to ultra-thin phase change material layers","authors":"D. Roy, J. Klootwijk, D. Gravesteijn, R. Wolters","doi":"10.1109/ESSDERC.2011.6044228","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044228","url":null,"abstract":"In this article we report on the change in contact resistance of TiW to doped-Sb2Te in the 5nm–50nm thickness range of the PCM layer. This interface is characterized both in the amorphous and in crystalline state of doped-Sb2Te. The nature of the interface is characterized by electrical contact resistance measurements and is expressed in terms of specific contact resistance, ρC. Results from the measurements on these structures with illumination indicated the existence of a space-charge region at the metal amorphous doped-Sb2Te interface.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127354516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ESSCIRC.2011.6044907
P. Heremans, W. Dehaene, M. Steyaert, K. Myny, H. Marien, Jan Genoe, G. Gelinck, E. Veenendaal
In this paper, we review the state of the art of digital and analog circuits that have been shown in recent years in organic thin-film transistor technology on flexible plastic foil. The transistors are developed for backplanes of displays, and therefore have the characteristics to be unipolar and to possess two gates. The dual-gate architecture is employed to increase the transistors intrinsic transconductance, and to create dual-VT logic. We highlight recent examples of digital and analog plastic thin-film circuits. Furthermore, we give an outlook into new technological evolutions, including thin-film semiconductors with high mobility, the advent of complementary thin-film circuits, and of thin-film electrically re-programmable nonvolatile memory.
{"title":"Circuit design in organic semiconductor technologies","authors":"P. Heremans, W. Dehaene, M. Steyaert, K. Myny, H. Marien, Jan Genoe, G. Gelinck, E. Veenendaal","doi":"10.1109/ESSCIRC.2011.6044907","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044907","url":null,"abstract":"In this paper, we review the state of the art of digital and analog circuits that have been shown in recent years in organic thin-film transistor technology on flexible plastic foil. The transistors are developed for backplanes of displays, and therefore have the characteristics to be unipolar and to possess two gates. The dual-gate architecture is employed to increase the transistors intrinsic transconductance, and to create dual-VT logic. We highlight recent examples of digital and analog plastic thin-film circuits. Furthermore, we give an outlook into new technological evolutions, including thin-film semiconductors with high mobility, the advent of complementary thin-film circuits, and of thin-film electrically re-programmable nonvolatile memory.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115267342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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