Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044227
N. Pashkov, G. Navarro, J. Bastien, M. Suri, L. Perniola, V. Sousa, S. Maitrejean, A. Persico, A. Roule, A. Toffoli, G. Reimbold, B. De Salvo, O. Faynot, P. Zuliani, R. Annunziata
This paper intends to provide an overview of electrical performances of GexTe1−x with different proportions of Germanium or Tellurium for phase-change memories. Germanium-rich as well as Tellurium-rich phase-change materials have been integrated in simple test devices and programming characteristics, data retention and endurance performances are thoroughly analyzed. Tellurium-rich GeTe alloys exhibit stable programming characteristics that can sustain endurance test up to 1e7 cycles, while Germanium-rich GeTe, probably triggered by Ge segregation, shows an unstable RESET state during repeated write/erase cycles. Data retention on fresh devices is best for out-of-stoichiometry GeTe.
{"title":"Physical and electrical characterization of Germanium or Tellurium rich GexTe1−x for phase change memories","authors":"N. Pashkov, G. Navarro, J. Bastien, M. Suri, L. Perniola, V. Sousa, S. Maitrejean, A. Persico, A. Roule, A. Toffoli, G. Reimbold, B. De Salvo, O. Faynot, P. Zuliani, R. Annunziata","doi":"10.1109/ESSDERC.2011.6044227","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044227","url":null,"abstract":"This paper intends to provide an overview of electrical performances of GexTe1−x with different proportions of Germanium or Tellurium for phase-change memories. Germanium-rich as well as Tellurium-rich phase-change materials have been integrated in simple test devices and programming characteristics, data retention and endurance performances are thoroughly analyzed. Tellurium-rich GeTe alloys exhibit stable programming characteristics that can sustain endurance test up to 1e7 cycles, while Germanium-rich GeTe, probably triggered by Ge segregation, shows an unstable RESET state during repeated write/erase cycles. Data retention on fresh devices is best for out-of-stoichiometry GeTe.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125842469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044189
S. You, S. Decoutere, S. Van Huylenbroeck, A. Sibaja-Hernandez, R. Venegas, K. De Meyer
Various isolation schemes consisting of junction isolation, silicon pedestal isolation, deep trench isolation (DTI), airgap deep trench isolation and SOI with DTI are compared in terms of thermal resistance (RTH) and collector-substrate capacitance (CCS). Although to some extent RTH and CCS can be traded, airgap DTI and especially pedestal isolation perform very well, because the former results in strong reduction of CCS, while the latter results in strong reduction of RTH.
{"title":"Impact of isolation scheme on thermal resistance and collector-substrate capacitance of SiGe HBTs","authors":"S. You, S. Decoutere, S. Van Huylenbroeck, A. Sibaja-Hernandez, R. Venegas, K. De Meyer","doi":"10.1109/ESSDERC.2011.6044189","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044189","url":null,"abstract":"Various isolation schemes consisting of junction isolation, silicon pedestal isolation, deep trench isolation (DTI), airgap deep trench isolation and SOI with DTI are compared in terms of thermal resistance (R<inf>TH</inf>) and collector-substrate capacitance (C<inf>CS</inf>). Although to some extent R<inf>TH</inf> and C<inf>CS</inf> can be traded, airgap DTI and especially pedestal isolation perform very well, because the former results in strong reduction of C<inf>CS</inf>, while the latter results in strong reduction of R<inf>TH</inf>.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122333543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044177
O. Alatise, N. Parker-Allotey, M. Jennings, P. Mawby, I. Kennedy, G. Petkos
Power losses are investigated in trench MOSFETs as functions of trench depth and switching frequency. MOSFETs with different trench depths are fabricated and characterized. Measurements show that gate charge and capacitance increases with trench depth thereby increasing switching losses. However, conduction losses reduce with increasing trench depth because of higher gate-modulated accumulation charge at the drain. Since switching losses increase with frequency, the trade-off between the conduction and switching losses for different trench depths will be determined by the switching frequency. In conclusion, deep-trench MOSFETs outperform shallow-trench MOSFETs at low frequencies and become outperformed by the latter at high frequencies.
{"title":"Trench depth optimization for energy efficient discrete power trench MOSFETs","authors":"O. Alatise, N. Parker-Allotey, M. Jennings, P. Mawby, I. Kennedy, G. Petkos","doi":"10.1109/ESSDERC.2011.6044177","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044177","url":null,"abstract":"Power losses are investigated in trench MOSFETs as functions of trench depth and switching frequency. MOSFETs with different trench depths are fabricated and characterized. Measurements show that gate charge and capacitance increases with trench depth thereby increasing switching losses. However, conduction losses reduce with increasing trench depth because of higher gate-modulated accumulation charge at the drain. Since switching losses increase with frequency, the trade-off between the conduction and switching losses for different trench depths will be determined by the switching frequency. In conclusion, deep-trench MOSFETs outperform shallow-trench MOSFETs at low frequencies and become outperformed by the latter at high frequencies.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128279745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044220
A. Bertacchini, S. Scorcioni, D. Dondi, L. Larcher, P. Pavan, M. Todaro, A. Campa, G. Caretto, S. Petroni, A. Passaseo, M. de Vittorio
This paper presents a new AlN-based MEMS devices suitable for vibrational energy harvesting applications. Due to their particular shape and unlike traditional cantilever which efficiently harvest energy only if subjected to stimulus in the proper direction, the proposed devices have 3D generation capabilities solving the problem of device orientation and placement in real applications. Thanks to their particular shape, the realized devices present more than one fundamental resonance frequencies in a range comprised between 500 Hz and 1.5 kHz, with a voltage generation higher than 300μV and an output power up to 0.4 pW for single MEMS device.
{"title":"AlN-based MEMS devices for vibrational energy harvesting applications","authors":"A. Bertacchini, S. Scorcioni, D. Dondi, L. Larcher, P. Pavan, M. Todaro, A. Campa, G. Caretto, S. Petroni, A. Passaseo, M. de Vittorio","doi":"10.1109/ESSDERC.2011.6044220","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044220","url":null,"abstract":"This paper presents a new AlN-based MEMS devices suitable for vibrational energy harvesting applications. Due to their particular shape and unlike traditional cantilever which efficiently harvest energy only if subjected to stimulus in the proper direction, the proposed devices have 3D generation capabilities solving the problem of device orientation and placement in real applications. Thanks to their particular shape, the realized devices present more than one fundamental resonance frequencies in a range comprised between 500 Hz and 1.5 kHz, with a voltage generation higher than 300μV and an output power up to 0.4 pW for single MEMS device.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"469 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132024197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044200
B. Tsui, Jui-Yao Lai
Poly-Si thin-film transistor SONOS memory cells with various source/drain junctions are studied comprehensively. For pure Schottky-barrier junction, the overlap between source/drain and gate is critical. A 2-nm underlap results in high tunneling resistance and thus poor programming efficiency. Suitable designed modified-Schottky-barrier junction can improve programming speed by Fowler-Nordheim tunneling while keeping erase and retention performance unaltered. The main degradation mechanism during endurance test is attributed to interface state generation and tunneling layer degradation. After improving the quality of the tunneling layer, the modified Schottky barrier junction would be a promising choice for 3-dimentional poly-Si memory.
{"title":"A study on poly-Si thin-film transistor (TFT) SONOS memory cells with source/drain engineering","authors":"B. Tsui, Jui-Yao Lai","doi":"10.1109/ESSDERC.2011.6044200","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044200","url":null,"abstract":"Poly-Si thin-film transistor SONOS memory cells with various source/drain junctions are studied comprehensively. For pure Schottky-barrier junction, the overlap between source/drain and gate is critical. A 2-nm underlap results in high tunneling resistance and thus poor programming efficiency. Suitable designed modified-Schottky-barrier junction can improve programming speed by Fowler-Nordheim tunneling while keeping erase and retention performance unaltered. The main degradation mechanism during endurance test is attributed to interface state generation and tunneling layer degradation. After improving the quality of the tunneling layer, the modified Schottky barrier junction would be a promising choice for 3-dimentional poly-Si memory.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130766591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044174
I. Imperiale, A. Gnudi, E. Gnani, S. Reggiani, G. Baccarani
Some key aspects of the behavior of graphene nanoribbon (GNR) FETs for high-frequency analog applications are identified and discussed by means of a simulation study based on a full-quantum ballistic transport model. GNRs of width in the order of 10 nm are considered, where the small band-gap and the consequent leakage currents due to band-to-band-tunneling (BTBT) require a careful design. Simulations performed with a realistic model for source/drain metal contacts indicate that a proper choice of the drain doping profile can partially suppress BTBT currents. A 40-nm gate-length 2-nm SiO2 gate-dielectric GNR-FET can achieve a peak small-signal voltage gain of about 30 and a cut-off frequency well above 1 THz.
{"title":"High-frequency analog GNR-FET design criteria","authors":"I. Imperiale, A. Gnudi, E. Gnani, S. Reggiani, G. Baccarani","doi":"10.1109/ESSDERC.2011.6044174","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044174","url":null,"abstract":"Some key aspects of the behavior of graphene nanoribbon (GNR) FETs for high-frequency analog applications are identified and discussed by means of a simulation study based on a full-quantum ballistic transport model. GNRs of width in the order of 10 nm are considered, where the small band-gap and the consequent leakage currents due to band-to-band-tunneling (BTBT) require a careful design. Simulations performed with a realistic model for source/drain metal contacts indicate that a proper choice of the drain doping profile can partially suppress BTBT currents. A 40-nm gate-length 2-nm SiO2 gate-dielectric GNR-FET can achieve a peak small-signal voltage gain of about 30 and a cut-off frequency well above 1 THz.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"45 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134191758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044211
Yue Chen, J. Tan, Xinyang Wang, A. Mierop, A. Theuwissen
This paper presents a CMOS image sensor (CIS) with pinned-photodiode 5T active pixels which use an in-pixel buried channel source follower (BSF) with an optimized row selector (RS). According to our previous work [1][2], using in-pixel BSFs with optimized RS can achieve significant pixel dark random noise reduction, i.e. 50% reduction, specially for random telegraph signal (RTS) noise, and an increase of the pixel output swing and dynamic range. With significant dark random noise reduction, in order to evaluate the performance for perspective space or medical imaging application, this proposed pixel structure using 0.18μm CMOS image sensor process is also further characterized under X-ray radiation. The results show that although X-ray radiation induced additional acceptor-like interface traps will increase dark random noise, the BSF pixels are able to constrain the dark random noise increase after X-ray radiation.
{"title":"X-ray radiation effect on CMOS imagers with in-pixel buried-channel source follower","authors":"Yue Chen, J. Tan, Xinyang Wang, A. Mierop, A. Theuwissen","doi":"10.1109/ESSDERC.2011.6044211","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044211","url":null,"abstract":"This paper presents a CMOS image sensor (CIS) with pinned-photodiode 5T active pixels which use an in-pixel buried channel source follower (BSF) with an optimized row selector (RS). According to our previous work [1][2], using in-pixel BSFs with optimized RS can achieve significant pixel dark random noise reduction, i.e. 50% reduction, specially for random telegraph signal (RTS) noise, and an increase of the pixel output swing and dynamic range. With significant dark random noise reduction, in order to evaluate the performance for perspective space or medical imaging application, this proposed pixel structure using 0.18μm CMOS image sensor process is also further characterized under X-ray radiation. The results show that although X-ray radiation induced additional acceptor-like interface traps will increase dark random noise, the BSF pixels are able to constrain the dark random noise increase after X-ray radiation.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129526975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044232
H. Jung, Hyo Kyeom Kim, Sang Young Lee, N. Lee, T. Park, C. Hwang
The effects of post-deposition annealing (PDA) on the electrical characteristics of ZrO2 and HfO2 gate dielectric films were investigated. After PDA at 600°C, the insulating properties of ZrO2 were improved, while those of HfO2 were deteriorated. The improved insulating properties of ZrO2 are attributed to both the negligible increase of interfacial layer (IL) thickness and the transformation of its crystalline structure to the tetragonal phase. The degraded insulating properties of HfO2 after PDA at high temperatures were due to the abrupt increase of IL thickness and the generation of current paths through grain boundaries. The different IL growth between HfO2 and ZrO2 after PDA could be understood from the different formation energy of oxygen interstitials in the two dielectric films.
{"title":"Thermally robust atomic layer deposited ZrO2 gate dielectric films upon the post-deposition annealing","authors":"H. Jung, Hyo Kyeom Kim, Sang Young Lee, N. Lee, T. Park, C. Hwang","doi":"10.1109/ESSDERC.2011.6044232","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044232","url":null,"abstract":"The effects of post-deposition annealing (PDA) on the electrical characteristics of ZrO<inf>2</inf> and HfO<inf>2</inf> gate dielectric films were investigated. After PDA at 600°C, the insulating properties of ZrO<inf>2</inf> were improved, while those of HfO<inf>2</inf> were deteriorated. The improved insulating properties of ZrO<inf>2</inf> are attributed to both the negligible increase of interfacial layer (IL) thickness and the transformation of its crystalline structure to the tetragonal phase. The degraded insulating properties of HfO<inf>2</inf> after PDA at high temperatures were due to the abrupt increase of IL thickness and the generation of current paths through grain boundaries. The different IL growth between HfO<inf>2</inf> and ZrO<inf>2</inf> after PDA could be understood from the different formation energy of oxygen interstitials in the two dielectric films.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130998779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044167
C. Veerappan, J. Richardson, R. Walker, Day-Uei Li, M. Fishburn, D. Stoppa, F. Borghetti, Yuki Maruyama, M. Gersbach, R. Henderson, C. Bruschini, E. Charbon
With the emergence of large arrays of high-functionality pixels, it has become critical to characterize the performance non-uniformity of such arrays. In this paper we characterize a 160×128 array of complex pixels, each with a single-photon avalanche diode (SPAD) and a time-to-digital converter (TDC). A study of the array's non-uniformities in terms of the timing resolution, jitter, and photon responsivity is conducted for the pixels at various illumination levels, temperatures, and other operating conditions. In the study we found that, in photon-starved operation, the TDCs exhibit a median resolution of 55ps and a standard deviation of 2 ps. The pixels show a median timing jitter of 140ps. Moreover, we measured negligible variations in photon responsivity while changing the number of active pixels. These findings suggest that the image sensor can be used in highly reliable, large-scale, time-correlated measurements of single photons for biological, molecular, and medical applications. The chip is especially valuable for time-resolved imaging, single-photon counting, and correlation-spectroscopy under many realistic operating conditions.
{"title":"Characterization of large-scale non-uniformities in a 20k TDC/SPAD array integrated in a 130nm CMOS process","authors":"C. Veerappan, J. Richardson, R. Walker, Day-Uei Li, M. Fishburn, D. Stoppa, F. Borghetti, Yuki Maruyama, M. Gersbach, R. Henderson, C. Bruschini, E. Charbon","doi":"10.1109/ESSDERC.2011.6044167","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044167","url":null,"abstract":"With the emergence of large arrays of high-functionality pixels, it has become critical to characterize the performance non-uniformity of such arrays. In this paper we characterize a 160×128 array of complex pixels, each with a single-photon avalanche diode (SPAD) and a time-to-digital converter (TDC). A study of the array's non-uniformities in terms of the timing resolution, jitter, and photon responsivity is conducted for the pixels at various illumination levels, temperatures, and other operating conditions. In the study we found that, in photon-starved operation, the TDCs exhibit a median resolution of 55ps and a standard deviation of 2 ps. The pixels show a median timing jitter of 140ps. Moreover, we measured negligible variations in photon responsivity while changing the number of active pixels. These findings suggest that the image sensor can be used in highly reliable, large-scale, time-correlated measurements of single photons for biological, molecular, and medical applications. The chip is especially valuable for time-resolved imaging, single-photon counting, and correlation-spectroscopy under many realistic operating conditions.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"CATV-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132727955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044219
Y. Civet, S. Basrour, F. Casset, B. Icard, D. Mercier, J. Carpentier, J. Bustos, F. Leverd
This paper deals with a new compensation method to insure Micro-Electro-Mechanical (MEM) resonators frequency accuracy. We report new results of modeling, fabrication and characterization of MEM resonators frequency compensated fulfilling industry requirements respect to CMOS compatibility and collective correction. Both clamped-clamped beam and bulk mode resonators presenting compensation holes are treated.
{"title":"Holed MEM resonators with high aspect ratio, for high accuracy frequency trimming","authors":"Y. Civet, S. Basrour, F. Casset, B. Icard, D. Mercier, J. Carpentier, J. Bustos, F. Leverd","doi":"10.1109/ESSDERC.2011.6044219","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044219","url":null,"abstract":"This paper deals with a new compensation method to insure Micro-Electro-Mechanical (MEM) resonators frequency accuracy. We report new results of modeling, fabrication and characterization of MEM resonators frequency compensated fulfilling industry requirements respect to CMOS compatibility and collective correction. Both clamped-clamped beam and bulk mode resonators presenting compensation holes are treated.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116320115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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