Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044206
G. Piccolo, V. Puliyankot, A. Kovalgin, R. Hueting, A. Heringa, J. Schmitz
In this paper we present the increased light emission for Si p-i-n light emitting diodes (LED) by geometrical scaling of the injector size for p- and n-type carriers. TCAD simulations and electrical and optical characteristics of our realized devices support our findings. Reducing the injector size decreases the diffusion current: therefore, for a particular on current, the pn-product, and hence the radiative recombination, inside the active region increases. A comparison is made among reference large-scale, micro-size and nano-size injector p-i-n diodes. We demonstrate a 4-fold increase in electroluminescence (EL) when the injectors are scaled down to micro-size and a further 10-fold increase for nano-size injectors.
{"title":"Light emission enhancement by geometrical scaling of carrier injectors in Si-based LEDs","authors":"G. Piccolo, V. Puliyankot, A. Kovalgin, R. Hueting, A. Heringa, J. Schmitz","doi":"10.1109/ESSDERC.2011.6044206","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044206","url":null,"abstract":"In this paper we present the increased light emission for Si p-i-n light emitting diodes (LED) by geometrical scaling of the injector size for p- and n-type carriers. TCAD simulations and electrical and optical characteristics of our realized devices support our findings. Reducing the injector size decreases the diffusion current: therefore, for a particular on current, the pn-product, and hence the radiative recombination, inside the active region increases. A comparison is made among reference large-scale, micro-size and nano-size injector p-i-n diodes. We demonstrate a 4-fold increase in electroluminescence (EL) when the injectors are scaled down to micro-size and a further 10-fold increase for nano-size injectors.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116199544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044165
T. Tsuchiya
We have successfully measured accurate charge pumping (CP) currents for individual interface traps for the first time, and discovered that the maximum CP current for a single trap is various and usually less than fq (f is the gate pulse frequency, q is the electron charge). From detailed experimental results of the pulse-width dependent CP current, we concluded that the phenomenon is due to the interaction between individual interface traps in the carrier capture/emission processes. These findings are extremely important for describing the carrier trapping/detrapping phenomena in semiconductors using the Shockley-Read-Hall Theory.
{"title":"Accurate measurements of the charge pumping current due to individual MOS interface traps and interactions in the carrier capture/emission processes","authors":"T. Tsuchiya","doi":"10.1109/ESSDERC.2011.6044165","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044165","url":null,"abstract":"We have successfully measured accurate charge pumping (CP) currents for individual interface traps for the first time, and discovered that the maximum CP current for a single trap is various and usually less than fq (f is the gate pulse frequency, q is the electron charge). From detailed experimental results of the pulse-width dependent CP current, we concluded that the phenomenon is due to the interaction between individual interface traps in the carrier capture/emission processes. These findings are extremely important for describing the carrier trapping/detrapping phenomena in semiconductors using the Shockley-Read-Hall Theory.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114259985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044197
Hyun-Woo Chung, Huijung Kim, Hyungi Kim, Kanguk Kim, Sua Kim, Ki-Whan Song, Jiyoung Kim, Y. Oh, Y. Hwang, H. Hong, G. Jin, C. Chung
New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.
{"title":"Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT)","authors":"Hyun-Woo Chung, Huijung Kim, Hyungi Kim, Kanguk Kim, Sua Kim, Ki-Whan Song, Jiyoung Kim, Y. Oh, Y. Hwang, H. Hong, G. Jin, C. Chung","doi":"10.1109/ESSDERC.2011.6044197","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044197","url":null,"abstract":"New 4F2 cell structure of VPT for the future DRAM devices has been successfully developed by using 30nm process technology. The VPT shows superior current driving capability of 33μA and steep subthreshold slope of 77mV/dec. The VPT device demonstrates excellent retention characteristics in static mode. The floating body effects can be reduced by adopting the gradual junction profile even in a pillar-type channel. Also, the VPT produces about 60% and 30% more gross dies per wafer than conventional 8F2 and 6F2 cells.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123433951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044183
C. Xu, P. Batude, K. Romanjek, C. Le Royer, C. Tabone, B. Previtali, M. Jaud, X. Garros, M. Vinet, T. Poiroux, Q. Rafhay, M. Mouis
In this work, an optimized method to extract GIDL parameters has been used to characterize junction quality in FDSOI devices. This paper gives a practical methodology to properly apply this method: first, it insists on the importance to discriminate the respective contributions of GIDL and gate tunneling in drain current. Then, an activation energy criterion is used to determine the bias conditions that are appropriate to correct application of this method. Experimental values of “tunneling” field and tunneling parameter are extracted, with better reliability than with previous methods. Reliable extractions of the GIDL parameters enable to characterize junction quality independently of junction abruptness and of the impact of traps in the bandgap. This method is successfully applied and results are in agreement with expected results.
{"title":"Improved extraction of GIDL in FDSOI devices for proper junction quality analysis","authors":"C. Xu, P. Batude, K. Romanjek, C. Le Royer, C. Tabone, B. Previtali, M. Jaud, X. Garros, M. Vinet, T. Poiroux, Q. Rafhay, M. Mouis","doi":"10.1109/ESSDERC.2011.6044183","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044183","url":null,"abstract":"In this work, an optimized method to extract GIDL parameters has been used to characterize junction quality in FDSOI devices. This paper gives a practical methodology to properly apply this method: first, it insists on the importance to discriminate the respective contributions of GIDL and gate tunneling in drain current. Then, an activation energy criterion is used to determine the bias conditions that are appropriate to correct application of this method. Experimental values of “tunneling” field and tunneling parameter are extracted, with better reliability than with previous methods. Reliable extractions of the GIDL parameters enable to characterize junction quality independently of junction abruptness and of the impact of traps in the bandgap. This method is successfully applied and results are in agreement with expected results.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126277678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044179
D. Krausse, F. Benkhelifa, R. Reiner, R. Quay, O. Ambacher
In this paper we report on the development of an RF high power amplifier, based on normally-on AlGaN/GaN Heterostructure Field-Effect Transistors (HFETs) on semi-insulating SiC substrates. The amplifier is derived from a transistor with a total gate periphery of 120 mm that exhibits a breakdown voltage of 600 V. The transistor shows excellent DC characteristics up to 53 A in pulsed mode. The realized amplifier shows good performance in continuous wave (CW) mode with an output power of 139 W and an efficiency of 71 % at a frequency of 13.56 MHz, respectively. In pulsed mode, the amplifier exhibits an output power of 431 W for a duty cycle of 10 % which emphasizes the potential of the AlGaN/GaN material system for ISM applications. The comparison of the obtained values with silicon-based semiconductor devices furthermore shows the impressive advantages of AlGaN/GaN-based devices for parameters like current density and power density that are for AlGaN/GaN-based devices by an order of magnitude higher.
{"title":"AlGaN/GaN power amplifiers for ISM frequency applications","authors":"D. Krausse, F. Benkhelifa, R. Reiner, R. Quay, O. Ambacher","doi":"10.1109/ESSDERC.2011.6044179","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044179","url":null,"abstract":"In this paper we report on the development of an RF high power amplifier, based on normally-on AlGaN/GaN Heterostructure Field-Effect Transistors (HFETs) on semi-insulating SiC substrates. The amplifier is derived from a transistor with a total gate periphery of 120 mm that exhibits a breakdown voltage of 600 V. The transistor shows excellent DC characteristics up to 53 A in pulsed mode. The realized amplifier shows good performance in continuous wave (CW) mode with an output power of 139 W and an efficiency of 71 % at a frequency of 13.56 MHz, respectively. In pulsed mode, the amplifier exhibits an output power of 431 W for a duty cycle of 10 % which emphasizes the potential of the AlGaN/GaN material system for ISM applications. The comparison of the obtained values with silicon-based semiconductor devices furthermore shows the impressive advantages of AlGaN/GaN-based devices for parameters like current density and power density that are for AlGaN/GaN-based devices by an order of magnitude higher.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116405815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044209
André Lange, C. Sohrmann, R. Jancke, J. Haase, B. Cheng, U. Kovac, A. Asenov
As feature sizes shrink, random fluctuations gain importance in semiconductor manufacturing and integrated circuit design. Therefore, statistical device variability has to be considered in circuit design and analysis to properly estimate their impact and avoid expensive over-design. Statistical MOSFET compact modeling is required to accurately capture marginal distributions of varying device parameters and to preserve their statistical correlations. Due to limited simulator capabilities, variables are often assumed to be normally distributed. Although correlations may be captured using Principal Component Analysis, such an assumption may be inaccurate. As an alternative, Nonlinear Power Models have been proposed. Since we see some limitations in this approach, we analyze whether the multivariate Generalized Lambda Distribution is an alternative for statistical device modeling. Applying both approaches to extracted statistical device parameters, we conclude that both methods do not differ significantly in accuracy, but the multivariate Generalized Lambda Distribution is more general and less computationally expensive.
{"title":"A general approach for multivariate statistical MOSFET compact modeling preserving correlations","authors":"André Lange, C. Sohrmann, R. Jancke, J. Haase, B. Cheng, U. Kovac, A. Asenov","doi":"10.1109/ESSDERC.2011.6044209","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044209","url":null,"abstract":"As feature sizes shrink, random fluctuations gain importance in semiconductor manufacturing and integrated circuit design. Therefore, statistical device variability has to be considered in circuit design and analysis to properly estimate their impact and avoid expensive over-design. Statistical MOSFET compact modeling is required to accurately capture marginal distributions of varying device parameters and to preserve their statistical correlations. Due to limited simulator capabilities, variables are often assumed to be normally distributed. Although correlations may be captured using Principal Component Analysis, such an assumption may be inaccurate. As an alternative, Nonlinear Power Models have been proposed. Since we see some limitations in this approach, we analyze whether the multivariate Generalized Lambda Distribution is an alternative for statistical device modeling. Applying both approaches to extracted statistical device parameters, we conclude that both methods do not differ significantly in accuracy, but the multivariate Generalized Lambda Distribution is more general and less computationally expensive.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128968414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044226
Q. Hubert, C. Jahan, A. Toffoli, L. Perniola, V. Sousa, A. Persico, J. Nodin, H. Grampeix, F. Aussenac, B. De Salvo
In this paper, the impact of a thin interfacial oxide layer on the main electrical characteristics of phase-change memory devices is investigated. Lance-type memory cells were fabricated and a thin film of TiO2 or HfO2 was interposed between the Ge2Sb2Te5 (GST) layer and the 300nm diameter tungsten (W) contact plug. Electrical analyses were performed and a large decrease of the reset current is obtained. In particular TiO2 and HfO2 cells yield about 78% and 60% of current reduction respectively compared to GST reference cells. A very good endurance (>106 cycles) and programming window (2 orders of magnitude) were also observed. We confirm that the reset current reduction is mainly due to a decrease of the equivalent contact area and also to a better thermal efficiency.
{"title":"Reset current reduction in phase-change memory cell using a thin interfacial oxide layer","authors":"Q. Hubert, C. Jahan, A. Toffoli, L. Perniola, V. Sousa, A. Persico, J. Nodin, H. Grampeix, F. Aussenac, B. De Salvo","doi":"10.1109/ESSDERC.2011.6044226","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044226","url":null,"abstract":"In this paper, the impact of a thin interfacial oxide layer on the main electrical characteristics of phase-change memory devices is investigated. Lance-type memory cells were fabricated and a thin film of TiO<inf>2</inf> or HfO<inf>2</inf> was interposed between the Ge<inf>2</inf>Sb<inf>2</inf>Te<inf>5</inf> (GST) layer and the 300nm diameter tungsten (W) contact plug. Electrical analyses were performed and a large decrease of the reset current is obtained. In particular TiO<inf>2</inf> and HfO<inf>2</inf> cells yield about 78% and 60% of current reduction respectively compared to GST reference cells. A very good endurance (>10<sup>6</sup> cycles) and programming window (2 orders of magnitude) were also observed. We confirm that the reset current reduction is mainly due to a decrease of the equivalent contact area and also to a better thermal efficiency.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128485689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044186
A. Vandooren, D. Leonelli, R. Rooyackers, K. Arstila, G. Groeseneken, C. Huyghebaert
This paper reports on the process integration of vertical Tunnel FETs (TFETs) and analyzes the impact of process and geometrical parameters on the device performance. The gate-source overlap is shown to be a critical parameter, especially when the overlap is marginal. The study also suggests that a high interface trap density is at the origin of the poor onset characteristic of the vertical TFET and that improvement in passivating the surface of the vertical nanowires should be beneficial.
{"title":"Electrical results of vertical Si N-Tunnel FETs","authors":"A. Vandooren, D. Leonelli, R. Rooyackers, K. Arstila, G. Groeseneken, C. Huyghebaert","doi":"10.1109/ESSDERC.2011.6044186","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044186","url":null,"abstract":"This paper reports on the process integration of vertical Tunnel FETs (TFETs) and analyzes the impact of process and geometrical parameters on the device performance. The gate-source overlap is shown to be a critical parameter, especially when the overlap is marginal. The study also suggests that a high interface trap density is at the origin of the poor onset characteristic of the vertical TFET and that improvement in passivating the surface of the vertical nanowires should be beneficial.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125715612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044213
Elie Maricau, Leqi Zhang, J. Franco, P. Roussel, G. Groeseneken, G. Gielen
Negative Bias Temperature Instability (NBTI) is one of the most important reliability concerns in nanometer CMOS technologies. Accurate models for aging effects such as NBTI can help a designer in determining and improving circuit lifetime. This paper proposes a comprehensible compact model for reliability simulation of analog integrated circuits. The proposed model includes all typical NBTI peculiarities such as relaxation after voltage stress reduction and dependence on time-varying stress voltage and temperature. Comprising both the recoverable and permanent NBTI components, the model also offers a significant accuracy improvement over existing models such as the popular Reaction-Diffusion model. It is therefore well suited for accurate circuit reliability analysis and failure-time prediction. Further, the model includes only 10 process-dependent parameters, enabling easy calibration. The model is validated on a 1.9nm EOT SiON CMOS process.
{"title":"A compact NBTI model for accurate analog integrated circuit reliability simulation","authors":"Elie Maricau, Leqi Zhang, J. Franco, P. Roussel, G. Groeseneken, G. Gielen","doi":"10.1109/ESSDERC.2011.6044213","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044213","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) is one of the most important reliability concerns in nanometer CMOS technologies. Accurate models for aging effects such as NBTI can help a designer in determining and improving circuit lifetime. This paper proposes a comprehensible compact model for reliability simulation of analog integrated circuits. The proposed model includes all typical NBTI peculiarities such as relaxation after voltage stress reduction and dependence on time-varying stress voltage and temperature. Comprising both the recoverable and permanent NBTI components, the model also offers a significant accuracy improvement over existing models such as the popular Reaction-Diffusion model. It is therefore well suited for accurate circuit reliability analysis and failure-time prediction. Further, the model includes only 10 process-dependent parameters, enabling easy calibration. The model is validated on a 1.9nm EOT SiON CMOS process.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126349214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044196
A. Asif, H. Richter, C. Comtesse, J. Burghartz
System-in-foil (SiF) technology calls for low cost, ultra-thin and, high-performance high-voltage transistors to satisfy the need for high-voltage driving capability in many of the emerging flexible display technologies. An ultra-thin (20 μm) N-type lateral DMOS transistor (N-LDMOS) in Chipfilm™ technology, developed for this application, is presented. The fabrication process is fully compatible with conventional high-voltage CMOS technology using shallow trench isolation (STI). The N-LDMOS has a breakdown voltage >100 volts with a maximum drain current of 4.4 mA at a channel length of 9 μm and a width of 50 μm. At drain voltage Vds = 100 V, self-heating causes a reduction in drain current up to 19% on a silicon carrier wafer and 35% on polyimide (PI) foil relative to the drain current without self heating, thus indicating power dissipation to be one of most serious issues in flexible electronics.
{"title":"Ultra-thin flexible 100 V Chipfilm™ N-LDMOS","authors":"A. Asif, H. Richter, C. Comtesse, J. Burghartz","doi":"10.1109/ESSDERC.2011.6044196","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044196","url":null,"abstract":"System-in-foil (SiF) technology calls for low cost, ultra-thin and, high-performance high-voltage transistors to satisfy the need for high-voltage driving capability in many of the emerging flexible display technologies. An ultra-thin (20 μm) N-type lateral DMOS transistor (N-LDMOS) in Chipfilm™ technology, developed for this application, is presented. The fabrication process is fully compatible with conventional high-voltage CMOS technology using shallow trench isolation (STI). The N-LDMOS has a breakdown voltage >100 volts with a maximum drain current of 4.4 mA at a channel length of 9 μm and a width of 50 μm. At drain voltage Vds = 100 V, self-heating causes a reduction in drain current up to 19% on a silicon carrier wafer and 35% on polyimide (PI) foil relative to the drain current without self heating, thus indicating power dissipation to be one of most serious issues in flexible electronics.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125041972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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