Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044184
Frank Wessely, Tillmann A. Krauss, U. Schwalke
In this paper we report on a newly developed nanowire based field-effect device-architecture (NWFET) that can be used in high temperature environments. Our devices posess both high temperature stability and low OFF-state current. By changes in source/drain bias-polarity the electrical properties of the NW-devices can be tuned, whether the lowest possible leakage current, or maximum output current is desirable in a specific application.
{"title":"CMOS without doping: Midgap Schottky-barrier nanowire field-effect-transistors for high-temperature applications","authors":"Frank Wessely, Tillmann A. Krauss, U. Schwalke","doi":"10.1109/ESSDERC.2011.6044184","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044184","url":null,"abstract":"In this paper we report on a newly developed nanowire based field-effect device-architecture (NWFET) that can be used in high temperature environments. Our devices posess both high temperature stability and low OFF-state current. By changes in source/drain bias-polarity the electrical properties of the NW-devices can be tuned, whether the lowest possible leakage current, or maximum output current is desirable in a specific application.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122107357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044207
M. Bernardoni, N. Delmonte, G. Sozzi, R. Menozzi
This paper shows a physical approach to large-signal electro-thermal simulation of AlGaN/GaN HEMTs. The dynamic thermal behavior of the HEMT is described by a 3D network of thermal resistances and capacitances describing the physical structure of the HEMT, and including features such as the thermal boundary resistance between GaN and SiC, and the die-attach, as well as temperature non-uniformity along the gate finger. The thermal network is self-consistently coupled inside ADS with an electro-thermal large-signal model.
{"title":"Large-signal GaN HEMT electro-thermal model with 3D dynamic description of self-heating","authors":"M. Bernardoni, N. Delmonte, G. Sozzi, R. Menozzi","doi":"10.1109/ESSDERC.2011.6044207","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044207","url":null,"abstract":"This paper shows a physical approach to large-signal electro-thermal simulation of AlGaN/GaN HEMTs. The dynamic thermal behavior of the HEMT is described by a 3D network of thermal resistances and capacitances describing the physical structure of the HEMT, and including features such as the thermal boundary resistance between GaN and SiC, and the die-attach, as well as temperature non-uniformity along the gate finger. The thermal network is self-consistently coupled inside ADS with an electro-thermal large-signal model.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132714858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044160
A. Sammak, W. de Boer, L. Qi, L. Nanver
Selective epitaxial growth of crystalline Ge on Si in a standard ASM Epsilon 2000 CVD reactor is investigated for the fabrication of Ge ultrashallow junction p+ n diodes. At the deposition temperature of 700˚C, most of the lattice mismatch-defects are trapped within first 300nm of Ge growth and good quality single crystal Ge is achieved within a layer thickness of approximately 1 μm on window sizes up to hundreds of μm2. For p+ n junction fabrication, a sequence of pure-Ga and then pure-B depositions are utilized for the ultrashallow p-doping of As-doped Ge-islands. The I-V characterization of the diodes confirms the good quality of the Ge and ideality factors of ∼ 1.1 with low saturation currents are reliably achieved.
{"title":"High-quality p+ n Ge diodes selectively grown on Si with a sub-300nm transition region","authors":"A. Sammak, W. de Boer, L. Qi, L. Nanver","doi":"10.1109/ESSDERC.2011.6044160","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044160","url":null,"abstract":"Selective epitaxial growth of crystalline Ge on Si in a standard ASM Epsilon 2000 CVD reactor is investigated for the fabrication of Ge ultrashallow junction p+ n diodes. At the deposition temperature of 700˚C, most of the lattice mismatch-defects are trapped within first 300nm of Ge growth and good quality single crystal Ge is achieved within a layer thickness of approximately 1 μm on window sizes up to hundreds of μm2. For p+ n junction fabrication, a sequence of pure-Ga and then pure-B depositions are utilized for the ultrashallow p-doping of As-doped Ge-islands. The I-V characterization of the diodes confirms the good quality of the Ge and ideality factors of ∼ 1.1 with low saturation currents are reliably achieved.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132037861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044181
T. van Hemert, B. K. Kemaneci, R. Hueting, D. Esseni, M. V. van Dal, J. Schmitz
Subthreshold measurements can reveal key device parameters. We present a method to identify the region of the transfer characteristic where the drain current is affected by neither parasitic off-state leakage nor strong inversion current. Then we employ this method to obtain the conduction band edge shift for FinFETs with various fin widths using temperature dependent transfer characteristics. The results indicate lowering of the conduction band edge up to 40 meV, and hence threshold voltage, for fin widths down to 5 nm. This is explained by the combination of quantum confinement and strain effect on the band edges. We demonstrate a qualitative agreement between measurements, theory and simulation.
{"title":"Extracting the conduction band offset in strained FinFETs from subthreshold-current measurements","authors":"T. van Hemert, B. K. Kemaneci, R. Hueting, D. Esseni, M. V. van Dal, J. Schmitz","doi":"10.1109/ESSDERC.2011.6044181","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044181","url":null,"abstract":"Subthreshold measurements can reveal key device parameters. We present a method to identify the region of the transfer characteristic where the drain current is affected by neither parasitic off-state leakage nor strong inversion current. Then we employ this method to obtain the conduction band edge shift for FinFETs with various fin widths using temperature dependent transfer characteristics. The results indicate lowering of the conduction band edge up to 40 meV, and hence threshold voltage, for fin widths down to 5 nm. This is explained by the combination of quantum confinement and strain effect on the band edges. We demonstrate a qualitative agreement between measurements, theory and simulation.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114814937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044198
Yimao Cai, Xing Zhang, Ru Huang
This paper proposes a new structure with counter lightly doped drain (C-LDD) implantation for Multi-level cell (MLC) NOR flash memory application, aimed at reducing drain disturb. The manufacturing of C-LDD cell is fully compatible with standard floating gate flash process and no extra mask is required. Experimental results show that, by introducing C-LDD structure, the drain disturb can be successfully inhibited compared with conventional flash cell due to the optimization of drain junction doping profile. Endurance reliability is also improved when C-LDD is adopted. In addition, experiments reveal that no program degradation is observed when applying C-LDD implantation. These advantages have shown that C-LDD structure is a low cost and effective way to obtain high reliability in NOR flash memory.
{"title":"Counter-lightly-doped-drain (C-LDD) structure for Multi-level cell (MLC) NOR flash memory free of drain disturb","authors":"Yimao Cai, Xing Zhang, Ru Huang","doi":"10.1109/ESSDERC.2011.6044198","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044198","url":null,"abstract":"This paper proposes a new structure with counter lightly doped drain (C-LDD) implantation for Multi-level cell (MLC) NOR flash memory application, aimed at reducing drain disturb. The manufacturing of C-LDD cell is fully compatible with standard floating gate flash process and no extra mask is required. Experimental results show that, by introducing C-LDD structure, the drain disturb can be successfully inhibited compared with conventional flash cell due to the optimization of drain junction doping profile. Endurance reliability is also improved when C-LDD is adopted. In addition, experiments reveal that no program degradation is observed when applying C-LDD implantation. These advantages have shown that C-LDD structure is a low cost and effective way to obtain high reliability in NOR flash memory.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044158
A. Ghannam, L. Ourak, D. Bourrier, C. Viallon, T. Parra
This paper presents a novel and efficient low cost process capable of integrating high-Q above-IC inductors and their interconnects using a single electroplating step. It relies on the SU8 and BPN resist as well as an optimized electroplating technique to form the 3D interconnected inductor. The SU8 is used to form a thick layer located underneath the inductor to elevate it from the substrate. Then, the BPN is used as a high resolution mold (16:1) for copper electroplating. Standard or time optimized electroplating is later used to grow copper in a 3D manner, making the transition between all metallic layers straight forward. High-Q (55 @ 5 GHz) power inductors have been designed and integrated above an RF power LDMOS device using this process. Finally, the process capabilities are demonstrated by integrating a solenoid inductor using only two lithography masks and a single electroplating step.
{"title":"Efficent low cost process for single step metal forming of 3D interconnected above-IC inductors","authors":"A. Ghannam, L. Ourak, D. Bourrier, C. Viallon, T. Parra","doi":"10.1109/ESSDERC.2011.6044158","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044158","url":null,"abstract":"This paper presents a novel and efficient low cost process capable of integrating high-Q above-IC inductors and their interconnects using a single electroplating step. It relies on the SU8 and BPN resist as well as an optimized electroplating technique to form the 3D interconnected inductor. The SU8 is used to form a thick layer located underneath the inductor to elevate it from the substrate. Then, the BPN is used as a high resolution mold (16:1) for copper electroplating. Standard or time optimized electroplating is later used to grow copper in a 3D manner, making the transition between all metallic layers straight forward. High-Q (55 @ 5 GHz) power inductors have been designed and integrated above an RF power LDMOS device using this process. Finally, the process capabilities are demonstrated by integrating a solenoid inductor using only two lithography masks and a single electroplating step.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134583498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044188
S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison
The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.
{"title":"TCAD optimization of a dual N/P-LDMOS transistor","authors":"S. Poli, S. Reggiani, R. K. Sharma, G. Baccarani, E. Gnani, A. Gnudi, M. Denison","doi":"10.1109/ESSDERC.2011.6044188","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044188","url":null,"abstract":"The physical behavior of the dual N/P-LDMOS device concept is reviewed and analyzed. Through a proper optimization, a scalable device with good RSP vs. VBD performance in a range of 20–150 V is identified. Further, the current expansion at high gate and drain biases is fully explained by means of TCAD simulations and nicely exploited for the design of an LDO linear voltage regulator with excellent performance in terms of both drop-out voltage and maximum load current.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128101195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044163
A. Raychowdhury, C. Augustine, D. Somasekhar, J. Tschanz, K. Roy, V. De
Recent advances in non-volatile spin transfer torque (STT)-RAM technology, which stores data by the spin orientation of a soft ferromagnetic material and shows current induced switching, have created interest for its use as embedded memory [1–2]. When a spin-polarized current passes through a mono-domain ferromagnet, the ferromagnet absorbs some of the angular momentum of the electrons. It creates a torque that causes a flip in the direction of magnetization in the ferromagnet. This is used in magnetic tunneling junction (MTJ) based spin torque transfer (STT) RAM cells where a thin insulator (MgO) is sandwiched between a fixed ferromagnetic layer (polarizer) and the free layer (storage node). Depending on the direction of the current flow (perpendicular to these layers in our study), the magnetization of the free layer is switched to a parallel (P: low resistance state) or anti-parallel (AP: high resistance state) state. The study in this abstract is done for the 22nm technology node (temp: 85°C) for a storage area of 2F×F in a 6F2 cell. Typical MTJ stacks employed for use in STTRAMs comprise of ferromagnetic or synthetic Antiferromagnetic (for higher stability) free layers with a single or double MgO barrier (SBFF and DBSAF) (Fig. 1a, b). In the authors' previous work the use of double MgO for better writability and single MgO for better readability has been shown. In this paper, we propose a novel bidirectional MTJ stack (Fig. 1) with antiparallel fixed layers (DBSAF-AP) that inherits the high readability of a single barrier stack with better writability than a double barrier stack by employing an intermediate metastable ferromagnetic state (Fig. 2 — to be described later). By using a self-consistent NEGF (for transport) and LLG (for magnetic dynamics) simulation framework [2,4] we show readability, writability and scalability of the proposed stack.
{"title":"Numerical analysis of a novel MTJ stack for high readability and writability","authors":"A. Raychowdhury, C. Augustine, D. Somasekhar, J. Tschanz, K. Roy, V. De","doi":"10.1109/ESSDERC.2011.6044163","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044163","url":null,"abstract":"Recent advances in non-volatile spin transfer torque (STT)-RAM technology, which stores data by the spin orientation of a soft ferromagnetic material and shows current induced switching, have created interest for its use as embedded memory [1–2]. When a spin-polarized current passes through a mono-domain ferromagnet, the ferromagnet absorbs some of the angular momentum of the electrons. It creates a torque that causes a flip in the direction of magnetization in the ferromagnet. This is used in magnetic tunneling junction (MTJ) based spin torque transfer (STT) RAM cells where a thin insulator (MgO) is sandwiched between a fixed ferromagnetic layer (polarizer) and the free layer (storage node). Depending on the direction of the current flow (perpendicular to these layers in our study), the magnetization of the free layer is switched to a parallel (P: low resistance state) or anti-parallel (AP: high resistance state) state. The study in this abstract is done for the 22nm technology node (temp: 85°C) for a storage area of 2F×F in a 6F2 cell. Typical MTJ stacks employed for use in STTRAMs comprise of ferromagnetic or synthetic Antiferromagnetic (for higher stability) free layers with a single or double MgO barrier (SBFF and DBSAF) (Fig. 1a, b). In the authors' previous work the use of double MgO for better writability and single MgO for better readability has been shown. In this paper, we propose a novel bidirectional MTJ stack (Fig. 1) with antiparallel fixed layers (DBSAF-AP) that inherits the high readability of a single barrier stack with better writability than a double barrier stack by employing an intermediate metastable ferromagnetic state (Fig. 2 — to be described later). By using a self-consistent NEGF (for transport) and LLG (for magnetic dynamics) simulation framework [2,4] we show readability, writability and scalability of the proposed stack.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133798336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044233
T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai
This paper reports device process approach for further EOT scaling with small interface state density based on controlling La-silicate/Si interface. The interface state density of 1.6 × 1011 cm−2 eV−1 can be achieved by annealing at 800 °C for 30min in forming gas while significant increase in EOT has been also observed. EOT increase caused by high temperature annealing has been drastically inhibited with MIPS stacks accompanied by high quality interface. The effective electron mobility of 155 cm2/Vsec at 1MV/cm with an EOT of 0.62 nm has been obtained in direct contact La-silicate/Si structure by combination of MIPS stacks with high temperature annealing.
{"title":"Metal inserted poly-Si with high temperature annealing for achieving EOT of 0.62nm in La-silicate MOSFET","authors":"T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai","doi":"10.1109/ESSDERC.2011.6044233","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044233","url":null,"abstract":"This paper reports device process approach for further EOT scaling with small interface state density based on controlling La-silicate/Si interface. The interface state density of 1.6 × 1011 cm−2 eV−1 can be achieved by annealing at 800 °C for 30min in forming gas while significant increase in EOT has been also observed. EOT increase caused by high temperature annealing has been drastically inhibited with MIPS stacks accompanied by high quality interface. The effective electron mobility of 155 cm2/Vsec at 1MV/cm with an EOT of 0.62 nm has been obtained in direct contact La-silicate/Si structure by combination of MIPS stacks with high temperature annealing.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130289120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044185
L. Lattanzio, L. De Michielis, A. Ionescu
We propose a novel Tunnel field-effect transistor (TFET) concept called the electron-hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron-hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p-i-n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Near ideal average subthreshold slope (SSAVG ∼ 12 mV/dec over 6 decades of current) and ION/Ioff > 108 at VD = VG = 0.5 V figures of merit are obtained, due to the OFF-ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the silicon channel. Drive current (ION) in the EHBTFET is 3× higher that in traditional all-Si Tunnel FET but below 0.1 μA/μm.
{"title":"Electron-hole bilayer tunnel FET for steep subthreshold swing and improved ON current","authors":"L. Lattanzio, L. De Michielis, A. Ionescu","doi":"10.1109/ESSDERC.2011.6044185","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044185","url":null,"abstract":"We propose a novel Tunnel field-effect transistor (TFET) concept called the electron-hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron-hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p-i-n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Near ideal average subthreshold slope (SS<inf>AVG</inf> ∼ 12 mV/dec over 6 decades of current) and I<inf>ON</inf>/I<inf>off</inf> > 10<sup>8</sup> at V<inf>D</inf> = V<inf>G</inf> = 0.5 V figures of merit are obtained, due to the OFF-ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the silicon channel. Drive current (I<inf>ON</inf>) in the EHBTFET is 3× higher that in traditional all-Si Tunnel FET but below 0.1 μA/μm.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129164040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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