Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044195
L. Czornomaz, M. Kazzi, D. Caimi, P. Machler, C. Rossel, M. Bjoerk, C. Marchiori, J. Fompeyrine
Self-aligned access regions for indium gallium arsenide (In0.53Ga0.47As) n-type metal-oxide-semiconductor field effect transistors suitable for an extremely-thin III-V-on-insulator approach are investigated. Highly doped n+ source/drain regions are selectively grown by metal-organic vapor phase epitaxy and self-aligned Nickel-InGaAs alloyed metal contacts are obtained using a self-aligned silicide-like process, where different process conditions have been studied. Soft pre-epitaxy cleaning is followed by X-ray photoelectron spectroscopy. Relevant contact and sheet resistances are measured and integration issues are highlighted.
研究了适用于极薄iii - v -on-绝缘体方法的砷化铟镓(In0.53Ga0.47As) n型金属氧化物半导体场效应晶体管的自对准通路。通过金属-有机气相外延选择性地生长高掺杂n+源/漏区，并采用自对准类硅化物工艺获得自对准镍- ingaas合金金属触点，其中研究了不同的工艺条件。软预外延清洗之后是x射线光电子能谱。测量了相关的接触电阻和片电阻，并强调了集成问题。
{"title":"Self-aligned S/D regions for InGaAs MOSFETs","authors":"L. Czornomaz, M. Kazzi, D. Caimi, P. Machler, C. Rossel, M. Bjoerk, C. Marchiori, J. Fompeyrine","doi":"10.1109/ESSDERC.2011.6044195","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044195","url":null,"abstract":"Self-aligned access regions for indium gallium arsenide (In0.53Ga0.47As) n-type metal-oxide-semiconductor field effect transistors suitable for an extremely-thin III-V-on-insulator approach are investigated. Highly doped n+ source/drain regions are selectively grown by metal-organic vapor phase epitaxy and self-aligned Nickel-InGaAs alloyed metal contacts are obtained using a self-aligned silicide-like process, where different process conditions have been studied. Soft pre-epitaxy cleaning is followed by X-ray photoelectron spectroscopy. Relevant contact and sheet resistances are measured and integration issues are highlighted.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133355370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044194
C. Diouf, A. Cros, S. Monfray, J. Mitard, J. Rosa, F. Boeuf, G. Ghibaudo
The limiting carrier velocity concept allowing the determination of the nature of transport is used for the first time in Ge channel MOSFET. The limiting carrier velocity extracted on bulk germanium (Ge) pMOSFET is studied versus temperature. A drift-diffusion dominated transport is demonstrated despite the good transport quality of germanium devices down to 60 nm.
{"title":"Transport characterisation of Ge pMOSFETS in saturation regime","authors":"C. Diouf, A. Cros, S. Monfray, J. Mitard, J. Rosa, F. Boeuf, G. Ghibaudo","doi":"10.1109/ESSDERC.2011.6044194","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044194","url":null,"abstract":"The limiting carrier velocity concept allowing the determination of the nature of transport is used for the first time in Ge channel MOSFET. The limiting carrier velocity extracted on bulk germanium (Ge) pMOSFET is studied versus temperature. A drift-diffusion dominated transport is demonstrated despite the good transport quality of germanium devices down to 60 nm.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133116552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044210
C. Tanaka, M. Saitoh, K. Ota, K. Uchida, T. Numata
An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter is reduced 300 mV smaller than that of bulk-Tr.-based inverter due to the ideal sub-threshold slope. The performance benefits of NW-Tr.-based stacked circuit and SRAM cell are measured in terms of ultra-low voltage and ultra-low power operation.
利用Spice模型参数研究了基于纳米线晶体管的CMOS电路的超低电压性能。BSIM4的所有Spice模型参数均提取自300 mm SOI晶圆上纳米线晶体管的测量数据。NW-Tr的延时时间和功耗。基于和bulk-Tr。的CMOS电路进行了测试。NW-Tr的工作电压。的逆变器比bulk-Tr减小了300 mV。基于逆变器的理想亚阈值斜率。NW-Tr的性能优势。基于堆叠电路和SRAM单元的超低电压和超低功耗工作进行了测量。
{"title":"Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits","authors":"C. Tanaka, M. Saitoh, K. Ota, K. Uchida, T. Numata","doi":"10.1109/ESSDERC.2011.6044210","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044210","url":null,"abstract":"An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter is reduced 300 mV smaller than that of bulk-Tr.-based inverter due to the ideal sub-threshold slope. The performance benefits of NW-Tr.-based stacked circuit and SRAM cell are measured in terms of ultra-low voltage and ultra-low power operation.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127863241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044190
A. Sahoo, S. Frégonèse, M. Weis, N. Malbert, T. Zimmer
This paper describes a new and simple approach to accurately characterize the transient self-heating effect in Si-Ge Heterojunction Bipolar Transistors (HBTs), based on pulse measurements and verified through transient electro-thermal simulations. The measurements have been carried out over pulses applied at Base and Collector terminals simultaneously and the time response of Collector current increase due to self-heating effect are obtained. Compared to previous approach, a complete calibration has been performed including all the passive elements such as coaxial cables, connectors and bias network. Furthermore, time domain junction temperature variations, current of heat flux and lattice temperature distribution have been obtained numerically by means of 3D electro-thermal device simulations. The thermal parameters extracted from measurements using HiCuM HBT compact model have been verified with the parameters extracted from electro-thermal transient simulation. It has been shown that, the standard R-C thermal network is not sufficient to accurately model the thermal spreading behavior and therefore a recursive network has been employed which is more physical and suitable for transient electro-thermal modeling.
{"title":"Electro-thermal characterization of Si-Ge HBTs with pulse measurement and transient simulation","authors":"A. Sahoo, S. Frégonèse, M. Weis, N. Malbert, T. Zimmer","doi":"10.1109/ESSDERC.2011.6044190","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044190","url":null,"abstract":"This paper describes a new and simple approach to accurately characterize the transient self-heating effect in Si-Ge Heterojunction Bipolar Transistors (HBTs), based on pulse measurements and verified through transient electro-thermal simulations. The measurements have been carried out over pulses applied at Base and Collector terminals simultaneously and the time response of Collector current increase due to self-heating effect are obtained. Compared to previous approach, a complete calibration has been performed including all the passive elements such as coaxial cables, connectors and bias network. Furthermore, time domain junction temperature variations, current of heat flux and lattice temperature distribution have been obtained numerically by means of 3D electro-thermal device simulations. The thermal parameters extracted from measurements using HiCuM HBT compact model have been verified with the parameters extracted from electro-thermal transient simulation. It has been shown that, the standard R-C thermal network is not sufficient to accurately model the thermal spreading behavior and therefore a recursive network has been employed which is more physical and suitable for transient electro-thermal modeling.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117302450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044172
M. Najmzadeh, D. Bouvet, W. Grabinski, A. Ionescu
In this work we report dense arrays of highly doped gate-all-around Si nanowire accumulation-mode nMOS-FETs with sub-5 nm cross-sections. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ≥ 2.5 GPa uniaxial tensile stress is reported for the first time. The deeply scaled Si nanowire shows low-field electron mobility of 332 cm2/V.s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to ≈400 K and a VTH drift of −1.72 mV/K, VFB drift of −3.04 mV/K and an ion impurity scattering-based mobility reduction were observed.
{"title":"Accumulation-mode GAA Si NW nFET with sub-5 nm cross-section and high uniaxial tensile strain","authors":"M. Najmzadeh, D. Bouvet, W. Grabinski, A. Ionescu","doi":"10.1109/ESSDERC.2011.6044172","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044172","url":null,"abstract":"In this work we report dense arrays of highly doped gate-all-around Si nanowire accumulation-mode nMOS-FETs with sub-5 nm cross-sections. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ≥ 2.5 GPa uniaxial tensile stress is reported for the first time. The deeply scaled Si nanowire shows low-field electron mobility of 332 cm2/V.s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to ≈400 K and a VTH drift of −1.72 mV/K, VFB drift of −3.04 mV/K and an ion impurity scattering-based mobility reduction were observed.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"19 3-4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123547564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044161
Christoph Weis, S. Aschauer, G. Wachutka, A. Hartl, F. Hille, F. Pfirsch
Silicon power diodes can run into thermal destruction due to cosmic radiation-induced effects. We performed electro-thermal coupled device simulations in order to explain the failure mechanism. The results are compared to ion irradiation experiments. We find a strong heating located at the point where the incident ion deposits charge with a temperature rise which can explain melting of used materials.
{"title":"Numerical analysis of cosmic radiation-induced failures in power diodes","authors":"Christoph Weis, S. Aschauer, G. Wachutka, A. Hartl, F. Hille, F. Pfirsch","doi":"10.1109/ESSDERC.2011.6044161","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044161","url":null,"abstract":"Silicon power diodes can run into thermal destruction due to cosmic radiation-induced effects. We performed electro-thermal coupled device simulations in order to explain the failure mechanism. The results are compared to ion irradiation experiments. We find a strong heating located at the point where the incident ion deposits charge with a temperature rise which can explain melting of used materials.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132150125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044218
X. Sun, G. Posada, B. Majeed, W. Zhang, W. De Raedt, C. Diekmann, C. Eggs, E. Schmidhammer
This paper presents a 3D integration concept as a solution to package FBAR or BAW devices providing at the same time additional RF functionality. The feasibility of this 3D packaging solution has been proven by the successful realization of a 3D packaging demonstration vehicle including FBAR device, solder ring, bumps, through substrate via, low loss interconnects and extra integrated RF functionality. A good RF performance has been obtained. This concept could also be used for the packaging of MEMS, since the requirements are similar.
{"title":"3D stack packaging solution for BAW devices: 3D packaging demonstrator and RF performance","authors":"X. Sun, G. Posada, B. Majeed, W. Zhang, W. De Raedt, C. Diekmann, C. Eggs, E. Schmidhammer","doi":"10.1109/ESSDERC.2011.6044218","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044218","url":null,"abstract":"This paper presents a 3D integration concept as a solution to package FBAR or BAW devices providing at the same time additional RF functionality. The feasibility of this 3D packaging solution has been proven by the successful realization of a 3D packaging demonstration vehicle including FBAR device, solder ring, bumps, through substrate via, low loss interconnects and extra integrated RF functionality. A good RF performance has been obtained. This concept could also be used for the packaging of MEMS, since the requirements are similar.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126689501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044170
G. Mutinati, E. Brunet, T. Maier, S. Steinhauer, A. Kock
We demonstrate a novel gas sensor device, which is based on silicon chip-to-chip synthesis of ultralong tin oxide (SnO2) nanowires. The sensor device employs an interconnected nanowire network configuration, which exhibits a huge surface-to-volume ratio and provides full access of the target gas to the nanowires. The chip-to-chip SnO2 nanowire device has an extraordinary sensitivity to the toxic gas H2S. A concentration of only 1.4 ppm decreases the resistance of the sensor by ∼ 85%, which demonstrates a detection limit far in the ppb range. The SnO2-nanowire fabrication procedure based on spray pyrolysis and subsequent annealing is performed at atmospheric pressure, requires no vacuum and allows upscale of the substrate to a wafer size. 3D-integration with CMOS chips is proposed as viable way for practical realization of smart nanowire based gas sensor devices for the consumer market.
{"title":"Gas sensors based on silicon chip-to-chip synthesis of tin oxide nanowires","authors":"G. Mutinati, E. Brunet, T. Maier, S. Steinhauer, A. Kock","doi":"10.1109/ESSDERC.2011.6044170","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044170","url":null,"abstract":"We demonstrate a novel gas sensor device, which is based on silicon chip-to-chip synthesis of ultralong tin oxide (SnO2) nanowires. The sensor device employs an interconnected nanowire network configuration, which exhibits a huge surface-to-volume ratio and provides full access of the target gas to the nanowires. The chip-to-chip SnO2 nanowire device has an extraordinary sensitivity to the toxic gas H2S. A concentration of only 1.4 ppm decreases the resistance of the sensor by ∼ 85%, which demonstrates a detection limit far in the ppb range. The SnO2-nanowire fabrication procedure based on spray pyrolysis and subsequent annealing is performed at atmospheric pressure, requires no vacuum and allows upscale of the substrate to a wafer size. 3D-integration with CMOS chips is proposed as viable way for practical realization of smart nanowire based gas sensor devices for the consumer market.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122330070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044156
I. Nissinen, J. Nissinen, Antti-Kalle Lansman, L. Hallman, A. Kilpelä, Juha Kostamovaara, M. Kogler, M. Aikio, J. Tenhunen
A time-gated single photon avalanche diode (SPAD) has been designed and fabricated in a standard high voltage 0.35 μm CMOS technology for Raman spectroscopy. The sub-ns time gating window is used to suppress the fluorescence background typical of Raman studies, and also to minimize the dark count rate in order to maximize the signal-to-noise ratio of the Raman signal. The proposed time-gating technique is applied for measuring the Raman spectra of olive oil with a gate window of 300 ps, and shows significant fluorescence suppression.
{"title":"A sub-ns time-gated CMOS single photon avalanche diode detector for Raman spectroscopy","authors":"I. Nissinen, J. Nissinen, Antti-Kalle Lansman, L. Hallman, A. Kilpelä, Juha Kostamovaara, M. Kogler, M. Aikio, J. Tenhunen","doi":"10.1109/ESSDERC.2011.6044156","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044156","url":null,"abstract":"A time-gated single photon avalanche diode (SPAD) has been designed and fabricated in a standard high voltage 0.35 μm CMOS technology for Raman spectroscopy. The sub-ns time gating window is used to suppress the fluorescence background typical of Raman studies, and also to minimize the dark count rate in order to maximize the signal-to-noise ratio of the Raman signal. The proposed time-gating technique is applied for measuring the Raman spectra of olive oil with a gate window of 300 ps, and shows significant fluorescence suppression.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121075088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044166
K. Cheung, J. Campbell, A. Oates
We experimentally verify for the first time that random telegraph noise (RTN) in ultra-scaled MOSFETs is related to the inversion charge density in the channel. We then examine the merit of high mobility channel devices from the RTN prospective. This analysis strongly suggests that RTN is a serious obstacle for high mobility channel adoption.
{"title":"High mobility channel from the prospective of random telegraph noise","authors":"K. Cheung, J. Campbell, A. Oates","doi":"10.1109/ESSDERC.2011.6044166","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044166","url":null,"abstract":"We experimentally verify for the first time that random telegraph noise (RTN) in ultra-scaled MOSFETs is related to the inversion charge density in the channel. We then examine the merit of high mobility channel devices from the RTN prospective. This analysis strongly suggests that RTN is a serious obstacle for high mobility channel adoption.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121117566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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