Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044193
V. Gudmundsson, P. Hellstrom, M. Ostling
The effect of Be segregation on the Schottky barrier heights (SBH) of NiSi/Si is studied. Many elements have been shown to modulate the SBH of NiSi. However, group II elements have, to our knowledge, not been investigated before. Be is a double acceptor in Si, making it interesting for SBH modulation towards the valence band. The results show that Be implantation did not change the silicidation process. The SBH modulation was found to be strongly dependent on the silicidation temperature, with a minimum barrier to the valence band Φbp=0.28±0.02 eV, for diodes formed at 600 °C. SIMS analysis show the Be dose left at the interface is very low. With such a low dose, modulation cannot be caused by an interface dipole. However, the results can be explained assuming a thin (∼4–5 nm) layer of activated Be close to the interface.
{"title":"Effect of Be segregation on NiSi/Si Schottky barrier heights","authors":"V. Gudmundsson, P. Hellstrom, M. Ostling","doi":"10.1109/ESSDERC.2011.6044193","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044193","url":null,"abstract":"The effect of Be segregation on the Schottky barrier heights (SBH) of NiSi/Si is studied. Many elements have been shown to modulate the SBH of NiSi. However, group II elements have, to our knowledge, not been investigated before. Be is a double acceptor in Si, making it interesting for SBH modulation towards the valence band. The results show that Be implantation did not change the silicidation process. The SBH modulation was found to be strongly dependent on the silicidation temperature, with a minimum barrier to the valence band Φbp=0.28±0.02 eV, for diodes formed at 600 °C. SIMS analysis show the Be dose left at the interface is very low. With such a low dose, modulation cannot be caused by an interface dipole. However, the results can be explained assuming a thin (∼4–5 nm) layer of activated Be close to the interface.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131642978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044243
P. Dautriche
Market trends for Multimedia Application Processor go on pushing CMOS technology in nanometer range. This puts analog design community in a strange paradox with simultaneously big challenges and tremendous opportunities. Analog is more than ever a key ingredient of advanced SoC with high performances PLL, giga samples high speed serial links and embedded power management. Challenge appears while achieving very high level of analog performances in a non analog-optimized and moving environment, inducing design architecture change and development of new design methodology. Opportunities come when analyzing nanometer MOS device performances which are going beyond analog designer dreams. These tremendous performances open the door for new sets of applications such as embedded mmW, digitally boosted analog functions with new market opportunities. The talk will highlight this new analog era coming with nanometer technologies.
{"title":"Analog design trends and challenges in 28 and 20nm CMOS technology","authors":"P. Dautriche","doi":"10.1109/ESSDERC.2011.6044243","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044243","url":null,"abstract":"Market trends for Multimedia Application Processor go on pushing CMOS technology in nanometer range. This puts analog design community in a strange paradox with simultaneously big challenges and tremendous opportunities. Analog is more than ever a key ingredient of advanced SoC with high performances PLL, giga samples high speed serial links and embedded power management. Challenge appears while achieving very high level of analog performances in a non analog-optimized and moving environment, inducing design architecture change and development of new design methodology. Opportunities come when analyzing nanometer MOS device performances which are going beyond analog designer dreams. These tremendous performances open the door for new sets of applications such as embedded mmW, digitally boosted analog functions with new market opportunities. The talk will highlight this new analog era coming with nanometer technologies.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129797619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044199
Y. Liu, T. Mastukawa, K. Endo, S. Oruchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, K. Sakamoto, M. Masahara, T. Kamei, T. Hayashida, A. Ogura
The threshold voltage (Vt) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior Id-Vg characteristics are observed in the scaled poly-Si channel FinFETs with gate length (Lg) down to 54 nm or less. The standard deviation of Vt (σVt) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (Tox). However, the σVt of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even Lg was down to 76 nm.
{"title":"Variability analysis of scaled poly-Si channel FinFETs and tri-gate flash memories for high density and low cost stacked 3D-memory application","authors":"Y. Liu, T. Mastukawa, K. Endo, S. Oruchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, K. Sakamoto, M. Masahara, T. Kamei, T. Hayashida, A. Ogura","doi":"10.1109/ESSDERC.2011.6044199","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044199","url":null,"abstract":"The threshold voltage (V<inf>t</inf>) in scaled poly-Si channel FinFETs and tri-gate flash memories with poly-Si floating gate (FG) was systematically compared with crystal channel ones, for the first time. It was found that some superior I<inf>d</inf>-V<inf>g</inf> characteristics are observed in the scaled poly-Si channel FinFETs with gate length (L<inf>g</inf>) down to 54 nm or less. The standard deviation of V<inf>t</inf> (σV<inf>t</inf>) of poly-Si channel FinFETs was 3 times higher than that of crystal channel ones at the same gate oxide thickness (T<inf>ox</inf>). However, the σV<inf>t</inf> of poly-Si channel tri-gate flash memories after one program/erase (P/E) cycle became comparable to that of crystal channel ones. Moreover, it was found that punch-through voltage of the poly-Si channel tri-gate flash memory is as high as 4.6 V even L<inf>g</inf> was down to 76 nm.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115495799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044237
T. Ueda, Tsuyoshi Tanaka, D. Ueda
In this paper, we review the recent advances of GaN power switching and RF transistors developed at Panasonic. The presented devices are formed on cost effective Si substrates, which are very promising for the future mass production contributing to the reduction of the total fabrication cost. We develop the epitaxial growth technology using metal organic chemical vapor deposition (MOCVD) over 6-inch Si substrates by novel buffer layers relaxing the stress caused by the lattice and the thermal mismatches. Aiming at the power switching applications, we propose a new device structure called Gate Injection Transistor (GIT) for strongly desired normally-off operation together with low on-state resistances. The GITs are applied for an inverter to drive a motor which exhibits high operating efficiencies. Further increase of the breakdown voltages up to 2200V on Si is achieved by a novel Blocking Voltage Boosting (BVB) structure which prevents the inversion elections at the AlN/Si flowing at the periphery of the chips. As for the RF devices, we present 203W output power at 2.5GHz and 10.7W at 26.5GHz by AlGaN/GaN devices on Si. These GaN-based switching and RF power devices on Si substrates are very promising for a variety of applications taking advantages of their inherent low cost with superior performances.
{"title":"Current status on GaN-based RF-power devices","authors":"T. Ueda, Tsuyoshi Tanaka, D. Ueda","doi":"10.1109/ESSDERC.2011.6044237","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044237","url":null,"abstract":"In this paper, we review the recent advances of GaN power switching and RF transistors developed at Panasonic. The presented devices are formed on cost effective Si substrates, which are very promising for the future mass production contributing to the reduction of the total fabrication cost. We develop the epitaxial growth technology using metal organic chemical vapor deposition (MOCVD) over 6-inch Si substrates by novel buffer layers relaxing the stress caused by the lattice and the thermal mismatches. Aiming at the power switching applications, we propose a new device structure called Gate Injection Transistor (GIT) for strongly desired normally-off operation together with low on-state resistances. The GITs are applied for an inverter to drive a motor which exhibits high operating efficiencies. Further increase of the breakdown voltages up to 2200V on Si is achieved by a novel Blocking Voltage Boosting (BVB) structure which prevents the inversion elections at the AlN/Si flowing at the periphery of the chips. As for the RF devices, we present 203W output power at 2.5GHz and 10.7W at 26.5GHz by AlGaN/GaN devices on Si. These GaN-based switching and RF power devices on Si substrates are very promising for a variety of applications taking advantages of their inherent low cost with superior performances.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125872603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044212
S. Tyaginov, I. Starkov, C. Jungemann, H. Enichlmair, Jong-Mun Park, T. Grasser
We employ a physics-based model for hot-carrier degradation (HCD), which includes three main sub-tasks: the carrier transport module, a module describing interface state generation and a module for the simulation of the degraded devices. We examine different realizations of the model: with the transport module represented by Monte-Carlo, energy transport and drift-diffusion schemes. The main version, based on the Monte-Carlo approach, is able to represent HCD observed in different MOSFETs using the same set of the model parameters. These parameters have reliable and physically reasonable values. Therefore, we check whether two other versions are capable of the same representation (with the same parameters) or not. It appears that the simplified treatments fail to describe the degradation in devices of the same architecture but with different channel lengths employing a unique set of parameters. This circumstance suggests that a comprehensive HCD model has to be based on a rigorous solution of the Boltzmann transport equation (e.g. by means of a Monte-Carlo method).
{"title":"Impact of the carrier distribution function on hot-carrier degradation modeling","authors":"S. Tyaginov, I. Starkov, C. Jungemann, H. Enichlmair, Jong-Mun Park, T. Grasser","doi":"10.1109/ESSDERC.2011.6044212","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044212","url":null,"abstract":"We employ a physics-based model for hot-carrier degradation (HCD), which includes three main sub-tasks: the carrier transport module, a module describing interface state generation and a module for the simulation of the degraded devices. We examine different realizations of the model: with the transport module represented by Monte-Carlo, energy transport and drift-diffusion schemes. The main version, based on the Monte-Carlo approach, is able to represent HCD observed in different MOSFETs using the same set of the model parameters. These parameters have reliable and physically reasonable values. Therefore, we check whether two other versions are capable of the same representation (with the same parameters) or not. It appears that the simplified treatments fail to describe the degradation in devices of the same architecture but with different channel lengths employing a unique set of parameters. This circumstance suggests that a comprehensive HCD model has to be based on a rigorous solution of the Boltzmann transport equation (e.g. by means of a Monte-Carlo method).","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124109523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044175
E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani
In this work we investigate by numerical simulation the achievable performance of a steep-slope nanowire FET based on the filtering of the high-energy electrons by a superlattice heterostructure in the source extension. After a preliminary study aimed to identify the most promising material pairs for the superlattice with respect to the typical FET evaluation metrics, we concentrate on a superlattice-based FET employing the InGaAs-InAlAs pair, which provides a good switching slope and an excellent on-current. The device optimization leads to a prediction of an inverse SS = 35 mV/dec and an on-current exceeding 2.3 mA/μm at a supply voltage of 400 mV.
{"title":"An investigation on steep-slope and low-power nanowire FETs","authors":"E. Gnani, P. Maiorano, S. Reggiani, A. Gnudi, G. Baccarani","doi":"10.1109/ESSDERC.2011.6044175","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044175","url":null,"abstract":"In this work we investigate by numerical simulation the achievable performance of a steep-slope nanowire FET based on the filtering of the high-energy electrons by a superlattice heterostructure in the source extension. After a preliminary study aimed to identify the most promising material pairs for the superlattice with respect to the typical FET evaluation metrics, we concentrate on a superlattice-based FET employing the InGaAs-InAlAs pair, which provides a good switching slope and an excellent on-current. The device optimization leads to a prediction of an inverse SS = 35 mV/dec and an on-current exceeding 2.3 mA/μm at a supply voltage of 400 mV.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122874254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044182
M. Fjer, S. Persson, E. Escobedo-Cousin, A. O'Neill
In this paper, a study of the noise performance of strained Si Heterojunction Bipolar Transistors (sSi HBTs) is presented. This novel device exhibits low noise levels compared with Si Bipolar Junction Transistors (Si BJTs) and SiGe Heterojunction Bipolar Transistors (SiGe HBTs) for the same collector current, which can lower the noise in circuit applications. This performance benefit originates from the high current gain in sSi HBTs. However, the latter shows a higher noise level compared with the other devices at fixed base current. This is due to the presence of defects that are caused by the integration of a strained relaxed buffer used in the fabrication of sSi HBTs. The relationship between low frequency noise and defects has also been demonstrated using material characterisation.
{"title":"Noise performance in strained Si heterojunction bipolar transistors","authors":"M. Fjer, S. Persson, E. Escobedo-Cousin, A. O'Neill","doi":"10.1109/ESSDERC.2011.6044182","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044182","url":null,"abstract":"In this paper, a study of the noise performance of strained Si Heterojunction Bipolar Transistors (sSi HBTs) is presented. This novel device exhibits low noise levels compared with Si Bipolar Junction Transistors (Si BJTs) and SiGe Heterojunction Bipolar Transistors (SiGe HBTs) for the same collector current, which can lower the noise in circuit applications. This performance benefit originates from the high current gain in sSi HBTs. However, the latter shows a higher noise level compared with the other devices at fixed base current. This is due to the presence of defects that are caused by the integration of a strained relaxed buffer used in the fabrication of sSi HBTs. The relationship between low frequency noise and defects has also been demonstrated using material characterisation.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125627565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044203
P. Kostov, W. Gaberl, H. Zimmermann
In this work we present three speed optimized types of phototransistors built in a standard 180 nm CMOS technology without process modifications. An OPTO ASIC wafer consisting of a p+ substrate with a low doped p+ epitaxial layer on top of it is used for the implementation. The phototransistors were produced in 40×40 μm2 and 100×100 μm2 sizes. A gain in responsivity of more than 13 and bandwidths up to 50.7 MHz are achieved. As emitter followers, these phototransistors open the opportunity for application where high-speed photosensitive devices with inherent gain are needed. Possible applications are high speed opto-couplers, optical sensors, image sensors, etc.
{"title":"High-speed PNP PIN phototransistors in a 0.18 μm CMOS process","authors":"P. Kostov, W. Gaberl, H. Zimmermann","doi":"10.1109/ESSDERC.2011.6044203","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044203","url":null,"abstract":"In this work we present three speed optimized types of phototransistors built in a standard 180 nm CMOS technology without process modifications. An OPTO ASIC wafer consisting of a p<sup>+</sup> substrate with a low doped p<sup>+</sup> epitaxial layer on top of it is used for the implementation. The phototransistors were produced in 40×40 μm<sup>2</sup> and 100×100 μm<sup>2</sup> sizes. A gain in responsivity of more than 13 and bandwidths up to 50.7 MHz are achieved. As emitter followers, these phototransistors open the opportunity for application where high-speed photosensitive devices with inherent gain are needed. Possible applications are high speed opto-couplers, optical sensors, image sensors, etc.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124829653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044215
C. Kampen, A. Burenkov, Jurgen Lorenz
In this paper we present an extensive comparison of tunneling device simulations versus experimental results. Different tunneling models were used to simulate long channel silicon on insulator tunneling field effect transistors. The results were compared to experimental results, which were taken from the literature. A calibrated parameter set of the dynamic NonLocal-Tunneling model is presented, which qualitatively reproduces the experimental results at different electrostatic potential conditions and physical gate lengths.
{"title":"Challenges in TCAD simulations of tunneling field effect transistors","authors":"C. Kampen, A. Burenkov, Jurgen Lorenz","doi":"10.1109/ESSDERC.2011.6044215","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044215","url":null,"abstract":"In this paper we present an extensive comparison of tunneling device simulations versus experimental results. Different tunneling models were used to simulate long channel silicon on insulator tunneling field effect transistors. The results were compared to experimental results, which were taken from the literature. A calibrated parameter set of the dynamic NonLocal-Tunneling model is presented, which qualitatively reproduces the experimental results at different electrostatic potential conditions and physical gate lengths.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122851601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044162
Quan Chen, W. Schoenmaker, N. Banagaaya, W. Schilders, N. Wong
This paper deals with reformulating the electromagnetic field equations for a combined EM and TCAD approach in such a way that both extreme high and low frequencies can be solved. The importance of the method is found in eliminating the need for direct solvers which are restricted in application to very large systems. We elaborate on the numerical recipe for finding field solutions using the generic TCAD procedure based on the Newton-Raphson method combined with iterative solvers.
{"title":"EM-TCAD solving from 0–100 THz: A new implementation of an electromagnetic solver","authors":"Quan Chen, W. Schoenmaker, N. Banagaaya, W. Schilders, N. Wong","doi":"10.1109/ESSDERC.2011.6044162","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044162","url":null,"abstract":"This paper deals with reformulating the electromagnetic field equations for a combined EM and TCAD approach in such a way that both extreme high and low frequencies can be solved. The importance of the method is found in eliminating the need for direct solvers which are restricted in application to very large systems. We elaborate on the numerical recipe for finding field solutions using the generic TCAD procedure based on the Newton-Raphson method combined with iterative solvers.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116029937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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