Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044173
A. Paussa, M. Bresciani, D. Esseni, P. Palestri, L. Selmi
We report modeling results for low-field mobility and velocity saturation in bilayer graphene based on a newly developed semiclassical transport Monte-Carlo simulator validated by comparison with momentum relaxation time (MRT) calculations. We show that remote phonons originating in the dielectric stack are expected to strongly affect the mobility, although assessing their actual influence at high inversion charge requires the development of an accurate model for dynamic screening. When the applied bias opens the energy gap, the mobility is significantly reduced. The saturation velocity is expected to be as high as 3×107 cm/s and less degraded than mobility by bandgap opening.
{"title":"Phonon limited uniform transport in bilayer graphene transistors","authors":"A. Paussa, M. Bresciani, D. Esseni, P. Palestri, L. Selmi","doi":"10.1109/ESSDERC.2011.6044173","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044173","url":null,"abstract":"We report modeling results for low-field mobility and velocity saturation in bilayer graphene based on a newly developed semiclassical transport Monte-Carlo simulator validated by comparison with momentum relaxation time (MRT) calculations. We show that remote phonons originating in the dielectric stack are expected to strongly affect the mobility, although assessing their actual influence at high inversion charge requires the development of an accurate model for dynamic screening. When the applied bias opens the energy gap, the mobility is significantly reduced. The saturation velocity is expected to be as high as 3×107 cm/s and less degraded than mobility by bandgap opening.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123296165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044908
L. Fulbert, J. Fédéli
Silicon photonics has generated an outstanding interest for optical communications and for inter and intra-chip interconnects in electronic systems. High performance generic building blocks that can be used for a broad range of applications have already been demonstrated such as waveguides, I/O couplers, laser sources by III-V/Si heterogeneous integration, fast silicon modulators and germanium photodetectors. The paper will also review the different scenarios for integrating photonic functions with an electronic circuit, as well as the associated design, test and packaging challenges.
{"title":"Photonics — Electronics integration on CMOS","authors":"L. Fulbert, J. Fédéli","doi":"10.1109/ESSCIRC.2011.6044908","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044908","url":null,"abstract":"Silicon photonics has generated an outstanding interest for optical communications and for inter and intra-chip interconnects in electronic systems. High performance generic building blocks that can be used for a broad range of applications have already been demonstrated such as waveguides, I/O couplers, laser sources by III-V/Si heterogeneous integration, fast silicon modulators and germanium photodetectors. The paper will also review the different scenarios for integrating photonic functions with an electronic circuit, as well as the associated design, test and packaging challenges.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124005264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044164
Zhaowang Zong, Z. Qiu, Ran Liu
The frequency-dependent thermal response in 3ω measurement is investigated using transient electro-thermal coupling simulations. Furthermore, the heat flow ratio m(ω), quantifying the deviation degree of Cahill's model, is exploited for extraction of the thermal conductivity of the heater strip itself, which extends the capability of 3ω method to high-thermal-conductivity thin films.
{"title":"A novel technique for extraction of thermal conductivity in metallic thin films","authors":"Zhaowang Zong, Z. Qiu, Ran Liu","doi":"10.1109/ESSDERC.2011.6044164","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044164","url":null,"abstract":"The frequency-dependent thermal response in 3ω measurement is investigated using transient electro-thermal coupling simulations. Furthermore, the heat flow ratio m(ω), quantifying the deviation degree of Cahill's model, is exploited for extraction of the thermal conductivity of the heater strip itself, which extends the capability of 3ω method to high-thermal-conductivity thin films.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131483744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044171
Ji Cao, A. Ionescu
Self-aligned suspended-body single-walled carbon nanotube field-effect-transistors (SWCNT FETs) have been demonstrated with efficient and independent electrostatic control by two laterally placed independent gates spaced less than 100 nm away from the CNT channel. The operation of the suspended-body SWCNTFETs, in double-gate (DG) mode and single-gate (SG) mode, is analyzed in detail. Strong interface coupling of the double gates and tuning of the second independent gate (linear threshold voltage variation, constant subthreshold swing), are typical effects in these suspended-body SWCNTFETs. The comparison of SG and DG operations demonstrates the superiority of DG SWCNTFETs: remarkably improved subthreshold slope (from 130 mV/decade to 86 mV/decade) and transconductance (higher than four times the value in SG SWCNTFETs). The experimental data and the difference between SG and DG modes are explained. The double-gate suspended-body CNTFETs hold promise for bottom-up fabrication of resonant nano-electro-mechanical-systems (NEMS) devices, such as tunable/switchable resonators for sensing and radio-frequency (RF) applications.
{"title":"Self-aligned double-gate suspended-body single-walled carbon nanotube field-effect-transistors","authors":"Ji Cao, A. Ionescu","doi":"10.1109/ESSDERC.2011.6044171","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044171","url":null,"abstract":"Self-aligned suspended-body single-walled carbon nanotube field-effect-transistors (SWCNT FETs) have been demonstrated with efficient and independent electrostatic control by two laterally placed independent gates spaced less than 100 nm away from the CNT channel. The operation of the suspended-body SWCNTFETs, in double-gate (DG) mode and single-gate (SG) mode, is analyzed in detail. Strong interface coupling of the double gates and tuning of the second independent gate (linear threshold voltage variation, constant subthreshold swing), are typical effects in these suspended-body SWCNTFETs. The comparison of SG and DG operations demonstrates the superiority of DG SWCNTFETs: remarkably improved subthreshold slope (from 130 mV/decade to 86 mV/decade) and transconductance (higher than four times the value in SG SWCNTFETs). The experimental data and the difference between SG and DG modes are explained. The double-gate suspended-body CNTFETs hold promise for bottom-up fabrication of resonant nano-electro-mechanical-systems (NEMS) devices, such as tunable/switchable resonators for sensing and radio-frequency (RF) applications.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128436224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044214
Takashi Sato, Tadamichi Kozaki, T. Uezono, Hiroshi Tsutsui, H. Ochi
A device array suitable for efficiently collecting statistical information on bias-temperature instability (BTI) parameters of a large number of transistors is presented. The proposed array structure substantially shortens measurement time of threshold voltage shifts under BTI conditions by parallelizing stress periods of multiple devices while maintaining 0.2mV precision. An implementation of BTI array consisting of 128 devices successfully validates stress-pipelining concept. Log-normal distributions of time exponents are experimentally observed.
{"title":"A device array for efficient bias-temperature instability measurements","authors":"Takashi Sato, Tadamichi Kozaki, T. Uezono, Hiroshi Tsutsui, H. Ochi","doi":"10.1109/ESSDERC.2011.6044214","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044214","url":null,"abstract":"A device array suitable for efficiently collecting statistical information on bias-temperature instability (BTI) parameters of a large number of transistors is presented. The proposed array structure substantially shortens measurement time of threshold voltage shifts under BTI conditions by parallelizing stress periods of multiple devices while maintaining 0.2mV precision. An implementation of BTI array consisting of 128 devices successfully validates stress-pipelining concept. Log-normal distributions of time exponents are experimentally observed.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125409926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044191
M. Shayesteh, C. Daunt, D. O'Connell, V. Djara, M. White, B. Long, R. Duffy
The authors extract contact resistivity of NiGe layers on phosphorus-doped and arsenic-doped germanium, using the Transfer Length Method. It is shown experimentally that higher implant dose yields lower contact resistivity. Furthermore phosphorus is a better choice of dopant in terms of contact resistance and sheet resistance at low activation anneal temperatures, such as 500 °C. The impact of high contact resistance is evaluated for 22 nm technology NMOS germanium devices and beyond.
{"title":"N-type doped germanium contact resistance extraction and evaluation for advanced devices","authors":"M. Shayesteh, C. Daunt, D. O'Connell, V. Djara, M. White, B. Long, R. Duffy","doi":"10.1109/ESSDERC.2011.6044191","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044191","url":null,"abstract":"The authors extract contact resistivity of NiGe layers on phosphorus-doped and arsenic-doped germanium, using the Transfer Length Method. It is shown experimentally that higher implant dose yields lower contact resistivity. Furthermore phosphorus is a better choice of dopant in terms of contact resistance and sheet resistance at low activation anneal temperatures, such as 500 °C. The impact of high contact resistance is evaluated for 22 nm technology NMOS germanium devices and beyond.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122475991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044169
S. Breitkreutz, J. Kiermaier, X. Ju, G. Csaba, D. Schmitt-Landsiedel, M. Becherer
In Nanomagnetic Logic (NML), computing operations are performed by non-volatile, field-coupled nanomagnets. For information propagation in nanomagnetic wires between logic gates, directed signal flow has to be implemented in the field-coupled devices. In this paper we present the solution for directed information propagation in a wire realized in NML with perpendicular magnetization. For the first time, non-reciprocal signal flow is experimentally demonstrated for field-coupled nanomagnets and homogeneous clocking fields. Micromagnetic simulations are performed and field-coupled nanomagnets are fabricated by focused ion beam (FIB) lithography and ion beam etching. Partial irradiation with a FIB is investigated to tailor the switching behavior of the nanomagnets. Three coupled nano-magnets in a wire are measured to verify the simulation results. Non-reciprocal field-coupling of the nanomagnets is proven by experiments within a nanomagnetic wire.
{"title":"Nanomagnetic Logic: Demonstration of directed signal flow for field-coupled computing devices","authors":"S. Breitkreutz, J. Kiermaier, X. Ju, G. Csaba, D. Schmitt-Landsiedel, M. Becherer","doi":"10.1109/ESSDERC.2011.6044169","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044169","url":null,"abstract":"In Nanomagnetic Logic (NML), computing operations are performed by non-volatile, field-coupled nanomagnets. For information propagation in nanomagnetic wires between logic gates, directed signal flow has to be implemented in the field-coupled devices. In this paper we present the solution for directed information propagation in a wire realized in NML with perpendicular magnetization. For the first time, non-reciprocal signal flow is experimentally demonstrated for field-coupled nanomagnets and homogeneous clocking fields. Micromagnetic simulations are performed and field-coupled nanomagnets are fabricated by focused ion beam (FIB) lithography and ion beam etching. Partial irradiation with a FIB is investigated to tailor the switching behavior of the nanomagnets. Three coupled nano-magnets in a wire are measured to verify the simulation results. Non-reciprocal field-coupling of the nanomagnets is proven by experiments within a nanomagnetic wire.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131299956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044159
A. Abuelgasim, Kanad Mallik, C. D. de Groot, P. Ashburn
We show that deep level doping of Czochralski-grown silicon wafers is capable of providing very high resistivity wafers suitable for integrated passive devices and 3D integration. Starting from n-type Czochralski silicon wafers having a nominal resistivity of 50 Ωcm, we use Au ion implantation to increase the resistivity. Coplanar waveguides fabricated on the wafers show strongly reduced attenuation. Hall measurements indicate that the increase in resistivity is clearly due to a reduction in free carriers. The temperature dependence of the free carrier concentration in the range of 200–350K indicates that the Fermi-level is virtually pinned mid-gap.
{"title":"Gold-doped high resistivity Czochralski-silicon for integrated passive devices and 3D integration","authors":"A. Abuelgasim, Kanad Mallik, C. D. de Groot, P. Ashburn","doi":"10.1109/ESSDERC.2011.6044159","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044159","url":null,"abstract":"We show that deep level doping of Czochralski-grown silicon wafers is capable of providing very high resistivity wafers suitable for integrated passive devices and 3D integration. Starting from n-type Czochralski silicon wafers having a nominal resistivity of 50 Ωcm, we use Au ion implantation to increase the resistivity. Coplanar waveguides fabricated on the wafers show strongly reduced attenuation. Hall measurements indicate that the increase in resistivity is clearly due to a reduction in free carriers. The temperature dependence of the free carrier concentration in the range of 200–350K indicates that the Fermi-level is virtually pinned mid-gap.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116043975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSCIRC.2011.6044912
M. Steyaert, T. V. Breussegem, H. Meyvaert, P. Callemeyn, M. Wens
Monolithic integration of electronic systems is one of the major techniques to reduce cost, size and power consumption in state-of-the-art consumer applications. Integration of transceivers and other mixed-signal building blocks has proven to be a very successful approach to build low cost, compact and portable systems [1]. Remarkably a certain building block remains discrete in commercial applications: the switched-power supply. This paper will demonstrate how recent research efforts cleared the path to develop fully integrated DC-DC converters in standard CMOS.
{"title":"DC-DC converters: From discrete towards fully integrated CMOS","authors":"M. Steyaert, T. V. Breussegem, H. Meyvaert, P. Callemeyn, M. Wens","doi":"10.1109/ESSCIRC.2011.6044912","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2011.6044912","url":null,"abstract":"Monolithic integration of electronic systems is one of the major techniques to reduce cost, size and power consumption in state-of-the-art consumer applications. Integration of transceivers and other mixed-signal building blocks has proven to be a very successful approach to build low cost, compact and portable systems [1]. Remarkably a certain building block remains discrete in commercial applications: the switched-power supply. This paper will demonstrate how recent research efforts cleared the path to develop fully integrated DC-DC converters in standard CMOS.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125908975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-13DOI: 10.1109/ESSDERC.2011.6044201
A. Maconi, A. Arreghini, C. M. Compagnoni, G. Van den bosch, A. Spinelli, J. van Houdt, A. Lacaita
This paper investigates the impact of lateral charge migration on the retention performance of charge-trap memories whose storage layer is not patterned self-aligned with the channel area of each cell. Experimental results on planar SONOS devices, revealing an important contribution of lateral charge migration at 150 °C, are used to calibrate a new numerical model accounting for both the vertical and the lateral charge loss from the silicon nitride. Modeling results allow a detailed analysis of the retention transients of both planar and 3D SONOS arrays, evaluating, for the latter, the minimum dimensions needed to fulfill the retention requirements at 85 °C.
{"title":"Impact of lateral charge migration on the retention performance of planar and 3D SONOS devices","authors":"A. Maconi, A. Arreghini, C. M. Compagnoni, G. Van den bosch, A. Spinelli, J. van Houdt, A. Lacaita","doi":"10.1109/ESSDERC.2011.6044201","DOIUrl":"https://doi.org/10.1109/ESSDERC.2011.6044201","url":null,"abstract":"This paper investigates the impact of lateral charge migration on the retention performance of charge-trap memories whose storage layer is not patterned self-aligned with the channel area of each cell. Experimental results on planar SONOS devices, revealing an important contribution of lateral charge migration at 150 °C, are used to calibrate a new numerical model accounting for both the vertical and the lateral charge loss from the silicon nitride. Modeling results allow a detailed analysis of the retention transients of both planar and 3D SONOS arrays, evaluating, for the latter, the minimum dimensions needed to fulfill the retention requirements at 85 °C.","PeriodicalId":161896,"journal":{"name":"2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126498756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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