Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984802
J. Tay, J. Cheah, Q. Liu, C. Gan
Data are stored as electrical charges in floating gates of the transistors in Non-Volatile Memory (NVM) devices. Reading back this stored data will help in understanding how memory is organized which is important in the digital forensics field. Sample preparation from back-side approach had been attempted and scanning capacitance microscopy (SCM) can be used to probe the charges stored in the floating gate transistors directly. However, it is challenging to attain a uniform surface across the memory device using mechanical polishing and also difficult to read back the full data. In this paper, front-side sample preparation will be discussed for data retrieval with SCM probing method. The application has been demonstrated on 8-bit microcontroller with 16 KB ISP flash memory and 512 bytes EEPROM.
{"title":"Study of Front-Side Approach to Retrieve Stored Data in Non-Volatile Memory Devices Using Scanning Capacitance Microscopy","authors":"J. Tay, J. Cheah, Q. Liu, C. Gan","doi":"10.1109/IPFA47161.2019.8984802","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984802","url":null,"abstract":"Data are stored as electrical charges in floating gates of the transistors in Non-Volatile Memory (NVM) devices. Reading back this stored data will help in understanding how memory is organized which is important in the digital forensics field. Sample preparation from back-side approach had been attempted and scanning capacitance microscopy (SCM) can be used to probe the charges stored in the floating gate transistors directly. However, it is challenging to attain a uniform surface across the memory device using mechanical polishing and also difficult to read back the full data. In this paper, front-side sample preparation will be discussed for data retrieval with SCM probing method. The application has been demonstrated on 8-bit microcontroller with 16 KB ISP flash memory and 512 bytes EEPROM.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115690892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/ipfa47161.2019.8984796
{"title":"IPFA 2019 Cover Page","authors":"","doi":"10.1109/ipfa47161.2019.8984796","DOIUrl":"https://doi.org/10.1109/ipfa47161.2019.8984796","url":null,"abstract":"","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"59 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128343215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984844
Tan Hk, Liu Bh, Chooi Ml, Hua Yn, Lin Xm
As technology scales, transmission electron microscope (TEM) has become one of the most widely used analysis tool in characterization and failure analysis. This paper introduces techniques on ensuring electron transparency for TEM analysis using secondary electron emission, backscatter electron emission and X-ray emission, all of which could be found within a scanning electron microscope (SEM) system.
{"title":"Study of Silicon thickness for electron transparency","authors":"Tan Hk, Liu Bh, Chooi Ml, Hua Yn, Lin Xm","doi":"10.1109/IPFA47161.2019.8984844","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984844","url":null,"abstract":"As technology scales, transmission electron microscope (TEM) has become one of the most widely used analysis tool in characterization and failure analysis. This paper introduces techniques on ensuring electron transparency for TEM analysis using secondary electron emission, backscatter electron emission and X-ray emission, all of which could be found within a scanning electron microscope (SEM) system.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"46 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120851164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984842
Zhendong Jiang, H. Kwok, Meng Zhang, Xiaotong Ma, Yan Yan, Guijun Li, Sunbin Deng, Wei Zhou, Rongsheng Chen, M. Wong
In this paper, the effect of active layer (AC) thickness on the device performance and hot carrier (HC) instability of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) based on metal induced crystallization (MIC) is investigated. The thinner AC thickness of MIC poly-Si TFTs brings better device performance and HC instability, which may be respectively attributed to the better gate control to the active channel and different electric field distributions in the active channel and gate oxide.
{"title":"Effect of Active Layer Thickness on Device Performance and Hot Carrier Instability in Metal Induced Crystallized Polycrystalline Silicon Thin-Film Transistors","authors":"Zhendong Jiang, H. Kwok, Meng Zhang, Xiaotong Ma, Yan Yan, Guijun Li, Sunbin Deng, Wei Zhou, Rongsheng Chen, M. Wong","doi":"10.1109/IPFA47161.2019.8984842","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984842","url":null,"abstract":"In this paper, the effect of active layer (AC) thickness on the device performance and hot carrier (HC) instability of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) based on metal induced crystallization (MIC) is investigated. The thinner AC thickness of MIC poly-Si TFTs brings better device performance and HC instability, which may be respectively attributed to the better gate control to the active channel and different electric field distributions in the active channel and gate oxide.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123968453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984840
Hongjian Wang, Liyuan Liu, Zeya Peng, Youliang Wang
Nowadays, with the products and systems becomes more complex, it will be more difficulty to process the failure analysis in the dependability. Besides we can see the great progress in the field of machine learning, and the joint applications of machine learning and other fields are becoming more widespread. In this paper we propose a new function which combine the expert system and Bayesian networks to failure analysis. This method starts with data mining which will collect the clear, complete data to a data warehouse. Then it takes advantage of the Fault Tree and mapping it to Bayesian networks. At last we use the Bayesian networks and the statistical data to compute the probability of the failure in order to take analysis. We give an example to explain how this model works, and it will get a well performance because of it uses the data from failure cases and other related data.
{"title":"An overview of failure analysis expert system based on Bayesian networks","authors":"Hongjian Wang, Liyuan Liu, Zeya Peng, Youliang Wang","doi":"10.1109/IPFA47161.2019.8984840","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984840","url":null,"abstract":"Nowadays, with the products and systems becomes more complex, it will be more difficulty to process the failure analysis in the dependability. Besides we can see the great progress in the field of machine learning, and the joint applications of machine learning and other fields are becoming more widespread. In this paper we propose a new function which combine the expert system and Bayesian networks to failure analysis. This method starts with data mining which will collect the clear, complete data to a data warehouse. Then it takes advantage of the Fault Tree and mapping it to Bayesian networks. At last we use the Bayesian networks and the statistical data to compute the probability of the failure in order to take analysis. We give an example to explain how this model works, and it will get a well performance because of it uses the data from failure cases and other related data.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115222146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984815
Xintong Zhu, Xiaoxuan Li, R. R. Nistala, Zishan Ali, Lulu Peng, L. Selvaraj, Chor Shu Cheng, Z. Mo
In this study, soft magnetic thin films including Co-Zr-Ta (CZT) and its variant are deposited on TEOS SiO2 and polyimide to characterize the interfacial adhesion strength of the full magnetic stack using the 4-Point-Bending (4PB) technique. Variation in critical load value Gc, an indicator of the interfacial adhesion strength, is observed. Auger Electron Spectroscopy (AES) is performed for elemental analysis to confirm the interface of de-lamination.
{"title":"4-Point-Bending Characterization of Interfacial Adhesion Strength of Co-Zr-Ta and Co-Zr-Ta Variant Thin-Film Stacks","authors":"Xintong Zhu, Xiaoxuan Li, R. R. Nistala, Zishan Ali, Lulu Peng, L. Selvaraj, Chor Shu Cheng, Z. Mo","doi":"10.1109/IPFA47161.2019.8984815","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984815","url":null,"abstract":"In this study, soft magnetic thin films including Co-Zr-Ta (CZT) and its variant are deposited on TEOS SiO2 and polyimide to characterize the interfacial adhesion strength of the full magnetic stack using the 4-Point-Bending (4PB) technique. Variation in critical load value Gc, an indicator of the interfacial adhesion strength, is observed. Auger Electron Spectroscopy (AES) is performed for elemental analysis to confirm the interface of de-lamination.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115496087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984835
Masayuki Kobayashi, K. Sakai, Kenta Sumikawa, O. Kikuchi
It is common to apply scanning acoustic tomography (SAT) for microelectronic packages inspection because it enables nondestructive imaging of defects. SAT phase inversion imaging is useful tool for detecting defect areas accurately and quickly. Phase inversion imaging is based on the phenomenon of the phase inversion of an ultrasound wave at interfaces in a sample. We propose a signal processing method for phase inversion imaging. Specifically, it is a robust method of finding the phase inversion. With this method, the phase inversion is found by estimating the correlation between a reflected wave signal of a sample and reference wave signal. A negative correlation between these signals indicates the existence of defects in the sample. Defect detection tests with the proposed method were carried out using integrated circuit packages. The tests results indicate that the proposed method improves robustness for detecting defects compared with a conventional method. The tests also demonstrated that small defects on the order of 100 micrometers could be detected using an ultrasound probe with a nominal frequency of 75 MHz.
{"title":"Signal Processing Method for Scanning-Acoustic-Tomography Defect Detection based on Correlation between Ultrasound Waveforms","authors":"Masayuki Kobayashi, K. Sakai, Kenta Sumikawa, O. Kikuchi","doi":"10.1109/IPFA47161.2019.8984835","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984835","url":null,"abstract":"It is common to apply scanning acoustic tomography (SAT) for microelectronic packages inspection because it enables nondestructive imaging of defects. SAT phase inversion imaging is useful tool for detecting defect areas accurately and quickly. Phase inversion imaging is based on the phenomenon of the phase inversion of an ultrasound wave at interfaces in a sample. We propose a signal processing method for phase inversion imaging. Specifically, it is a robust method of finding the phase inversion. With this method, the phase inversion is found by estimating the correlation between a reflected wave signal of a sample and reference wave signal. A negative correlation between these signals indicates the existence of defects in the sample. Defect detection tests with the proposed method were carried out using integrated circuit packages. The tests results indicate that the proposed method improves robustness for detecting defects compared with a conventional method. The tests also demonstrated that small defects on the order of 100 micrometers could be detected using an ultrasound probe with a nominal frequency of 75 MHz.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984818
Chng Kheaw Chung, Chew Su Fang, C. Keng, Xueren Zhang
Flip chip ball grid array (FCBGA) packages is becoming more attractive for automotive applications driven by the high performance requirement. Stacked vias are widely used in FCBGA substrate due to higher routing request. The reliability of stacked vias is challenging when the package is working under harsh environments, especially for automotive application. In this paper, the crack issue of stack VIAs encountered during product qualification will be presented. Failure analysis has been done to identify the failure, 3D finite element (FEM) simulation has been carried out to understand the mechanism and to provide guidance of improvement. Solutions has been implemented in the new substrate, and the product has been qualified successfully for automotive application.
{"title":"Robust Package Development for Automotive Application","authors":"Chng Kheaw Chung, Chew Su Fang, C. Keng, Xueren Zhang","doi":"10.1109/IPFA47161.2019.8984818","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984818","url":null,"abstract":"Flip chip ball grid array (FCBGA) packages is becoming more attractive for automotive applications driven by the high performance requirement. Stacked vias are widely used in FCBGA substrate due to higher routing request. The reliability of stacked vias is challenging when the package is working under harsh environments, especially for automotive application. In this paper, the crack issue of stack VIAs encountered during product qualification will be presented. Failure analysis has been done to identify the failure, 3D finite element (FEM) simulation has been carried out to understand the mechanism and to provide guidance of improvement. Solutions has been implemented in the new substrate, and the product has been qualified successfully for automotive application.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122539391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984853
Y. Ni, Liuan Li, Liang He, Yang Liu
In this paper, we evaluated the effect of carbon doping on the breakdown mechanism of GaN buffer as well as the material and electrical properties of AlGaN/GaN HFETs. The introduction of carbon will slightly increase the surface roughness and degrade the 2DEG carrier density, while leakage current (breakdown voltage) can be suppressed (enhanced) significantly (346 V@1 μA/mm and 748 V@1 mA/mm). Leakage current of GaN can be explained using trap charge limited space-charge limited current (SCLC) model and shows an obvious dependency on carbon concentration. The transient drain current measurements demonstrate that the traps in the unintentional doped GaN buffer are mainly acceptor traps (CN) with an energy level of EV+538 meV, while both acceptor and donor traps (CGa with an energy level of EC-600 meV) coexist in the carbon doped GaN buffer layer.
{"title":"Breakdown Mechanism of AlGaN/GaN-based HFET With Carbon-doped GaN Buffer Layer grown on Si substrate","authors":"Y. Ni, Liuan Li, Liang He, Yang Liu","doi":"10.1109/IPFA47161.2019.8984853","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984853","url":null,"abstract":"In this paper, we evaluated the effect of carbon doping on the breakdown mechanism of GaN buffer as well as the material and electrical properties of AlGaN/GaN HFETs. The introduction of carbon will slightly increase the surface roughness and degrade the 2DEG carrier density, while leakage current (breakdown voltage) can be suppressed (enhanced) significantly (346 V@1 μA/mm and 748 V@1 mA/mm). Leakage current of GaN can be explained using trap charge limited space-charge limited current (SCLC) model and shows an obvious dependency on carbon concentration. The transient drain current measurements demonstrate that the traps in the unintentional doped GaN buffer are mainly acceptor traps (CN) with an energy level of EV+538 meV, while both acceptor and donor traps (CGa with an energy level of EC-600 meV) coexist in the carbon doped GaN buffer layer.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1814 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129718310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-07-01DOI: 10.1109/IPFA47161.2019.8984766
Nanditha P. Rao, M. Desai
A soft error is typically modeled as a probabilistic single bit-flip model. In such models, an important issue to consider is the likelihood of multiple errors. The fact that a particle strike causes multiple flips is noted in the literature. We use post-layout circuit simulations to characterize the impact of a single event transient (SET) on logic circuits and quantify the likelihood of multiple flips. We find that the impact of an SET needs to be viewed across two clock cycles and a good fraction of errors had multiple register flips. A key observation is that, amongst the erroneous outcomes, the probability of multiple flips for ‘gate-strike’ cases was substantial and went up to 50%, where as those for ‘register-strike’ cases was only 2%. This implies that, even if we were to eliminate the flips due to register strikes using robust flip-flop designs, a large fraction of the remaining flips (due to gate strikes) is likely to be multiple flips. Further, when a strike affected two nearby transistors, we saw an increase of a factor of 2x in multiple flip probability. It is also likely that two SETs merge to produce a wider SET, thus increasing its probability of getting captured. This implies that, existing fault tolerant latch designs may need to be revisited to handle such scenarios.
{"title":"The likelihood of multiple bit-flips due to neutron strikes and its implications on circuit designs","authors":"Nanditha P. Rao, M. Desai","doi":"10.1109/IPFA47161.2019.8984766","DOIUrl":"https://doi.org/10.1109/IPFA47161.2019.8984766","url":null,"abstract":"A soft error is typically modeled as a probabilistic single bit-flip model. In such models, an important issue to consider is the likelihood of multiple errors. The fact that a particle strike causes multiple flips is noted in the literature. We use post-layout circuit simulations to characterize the impact of a single event transient (SET) on logic circuits and quantify the likelihood of multiple flips. We find that the impact of an SET needs to be viewed across two clock cycles and a good fraction of errors had multiple register flips. A key observation is that, amongst the erroneous outcomes, the probability of multiple flips for ‘gate-strike’ cases was substantial and went up to 50%, where as those for ‘register-strike’ cases was only 2%. This implies that, even if we were to eliminate the flips due to register strikes using robust flip-flop designs, a large fraction of the remaining flips (due to gate strikes) is likely to be multiple flips. Further, when a strike affected two nearby transistors, we saw an increase of a factor of 2x in multiple flip probability. It is also likely that two SETs merge to produce a wider SET, thus increasing its probability of getting captured. This implies that, existing fault tolerant latch designs may need to be revisited to handle such scenarios.","PeriodicalId":169775,"journal":{"name":"2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"1935 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128993477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：