Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551626
L. P. Tatum, Madeline Sciullo, M. Law
In this work, we present a 2-Valley energy band model of electron transport that delivers more accurate solutions compared with the Farahmand model but with improved convergence and a faster solution time for very high electric fields. This was achieved by implementing the Fermi-Dirac integral distribution as a substitution for the Boltzmann exponential, electron carrier temperature due to heat generation and conduction in the semiconductor lattice, and additional electron concentration modeling for a second conduction energy band minima. The model was primarily tuned by varying the electron temperature relaxation time constant. It was tested using a GaN-based High Electron Mobility Transistor using the Finite-Element Quasi Fermi method.
{"title":"Simulation of Hot-Electron Effects with Multi-band Semiconductor Devices","authors":"L. P. Tatum, Madeline Sciullo, M. Law","doi":"10.1109/SISPAD.2018.8551626","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551626","url":null,"abstract":"In this work, we present a 2-Valley energy band model of electron transport that delivers more accurate solutions compared with the Farahmand model but with improved convergence and a faster solution time for very high electric fields. This was achieved by implementing the Fermi-Dirac integral distribution as a substitution for the Boltzmann exponential, electron carrier temperature due to heat generation and conduction in the semiconductor lattice, and additional electron concentration modeling for a second conduction energy band minima. The model was primarily tuned by varying the electron temperature relaxation time constant. It was tested using a GaN-based High Electron Mobility Transistor using the Finite-Element Quasi Fermi method.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114646656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551663
T. Nishimatsu, A. Payet, Byounghak Lee, Yasuyuki Kayama, Kiyoshi Ishikawa, Alexander Schmidt, I. Jang, Dae Sin Kim
A new dynamical space partitioning method is presented in a parallelized lattice kinetic Monte Carlo (kMC) simulator to overcome the loss of parallel efficiency found in other parallelized kMC simulators. The dynamical partitioning of the simulation cell allows better load balancing through all threads hence reducing time consuming events during the simulation. The new method is evaluated against both hypothetical and real cases. In both cases, minimal differences between serial and parallelized simulations are found. In real cases, other code optimizations may be needed to further improve the parallel efficiency.
{"title":"Dynamical space partitioning for acceleration of parallelized lattice kinetic Monte Carlo simulations","authors":"T. Nishimatsu, A. Payet, Byounghak Lee, Yasuyuki Kayama, Kiyoshi Ishikawa, Alexander Schmidt, I. Jang, Dae Sin Kim","doi":"10.1109/SISPAD.2018.8551663","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551663","url":null,"abstract":"A new dynamical space partitioning method is presented in a parallelized lattice kinetic Monte Carlo (kMC) simulator to overcome the loss of parallel efficiency found in other parallelized kMC simulators. The dynamical partitioning of the simulation cell allows better load balancing through all threads hence reducing time consuming events during the simulation. The new method is evaluated against both hypothetical and real cases. In both cases, minimal differences between serial and parallelized simulations are found. In real cases, other code optimizations may be needed to further improve the parallel efficiency.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123668335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551633
N. Rostand, S. Martinie, J. Lacord, O. Rozeau, O. Billoint, J. Barbe, T. Poiroux, G. Hubert
Single Event Transients (SET) are important issues concerning reliability of CMOS circuits. They lead to occurrence of soft errors in integrated circuits, such as Single Event Upset (SEU) which consists in unexpected bit state switch in SRAM cells [1], [2]. We can find models which describe SET in literature [1], [5] but they are not compact (i e. physical model implemented in Verilog-A). In previous work [6], we proposed a theoretical SET model but the implementation in Verilog-A was still challenging. Here, we describe the implementation in Verilog-A of this model and use it through standard SPICE simulations to study the effect of SET on SRAM cell and shift register.
{"title":"Compact Modelling of Single Event Transient in Bulk MOSFET for SPICE: Application to Elementary Circuit","authors":"N. Rostand, S. Martinie, J. Lacord, O. Rozeau, O. Billoint, J. Barbe, T. Poiroux, G. Hubert","doi":"10.1109/SISPAD.2018.8551633","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551633","url":null,"abstract":"Single Event Transients (SET) are important issues concerning reliability of CMOS circuits. They lead to occurrence of soft errors in integrated circuits, such as Single Event Upset (SEU) which consists in unexpected bit state switch in SRAM cells [1], [2]. We can find models which describe SET in literature [1], [5] but they are not compact (i e. physical model implemented in Verilog-A). In previous work [6], we proposed a theoretical SET model but the implementation in Verilog-A was still challenging. Here, we describe the implementation in Verilog-A of this model and use it through standard SPICE simulations to study the effect of SET on SRAM cell and shift register.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123922363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551642
N. Prasad, S. Banerjee, L. Register
Interlayer tunnel field effect transistors (ITFETs) make use of resonant tunneling between two layers of two-dimensional semiconductors to create a negative differential resistance. A narrow resonance allows for lowering the operating voltages in potential circuit applications. The use of multiple tunnel barriers is investigated as a means to obtain a narrow resonance, as the device dimensions are scaled down. For specificity, we analyze a bilayer graphene-based ITFET system.
{"title":"Enhancement of Resonance by the Use of Multiple Tunnel Barriers in Bilayer Graphene-Based Interlayer Tunnel Field Effect Transistors","authors":"N. Prasad, S. Banerjee, L. Register","doi":"10.1109/SISPAD.2018.8551642","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551642","url":null,"abstract":"Interlayer tunnel field effect transistors (ITFETs) make use of resonant tunneling between two layers of two-dimensional semiconductors to create a negative differential resistance. A narrow resonance allows for lowering the operating voltages in potential circuit applications. The use of multiple tunnel barriers is investigated as a means to obtain a narrow resonance, as the device dimensions are scaled down. For specificity, we analyze a bilayer graphene-based ITFET system.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"30 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123532581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551713
K. Sheikh, Lan Wei
A systematic methodology is presented to generate approximate circuits with fewer nodes and shorter paths to reduce process induced degradation due to imperfect process in emerging technologies such as CNFET. In a 16-bit CNFET adder example, at PCNTopen =5%, two resulted approximate adders achieve 80.5% and 90.2% circuit-level pass rate with a penalty of 3.3% and 24.0% in relative logic error, respectively, in comparison with 12.5% pass rate for the precision counterpart. The study paves the path to practically utilize such technology for error-resilient applications.
{"title":"Methodology to Generate Approximate Circuits to Reduce Process Induced Degradation in CNFET Based Circuits","authors":"K. Sheikh, Lan Wei","doi":"10.1109/SISPAD.2018.8551713","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551713","url":null,"abstract":"A systematic methodology is presented to generate approximate circuits with fewer nodes and shorter paths to reduce process induced degradation due to imperfect process in emerging technologies such as CNFET. In a 16-bit CNFET adder example, at PCNTopen =5%, two resulted approximate adders achieve 80.5% and 90.2% circuit-level pass rate with a penalty of 3.3% and 24.0% in relative logic error, respectively, in comparison with 12.5% pass rate for the precision counterpart. The study paves the path to practically utilize such technology for error-resilient applications.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125239976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551723
U. Kwon, T. Okagaki, Young-seok Song, Sungyeol Kim, Yohan Kim, Minkyoung Kim, A. Kim, Saetbyeol Ahn, Jihye Shin, Yonghee Park, Jongchol Kim, D. Kim, Weiyi Qi, Yang Lu, Nuo Xu, Hong-hyun Park, J. Wang, W. Choi
Intelligent design technology co-optimization (iDTCO) methodology for next generation logic architecture pathfinding and its application results are presented in this paper. There are 2 major steps in our iDTCO framework; standard cell (STC)-level iDTCO and block-level iDTCO. STC-level iDTCO, the main focus of this paper, consists of 4 major components; (1) full 3D process emulation with litho contour of standard cell (STC) layout, (2) auto-extraction of transistor compact model & parasitic RC extraction (PEX) in 3D, (3) performance-power-yield (PPY) analyzer, (4) multi-objective optimization of layout & process assumption (PA) to get best PPY. Applying our STC-level iDTCO flow to logic arch pathfinding, we could speed up our PPY analysis TAT by 5$sim$10 times with good accuracy of >95%.
{"title":"Intelligent DTCO (iDTCO) for next generation logic path-finding","authors":"U. Kwon, T. Okagaki, Young-seok Song, Sungyeol Kim, Yohan Kim, Minkyoung Kim, A. Kim, Saetbyeol Ahn, Jihye Shin, Yonghee Park, Jongchol Kim, D. Kim, Weiyi Qi, Yang Lu, Nuo Xu, Hong-hyun Park, J. Wang, W. Choi","doi":"10.1109/SISPAD.2018.8551723","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551723","url":null,"abstract":"Intelligent design technology co-optimization (iDTCO) methodology for next generation logic architecture pathfinding and its application results are presented in this paper. There are 2 major steps in our iDTCO framework; standard cell (STC)-level iDTCO and block-level iDTCO. STC-level iDTCO, the main focus of this paper, consists of 4 major components; (1) full 3D process emulation with litho contour of standard cell (STC) layout, (2) auto-extraction of transistor compact model & parasitic RC extraction (PEX) in 3D, (3) performance-power-yield (PPY) analyzer, (4) multi-objective optimization of layout & process assumption (PA) to get best PPY. Applying our STC-level iDTCO flow to logic arch pathfinding, we could speed up our PPY analysis TAT by 5$sim$10 times with good accuracy of >95%.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129033122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551709
Nianduan Lu, Wei Wei, X. Chuai, Yuhan Mei, Ling Li, Ming Liu
Based on the first-principles calculations, we have investigated the structure and electronic property of adsorbed small-molecules on boron nitride nanotubes (BNNTs). It is found thatthe sites of LUMO and HOMO would be changed after BNNTs absorbed the different small moleculesThe energy gap of BNNTs decreases with increasing the distance between small molecule and BNNTThe adsorption effect of BNNT will be optimal as the distance between the small molecule and BNNT is from 1 to 1.5 Å. The potential application of BNNT as highly sensitive gas sensor for N-based small molecules has also been discussed.
{"title":"Investigation of adsorbed small-molecule on boron nitride nanotube (BNNT) based on first-principles calculations","authors":"Nianduan Lu, Wei Wei, X. Chuai, Yuhan Mei, Ling Li, Ming Liu","doi":"10.1109/SISPAD.2018.8551709","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551709","url":null,"abstract":"Based on the first-principles calculations, we have investigated the structure and electronic property of adsorbed small-molecules on boron nitride nanotubes (BNNTs). It is found thatthe sites of LUMO and HOMO would be changed after BNNTs absorbed the different small moleculesThe energy gap of BNNTs decreases with increasing the distance between small molecule and BNNTThe adsorption effect of BNNT will be optimal as the distance between the small molecule and BNNT is from 1 to 1.5 Å. The potential application of BNNT as highly sensitive gas sensor for N-based small molecules has also been discussed.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130266986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551641
J. Duarte, Y.-K. Lin, Y. Liao, A. Sachid, M. Kao, H. Agarwal, P. Kushwaha, K. Chatterjee, D. Kwon, H.-L. Chang, S. Salahuddin, C. Hu
A complete simulation framework is presented for Negative Capacitance FinFETs including Numerical Simulation, Compact Modeling, and Circuit Evaluation. A 2D Numerical Simulation for FinFETs coupled with the Landau’s Ferroelectric Model captures device characteristics. A new version of the distributed Negative-Capacitance FinFET Compact Model is also presented in this work, where influence of short-channel effects in Ferroelectric voltage amplification are newly incorporated. Finally, a detailed analysis, from an energy perspective, is presented for the gate voltage amplification of Negative Capacitance FinFETs in ring-oscillator circuits.
{"title":"Negative-Capacitance FinFETs: Numerical Simulation, Compact Modeling and Circuit Evaluation","authors":"J. Duarte, Y.-K. Lin, Y. Liao, A. Sachid, M. Kao, H. Agarwal, P. Kushwaha, K. Chatterjee, D. Kwon, H.-L. Chang, S. Salahuddin, C. Hu","doi":"10.1109/SISPAD.2018.8551641","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551641","url":null,"abstract":"A complete simulation framework is presented for Negative Capacitance FinFETs including Numerical Simulation, Compact Modeling, and Circuit Evaluation. A 2D Numerical Simulation for FinFETs coupled with the Landau’s Ferroelectric Model captures device characteristics. A new version of the distributed Negative-Capacitance FinFET Compact Model is also presented in this work, where influence of short-channel effects in Ferroelectric voltage amplification are newly incorporated. Finally, a detailed analysis, from an energy perspective, is presented for the gate voltage amplification of Negative Capacitance FinFETs in ring-oscillator circuits.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125870968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551707
C. Medina-Bailón, C. Sampedro, J. Padilla, A. Godoy, L. Donetti, V. Georgiev, F. Gámiz, A. Asenov
As device dimensions are scaled down, the use of strained channels as performance booster becomes of special relevance. Moreover, the inclusion of quantum effects in the transport direction is imperative to predict the performance of future transistors. In particular, Source-to-Drain tunneling (S/D tunneling) is presented as a scaling limit in sub-10nm nodes. In this work, a Multi-Subband Ensemble Monte Carlo (MS-EMC) study of the impact of S/D tunneling in relaxed and biaxially strained channel FinFETs is presented.
{"title":"Impact of Strain on S/D tunneling in FinFETs: a MS-EMC study","authors":"C. Medina-Bailón, C. Sampedro, J. Padilla, A. Godoy, L. Donetti, V. Georgiev, F. Gámiz, A. Asenov","doi":"10.1109/SISPAD.2018.8551707","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551707","url":null,"abstract":"As device dimensions are scaled down, the use of strained channels as performance booster becomes of special relevance. Moreover, the inclusion of quantum effects in the transport direction is imperative to predict the performance of future transistors. In particular, Source-to-Drain tunneling (S/D tunneling) is presented as a scaling limit in sub-10nm nodes. In this work, a Multi-Subband Ensemble Monte Carlo (MS-EMC) study of the impact of S/D tunneling in relaxed and biaxially strained channel FinFETs is presented.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126822338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551653
F. T. Wakam, J. Lacord, M. Bawedin, S. Martinie, S. Cristoloveanu, J. Barbe
For the first time, we demonstrate a new concept for programming the ‘1’ state in A2RAM based on the impact ionization in the bridge, which can be assisted by the band-to-band tunneling effect in the top part of the silicon film. This new programming method reduces the programming voltage and writing time, making the A2RAM suitable as 1T-DRAM. Evidenced through TCAD simulation, the feasibility in matrix environment is also demonstrated.
{"title":"Evidence of fast and low-voltage A2RAM ‘1’ state programming","authors":"F. T. Wakam, J. Lacord, M. Bawedin, S. Martinie, S. Cristoloveanu, J. Barbe","doi":"10.1109/SISPAD.2018.8551653","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551653","url":null,"abstract":"For the first time, we demonstrate a new concept for programming the ‘1’ state in A2RAM based on the impact ionization in the bridge, which can be assisted by the band-to-band tunneling effect in the top part of the silicon film. This new programming method reduces the programming voltage and writing time, making the A2RAM suitable as 1T-DRAM. Evidenced through TCAD simulation, the feasibility in matrix environment is also demonstrated.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127490626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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