Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551700
M. Ancona, J. Calame, D. Meyer, S. Rajan
When GaN HEMTs are used in power amplifier applications, their performance falls well short of ideal due to power-gain roll-off that results from having a peaked transconductance characteristic. A promising design solution involves compositionally grading the channel, and we here formulate a numerical device model to explore this approach that couples linear electroelasticity, diffusion-drift transport with new mobility models, and density-gradient theory. Lumped modeling of the large-signal behavior is also developed to explore the power amplifier performance. Preliminary results presented here indicate that the graded-channel idea has value, especially for gate lengths greater than about 100nm.
{"title":"Device Modeling of Graded III-N HEMTs for Improved Linearity","authors":"M. Ancona, J. Calame, D. Meyer, S. Rajan","doi":"10.1109/SISPAD.2018.8551700","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551700","url":null,"abstract":"When GaN HEMTs are used in power amplifier applications, their performance falls well short of ideal due to power-gain roll-off that results from having a peaked transconductance characteristic. A promising design solution involves compositionally grading the channel, and we here formulate a numerical device model to explore this approach that couples linear electroelasticity, diffusion-drift transport with new mobility models, and density-gradient theory. Lumped modeling of the large-signal behavior is also developed to explore the power amplifier performance. Preliminary results presented here indicate that the graded-channel idea has value, especially for gate lengths greater than about 100nm.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"835 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120875012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551621
Eunseon Yu, Seongjae Cho
In this study, a capacitorless one-transistor dynamic random-access memory (1T DRAM) featuring a novel structure with SiGe quantum well (QW) is proposed and characterized by rigorous simulation. It is demonstrated that the ultra-thin vertical channel and SiGe QW greatly improve device scalability and data retention. In write operation, band-to-band tunneling is applied for faster write speed, higher device scalability, and stronger temperature tolerance. Moreover, the SiGe QW at the drain side generates an increased amount of holes at lower operation voltage and enhances the retention time by constructing a more effective hole storage. As the results, the proposed SiGe QW 1T DRAM showed sub-10-ns fast write and erase times and a long retention time reaching up to 1.12 s.
{"title":"A Highly Scalable and Energy-Efficient 1T DRAM Embedding a SiGe Quantum Well Structure for Significant Retention Enhancement","authors":"Eunseon Yu, Seongjae Cho","doi":"10.1109/SISPAD.2018.8551621","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551621","url":null,"abstract":"In this study, a capacitorless one-transistor dynamic random-access memory (1T DRAM) featuring a novel structure with SiGe quantum well (QW) is proposed and characterized by rigorous simulation. It is demonstrated that the ultra-thin vertical channel and SiGe QW greatly improve device scalability and data retention. In write operation, band-to-band tunneling is applied for faster write speed, higher device scalability, and stronger temperature tolerance. Moreover, the SiGe QW at the drain side generates an increased amount of holes at lower operation voltage and enhances the retention time by constructing a more effective hole storage. As the results, the proposed SiGe QW 1T DRAM showed sub-10-ns fast write and erase times and a long retention time reaching up to 1.12 s.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116142552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551649
E. Baer, J. Lorenz
Topography process simulation has been used to study the interaction of etching and deposition processes for spacer creation for self-aligned double patterning (SADP). For the deposition process, the influence of the layer conformality was investigated. For the etching processthe directionality of the ion flux was varied. The simulations show that by an appropriate combination of the deposition and etching processes, spacers can be created with the desired critical dimension (CD) and a small deviation between the inner and outer space CD values. In addition to using the simulation flow for tuning the processes, it can be employed to investigate the influence of variations. As an example, we studied the effect of the across-wafer non-uniformity of the thickness of the deposited oxide layer. For the process sequence considered, therelative change of the spacer CD is 4 to 5 times larger than the relative change of the oxide thickness.
{"title":"The Effect of Etching and Deposition Processes on the Width of Spacers Created during Self-Aligned Double Patterning","authors":"E. Baer, J. Lorenz","doi":"10.1109/SISPAD.2018.8551649","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551649","url":null,"abstract":"Topography process simulation has been used to study the interaction of etching and deposition processes for spacer creation for self-aligned double patterning (SADP). For the deposition process, the influence of the layer conformality was investigated. For the etching processthe directionality of the ion flux was varied. The simulations show that by an appropriate combination of the deposition and etching processes, spacers can be created with the desired critical dimension (CD) and a small deviation between the inner and outer space CD values. In addition to using the simulation flow for tuning the processes, it can be employed to investigate the influence of variations. As an example, we studied the effect of the across-wafer non-uniformity of the thickness of the deposited oxide layer. For the process sequence considered, therelative change of the spacer CD is 4 to 5 times larger than the relative change of the oxide thickness.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122523029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551699
M. Na, A. Chu, Yoo-mi Lee, A. Young, V. Zalani, Hung Tran
New device architectures such as horizontal Nanosheets have been seriously considered as a replacement for FinFET. A comprehensive, and realistic assessment of these architectures at the early stages of technology development is indispensable to understand their value propositions. In this study a new holistic technology-evaluation methodology for an early technology assessment is proposed. This methodology closely links performance-power metrics to realistic area scaling using block area assessment. This is especially critical for lower track cells since routing complexity can severely degrade performance. In addition, the optimization of an M1 power staple design combined with this evaluation can provide 12% additional area reduction with less than 1% of inverter performance penalty.
{"title":"Rapid and Holistic Technology Evaluation for Exploratory DTCO in Beyond 7nm Technologies","authors":"M. Na, A. Chu, Yoo-mi Lee, A. Young, V. Zalani, Hung Tran","doi":"10.1109/SISPAD.2018.8551699","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551699","url":null,"abstract":"New device architectures such as horizontal Nanosheets have been seriously considered as a replacement for FinFET. A comprehensive, and realistic assessment of these architectures at the early stages of technology development is indispensable to understand their value propositions. In this study a new holistic technology-evaluation methodology for an early technology assessment is proposed. This methodology closely links performance-power metrics to realistic area scaling using block area assessment. This is especially critical for lower track cells since routing complexity can severely degrade performance. In addition, the optimization of an M1 power staple design combined with this evaluation can provide 12% additional area reduction with less than 1% of inverter performance penalty.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128833946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551622
Xujiao Gao, B. Kerr, Andy Huang, G. Hennigan, L. Musson, Mihai Negoita
We present an analytic band-to-trap tunneling model developed using the open boundary scattering approach. The new model explicitly includes the effect of heterojunction band offset, in addition to the well known electric field effect. Its analytic form enables straightforward implementation into TCAD device and circuit simulators. The model is capable of simulating both electric field and band offset enhanced carrier recombination due to the band-to-trap tunneling in the depletion region near a heterojunction. Simulation results of an InGaP/GaAs heterojunction bipolar transistor reveal that the proposed model predicts significantly increased base currents, because the hole-to-trap tunneling from the base to the emitter is greatly enhanced by the emitter base heterojunction band offset. The results compare favorably with experimental observations. The developed method can be applied to all one dimensional potentials which can be approximated to a good degree such that the approximated potentials lead to piecewise analytic wave functions with open boundary conditions.
{"title":"Analytic Band-to-Trap Tunneling Model Including Electric Field and Band Offset Enhancement","authors":"Xujiao Gao, B. Kerr, Andy Huang, G. Hennigan, L. Musson, Mihai Negoita","doi":"10.1109/SISPAD.2018.8551622","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551622","url":null,"abstract":"We present an analytic band-to-trap tunneling model developed using the open boundary scattering approach. The new model explicitly includes the effect of heterojunction band offset, in addition to the well known electric field effect. Its analytic form enables straightforward implementation into TCAD device and circuit simulators. The model is capable of simulating both electric field and band offset enhanced carrier recombination due to the band-to-trap tunneling in the depletion region near a heterojunction. Simulation results of an InGaP/GaAs heterojunction bipolar transistor reveal that the proposed model predicts significantly increased base currents, because the hole-to-trap tunneling from the base to the emitter is greatly enhanced by the emitter base heterojunction band offset. The results compare favorably with experimental observations. The developed method can be applied to all one dimensional potentials which can be approximated to a good degree such that the approximated potentials lead to piecewise analytic wave functions with open boundary conditions.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127439256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551646
S. Baudot, S. Guissi, A. Milenin, J. Ervin, T. Schram
In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the fin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning process steps is assessed. Etch sensitivity to pattern density is reproduced in the model and provides insight on the effect of fin height variability.
{"title":"N7 FinFET Self-Aligned Quadruple Patterning Modeling","authors":"S. Baudot, S. Guissi, A. Milenin, J. Ervin, T. Schram","doi":"10.1109/SISPAD.2018.8551646","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551646","url":null,"abstract":"In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the fin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning process steps is assessed. Etch sensitivity to pattern density is reproduced in the model and provides insight on the effect of fin height variability.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117128098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/sispad.2018.8551690
{"title":"SISPAD 2018 Commentary","authors":"","doi":"10.1109/sispad.2018.8551690","DOIUrl":"https://doi.org/10.1109/sispad.2018.8551690","url":null,"abstract":"","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127013649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551673
S. Su, E. Chen, Jeff Wu
The electrical characteristics of <110> n/p Ge nanowire transistors (NWTs) with the cross section of $6times 6mathrm{n}mathrm{m}^{2}$ have been studied. The ION performance and the subthreshold swing are simulated by multi-subband Boltzmann transport equation and ballistic quantum transport solvers, respectively. The performance of <110> nGe NWTs is sensitive to the barrier height of interfacial layer due to highly-anisotropic $Lambda$-valleys. The dimension-dependent k·p parameters based on tight-binding full band are used to address the strong confinement of pGe NWTs. Comparing to Si NWTs, the intrinsic ION is twice as high for both n/p Ge NWTs at 28nm channel length. As the channel length is scaled down, such ION benefit is maintained till the tunneling effect comes in and degrades the subthreshold swing.
{"title":"A Simulation Perspective: The Potential and Limitation of Ge GAA CMOS Devices","authors":"S. Su, E. Chen, Jeff Wu","doi":"10.1109/SISPAD.2018.8551673","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551673","url":null,"abstract":"The electrical characteristics of <110> n/p Ge nanowire transistors (NWTs) with the cross section of $6times 6mathrm{n}mathrm{m}^{2}$ have been studied. The ION performance and the subthreshold swing are simulated by multi-subband Boltzmann transport equation and ballistic quantum transport solvers, respectively. The performance of <110> nGe NWTs is sensitive to the barrier height of interfacial layer due to highly-anisotropic $Lambda$-valleys. The dimension-dependent k·p parameters based on tight-binding full band are used to address the strong confinement of pGe NWTs. Comparing to Si NWTs, the intrinsic ION is twice as high for both n/p Ge NWTs at 28nm channel length. As the channel length is scaled down, such ION benefit is maintained till the tunneling effect comes in and degrades the subthreshold swing.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127699931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551740
N. Parihar, R. Tiwari, S. Mahapatra
Negative Bias Temperature Instability (NBTI) stress and recovery time kinetics fromReplacement Metal Gate (RMG) High-K Metal Gate (HKMG) p-channel FinFETs are measured and modeled. The impact of channel length (L) scaling on shift in threshold voltage ($mathrm{V}_{T})$,its power-law time exponent (n), Voltage Acceleration Factor (VAF) and Temperature (T) activation $( mathrm{E}_{A})$ is analyzed. TCAD and band structure calculations are utilized to explain the L dependence of experimental data.
{"title":"Modeling Channel Length Scaling Impact on NBTI in RMG Si p-FinFETs","authors":"N. Parihar, R. Tiwari, S. Mahapatra","doi":"10.1109/SISPAD.2018.8551740","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551740","url":null,"abstract":"Negative Bias Temperature Instability (NBTI) stress and recovery time kinetics fromReplacement Metal Gate (RMG) High-K Metal Gate (HKMG) p-channel FinFETs are measured and modeled. The impact of channel length (L) scaling on shift in threshold voltage ($mathrm{V}_{T})$,its power-law time exponent (n), Voltage Acceleration Factor (VAF) and Temperature (T) activation $( mathrm{E}_{A})$ is analyzed. TCAD and band structure calculations are utilized to explain the L dependence of experimental data.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"40 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114034500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551704
E. Bazizi, E. Banghart, B. Zhu, J. H. B. Tng, F. Benistant, Y. Hu, X. He, D. Zhou, H. Lo, D. Choi, J. G. Lee
3D TCAD (Technology Computer Aided Design) process and device simulation is used to show that taller and thinner fins at the 14nm device node enable significant DC and RO performance gains for both nFET and pFET short channel devices through improvement in charge inversion andleakage current control. In particular, simulations identify a maximum in the DC and RO performance as a function of the Fin Ratio, defined as the top fin width (TCD) over the bottom fin width (BCD). At long channel, TCAD simulation demonstrates that mobility degradation observed in nFET hardware devices (but not in pFET devices) is due to the effect of quantum confinement in the fin.
3D TCAD(技术计算机辅助设计)过程和器件仿真表明，在14nm器件节点上更高和更薄的鳍通过改进电荷反转和泄漏电流控制，使nFET和pFET短通道器件的直流和反渗透性能得到显著提高。特别地，模拟确定了直流和反渗透性能的最大值是鳍比的函数，定义为上鳍宽度(TCD)除以下鳍宽度(BCD)。在长信道下，TCAD模拟表明，在fet硬件器件中观察到的迁移率下降(而不是在fet器件中)是由于鳍中的量子限制的影响。
{"title":"14nm FinFET Device Boost via 2nd Generation Fins Optimized for High Performance CMOS Applications","authors":"E. Bazizi, E. Banghart, B. Zhu, J. H. B. Tng, F. Benistant, Y. Hu, X. He, D. Zhou, H. Lo, D. Choi, J. G. Lee","doi":"10.1109/SISPAD.2018.8551704","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551704","url":null,"abstract":"3D TCAD (Technology Computer Aided Design) process and device simulation is used to show that taller and thinner fins at the 14nm device node enable significant DC and RO performance gains for both nFET and pFET short channel devices through improvement in charge inversion andleakage current control. In particular, simulations identify a maximum in the DC and RO performance as a function of the Fin Ratio, defined as the top fin width (TCD) over the bottom fin width (BCD). At long channel, TCAD simulation demonstrates that mobility degradation observed in nFET hardware devices (but not in pFET devices) is due to the effect of quantum confinement in the fin.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123225170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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