Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551748
Prasad Sarangapani, Yuanchen Chu, Kuang-Chung Wang, Daniel Valencia, J. Charles, T. Kubis
Transition metal dichalcogenides (TMDCs) based 2D materials appear to very promising materials for tunnel field-effect transistors (TFETs). [1], [2]. The intrinsic subthreshold slope (SS) of these devices is determined by exponentially decaying band tail states/Urbach tails below conduction and valence band edges which places a lower bound on SS. Though there have been few recent studies on calculating and extracting band tails using simple models and qualitative analysis [3], [4], a rigorous study based on atomistic approach is still lacking.
{"title":"Nonequilibrium Green’s function method: Transport and band tail predictions in transition metal dichalcogenides","authors":"Prasad Sarangapani, Yuanchen Chu, Kuang-Chung Wang, Daniel Valencia, J. Charles, T. Kubis","doi":"10.1109/SISPAD.2018.8551748","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551748","url":null,"abstract":"Transition metal dichalcogenides (TMDCs) based 2D materials appear to very promising materials for tunnel field-effect transistors (TFETs). [1], [2]. The intrinsic subthreshold slope (SS) of these devices is determined by exponentially decaying band tail states/Urbach tails below conduction and valence band edges which places a lower bound on SS. Though there have been few recent studies on calculating and extracting band tails using simple models and qualitative analysis [3], [4], a rigorous study based on atomistic approach is still lacking.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125017288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551697
Jaehyun Lee, S. Berrada, H. Carrillo-Nuñez, C. Medina-Bailón, F. Adamu-Lema, V. Georgiev, A. Asenov
In this work, we perform statistical quantum transport simulations with $3times 3 mathrm{n}mathrm{m}^{2}$ Si nanowire (NW) field-effect transistors (FETs) to investigate the impact of dopant diffusion on random dopant fluctuation. First, we use an effective mass Hamiltonian for the transport where the confinement and transport effective masses are extracted from the tight-binding band structure calculations. The dopant diffusion along the transport direction from the source$/$drain regions to the channel region is modeled by the Gaussian doping profile. To generate random discrete dopants, we adopt a rejection scheme considering the 3-dimensional atomic arrangement of the NW structures. Our statistical simulation results show that the diffused dopants into the channel region cause large variability problems in Si NW FETs.
{"title":"The Impact of Dopant Diffusion on Random Dopant Fluctuation in Si Nanowire FETs: A Quantum Transport Study","authors":"Jaehyun Lee, S. Berrada, H. Carrillo-Nuñez, C. Medina-Bailón, F. Adamu-Lema, V. Georgiev, A. Asenov","doi":"10.1109/SISPAD.2018.8551697","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551697","url":null,"abstract":"In this work, we perform statistical quantum transport simulations with $3times 3 mathrm{n}mathrm{m}^{2}$ Si nanowire (NW) field-effect transistors (FETs) to investigate the impact of dopant diffusion on random dopant fluctuation. First, we use an effective mass Hamiltonian for the transport where the confinement and transport effective masses are extracted from the tight-binding band structure calculations. The dopant diffusion along the transport direction from the source$/$drain regions to the channel region is modeled by the Gaussian doping profile. To generate random discrete dopants, we adopt a rejection scheme considering the 3-dimensional atomic arrangement of the NW structures. Our statistical simulation results show that the diffused dopants into the channel region cause large variability problems in Si NW FETs.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124475258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551737
J. Hattori, T. Ikegami, K. Fukuda, H. Ota, S. Migita, H. Asai
We consider the method to simulate negative-capacitance field-effect transistors having a ferroelectric film as a gate insulator in the framework applicable to technology computer-aided design device simulators and propose a method with complete applicability. In the method, the behavior of the polarization in ferroelectrics is described by the Landau-Khalatnikov equation and it is solved simultaneously with the Poisson equation to obtain the distribution of the polarization and electrostatic potential. Also, the proposed method enables the device simulators to take into account a factor related to forming domain structures of the polarization.
{"title":"Device Simulation of Negative-Capacitance Field-Effect Transistors With a Ferroelectric Gate Insulator","authors":"J. Hattori, T. Ikegami, K. Fukuda, H. Ota, S. Migita, H. Asai","doi":"10.1109/SISPAD.2018.8551737","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551737","url":null,"abstract":"We consider the method to simulate negative-capacitance field-effect transistors having a ferroelectric film as a gate insulator in the framework applicable to technology computer-aided design device simulators and propose a method with complete applicability. In the method, the behavior of the polarization in ferroelectrics is described by the Landau-Khalatnikov equation and it is solved simultaneously with the Poisson equation to obtain the distribution of the polarization and electrostatic potential. Also, the proposed method enables the device simulators to take into account a factor related to forming domain structures of the polarization.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121464193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551724
N. Parihar, R. Tiwari, C. Ndiaye, M. Arabi, S. Mhira, H. Wong, S. Motzny, V. Moroz, V. Huard, S. Mahapatra
A physical framework is used to model time kinetics of Negative Bias Temperature Instability (NBTI) in Si and SiGe FDSOI p-MOSFETs and p-FinFETs. The effects of Germanium (Ge%) in the channel and Nitrogen (N%) in the High-K Metal Gate (HKMG) gate stack are explained. Mechanical strain effects in terms of STI to active distance (SA) for FDSOI and channel length (L) scaling for FinFET are explained. Band structure is calculated to correlate the process (Ge%, N%, strain) impact on device degradation. The model is included in Sentaurus Device TCAD to predict NBTI kinetics in Si and SiGe FinFETs.
{"title":"Modeling of Process (Ge, N) Dependence and Mechanical Strain Impact on NBTI in HKMG SiGe GF FDSOI p-MOSFETs and RMG p-FinFETs","authors":"N. Parihar, R. Tiwari, C. Ndiaye, M. Arabi, S. Mhira, H. Wong, S. Motzny, V. Moroz, V. Huard, S. Mahapatra","doi":"10.1109/SISPAD.2018.8551724","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551724","url":null,"abstract":"A physical framework is used to model time kinetics of Negative Bias Temperature Instability (NBTI) in Si and SiGe FDSOI p-MOSFETs and p-FinFETs. The effects of Germanium (Ge%) in the channel and Nitrogen (N%) in the High-K Metal Gate (HKMG) gate stack are explained. Mechanical strain effects in terms of STI to active distance (SA) for FDSOI and channel length (L) scaling for FinFET are explained. Band structure is calculated to correlate the process (Ge%, N%, strain) impact on device degradation. The model is included in Sentaurus Device TCAD to predict NBTI kinetics in Si and SiGe FinFETs.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115997123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551702
T. Iizuka, M. Miura-Mattausch, Hiroyuki Hashigami, H. Mattausch
The snapback phenomenon is investigated with use of 2D-device simulations. It is found that the phenomenon is induced by three sequentially occurring mechanisms: 1. Impact ionization, 2. Potential increase, and 3. Bipolar effect. Further, it is demonstrated that this series of mechanisms can be successfully modeled with use of the compact model HiSIM_HV by introducing an internal node within the substrate, which is solved in a consistent way. The node is verified to describe the new induced electrical balance correctly. It is demonstrated that the node potential change is the origin of the three involved mechanisms. The reason for the achieved simple but accurate modeling is mainly related to the potential-based modeling approach of HiSIM_HV adopted for the basic I - V modeling, which is influenced by the internal node potential as well.
{"title":"Consistent Modeling of Snapback Phenomenon Based on Conventional I-V Measurements","authors":"T. Iizuka, M. Miura-Mattausch, Hiroyuki Hashigami, H. Mattausch","doi":"10.1109/SISPAD.2018.8551702","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551702","url":null,"abstract":"The snapback phenomenon is investigated with use of 2D-device simulations. It is found that the phenomenon is induced by three sequentially occurring mechanisms: 1. Impact ionization, 2. Potential increase, and 3. Bipolar effect. Further, it is demonstrated that this series of mechanisms can be successfully modeled with use of the compact model HiSIM_HV by introducing an internal node within the substrate, which is solved in a consistent way. The node is verified to describe the new induced electrical balance correctly. It is demonstrated that the node potential change is the origin of the three involved mechanisms. The reason for the achieved simple but accurate modeling is mainly related to the potential-based modeling approach of HiSIM_HV adopted for the basic I - V modeling, which is influenced by the internal node potential as well.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126770796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551667
Shruti R. Kulkarni, Deepak Kadetotad, Jae-sun Seo, B. Rajendran
In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge2 Sb2 Te5, (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resistance dependence on programming voltages, currents and pulse time-scales.
{"title":"Well-Posed Verilog-A Compact Model for Phase Change Memory","authors":"Shruti R. Kulkarni, Deepak Kadetotad, Jae-sun Seo, B. Rajendran","doi":"10.1109/SISPAD.2018.8551667","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551667","url":null,"abstract":"In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge2 Sb2 Te5, (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resistance dependence on programming voltages, currents and pulse time-scales.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127171068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551743
H. Dixit, Jin Cho, F. Benistant
Resistance contribution within Ruthenium (Ru) interconnects, used in middle-of-the line and back-end-of- the line process in an integrated circuit, are evaluated using first-principles density functional theory based transport calculations using the non-equilibrium Green’s function. Three prominent scattering mechanisms impurity scattering, interface/surface scattering and grain-boundary reflections are studied systematically. The results are compared with available resistivity data from literature. The calculated reflection coefficients (R) for the symmetric-tilt grain boundaries lie in the range of 0.38 to 0.51, indicating the grain boundary reflections can significantly enhance the metal resistivity within Ru interconnects. These grain boundary reflection coefficients are in good agreement with hardware data and a fit to the measured resistivity data predicts an average reflection coefficient of 0.51 for Ru interconnect, using Mayadas-Shatzkes model. The results obtained provide useful physical insights into Ru grain-boundary reflections and can be used to classify the metals for advanced interconnect technology.
{"title":"First-principles evaluation of resistance contributions in Ruthenium interconnects for advanced technology nodes","authors":"H. Dixit, Jin Cho, F. Benistant","doi":"10.1109/SISPAD.2018.8551743","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551743","url":null,"abstract":"Resistance contribution within Ruthenium (Ru) interconnects, used in middle-of-the line and back-end-of- the line process in an integrated circuit, are evaluated using first-principles density functional theory based transport calculations using the non-equilibrium Green’s function. Three prominent scattering mechanisms impurity scattering, interface/surface scattering and grain-boundary reflections are studied systematically. The results are compared with available resistivity data from literature. The calculated reflection coefficients (R) for the symmetric-tilt grain boundaries lie in the range of 0.38 to 0.51, indicating the grain boundary reflections can significantly enhance the metal resistivity within Ru interconnects. These grain boundary reflection coefficients are in good agreement with hardware data and a fit to the measured resistivity data predicts an average reflection coefficient of 0.51 for Ru interconnect, using Mayadas-Shatzkes model. The results obtained provide useful physical insights into Ru grain-boundary reflections and can be used to classify the metals for advanced interconnect technology.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130714071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551692
Hong-hyun Park, W. Choi, M. A. Pourghaderi, Jongchol Kim, U. Kwon, D. Kim
We present quantum transport simulation results of vertically stacked multiple silicon nanowire (SiNW) FETs based on the non-equilibrium Green's function (NEGF) method. In order to consider more realistic device conditions such as complex geometry of the multi-channel FETs andvarious carrier scattering processes, we improved physical models and numerical techniques forthe NEGF simulations.
{"title":"Toward more realistic NEGF simulations of vertically stacked multiple SiNW FETs","authors":"Hong-hyun Park, W. Choi, M. A. Pourghaderi, Jongchol Kim, U. Kwon, D. Kim","doi":"10.1109/SISPAD.2018.8551692","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551692","url":null,"abstract":"We present quantum transport simulation results of vertically stacked multiple silicon nanowire (SiNW) FETs based on the non-equilibrium Green's function (NEGF) method. In order to consider more realistic device conditions such as complex geometry of the multi-channel FETs andvarious carrier scattering processes, we improved physical models and numerical techniques forthe NEGF simulations.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134037629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551691
H. Wong, Munkang Choi, R. Tiwari, S. Mahapatra
Nano-wire (NW) transistor is expected to be used in sub-5nm technology nodes for its better electrostatic control. Junction-less (JL) NW is a feasible candidate, as steep source/drain junctions are not required. In this paper, Negative Bias-Temperature-Instability (NBTI) of JL-NW is studied through calibrated TCAD simulation. It is found that JL NW has 20 times less NBTI degradation (in terms of oxide/channel fixed charge generation) than regular NW because of40 times less hole carrier concentration at the oxide/channel interface and absence of field enhanced degradation. A novel operation scheme is then proposed to reduce NBTI degradation in analog circuit by switching the source and drain terminals periodically. The concept is verified through TCAD simulation of NW current mirror and it is found that NW NBTI degradation can befurther reduced by 25% to 35% by using the novel scheme.
{"title":"On the NBTI of Junction-less Nanowire and Novel Operation Scheme to Minimize NBTI Degradation in Analog Circuits","authors":"H. Wong, Munkang Choi, R. Tiwari, S. Mahapatra","doi":"10.1109/SISPAD.2018.8551691","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551691","url":null,"abstract":"Nano-wire (NW) transistor is expected to be used in sub-5nm technology nodes for its better electrostatic control. Junction-less (JL) NW is a feasible candidate, as steep source/drain junctions are not required. In this paper, Negative Bias-Temperature-Instability (NBTI) of JL-NW is studied through calibrated TCAD simulation. It is found that JL NW has 20 times less NBTI degradation (in terms of oxide/channel fixed charge generation) than regular NW because of40 times less hole carrier concentration at the oxide/channel interface and absence of field enhanced degradation. A novel operation scheme is then proposed to reduce NBTI degradation in analog circuit by switching the source and drain terminals periodically. The concept is verified through TCAD simulation of NW current mirror and it is found that NW NBTI degradation can befurther reduced by 25% to 35% by using the novel scheme.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131592483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/SISPAD.2018.8551698
Seon-Young Lee, Ilgyou Shin, Sung-Bo Shim, Alexander Schmidt, I. Jang, D. Kim
Automatic flow of transmission electron microscopy (TEM)-based dislocation analysis on Source/Drain (S/D) and contact formation process is developed. Based on the previously developed model of dislocation stress, an automated methodology is implemented that allows fast and human-error-free extraction of dislocation core position and its impact on the device channel stress and the electrical performance. This approach enables us to analyze the impact of dislocations in S/D of advanced logic devices and to optimize structure and process conditions.
{"title":"TEM based dislocation auto analysis flow of advanced logic devices","authors":"Seon-Young Lee, Ilgyou Shin, Sung-Bo Shim, Alexander Schmidt, I. Jang, D. Kim","doi":"10.1109/SISPAD.2018.8551698","DOIUrl":"https://doi.org/10.1109/SISPAD.2018.8551698","url":null,"abstract":"Automatic flow of transmission electron microscopy (TEM)-based dislocation analysis on Source/Drain (S/D) and contact formation process is developed. Based on the previously developed model of dislocation stress, an automated methodology is implemented that allows fast and human-error-free extraction of dislocation core position and its impact on the device channel stress and the electrical performance. This approach enables us to analyze the impact of dislocations in S/D of advanced logic devices and to optimize structure and process conditions.","PeriodicalId":170070,"journal":{"name":"2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115175864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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