Pub Date : 2023-11-01DOI: 10.1088/1674-4926/44/11/114102
Danlu Liu, Ming Li, Tang Xu, Jie Dong, Yuming Fang, Yue Xu
The influence of the virtual guard ring width (GRW) on the performance of the p-well/deep n-well single-photon avalanche diode (SPAD) in a 180 nm standard CMOS process was investigated. TCAD simulation demonstrates that the electric field strength and current density in the guard ring are obviously enhanced when GRW is decreased to 1 μm. It is experimentally found that, compared with an SPAD with GRW = 2 μm, the dark count rate (DCR) and afterpulsing probability (AP) of the SPAD with GRW = 1 μm is significantly increased by 2.7 times and twofold, respectively, meanwhile, its photon detection probability (PDP) is saturated and hard to be promoted at over 2 V excess bias voltage. Although the fill factor (FF) can be enlarged by reducing GRW, the dark noise of devices is negatively affected due to the enhanced trap-assisted tunneling (TAT) effect in the 1 μm guard ring region. By comparison, the SPAD with GRW = 2 μm can achieve a better trade-off between the FF and noise performance. Our study provides a design guideline for guard rings to realize a low-noise SPAD for large-array applications.
{"title":"Study of the influence of virtual guard ring width on the performance of SPAD detectors in 180 nm standard CMOS technology","authors":"Danlu Liu, Ming Li, Tang Xu, Jie Dong, Yuming Fang, Yue Xu","doi":"10.1088/1674-4926/44/11/114102","DOIUrl":"https://doi.org/10.1088/1674-4926/44/11/114102","url":null,"abstract":"The influence of the virtual guard ring width (GRW) on the performance of the p-well/deep n-well single-photon avalanche diode (SPAD) in a 180 nm standard CMOS process was investigated. TCAD simulation demonstrates that the electric field strength and current density in the guard ring are obviously enhanced when GRW is decreased to 1 μm. It is experimentally found that, compared with an SPAD with GRW = 2 μm, the dark count rate (DCR) and afterpulsing probability (AP) of the SPAD with GRW = 1 μm is significantly increased by 2.7 times and twofold, respectively, meanwhile, its photon detection probability (PDP) is saturated and hard to be promoted at over 2 V excess bias voltage. Although the fill factor (FF) can be enlarged by reducing GRW, the dark noise of devices is negatively affected due to the enhanced trap-assisted tunneling (TAT) effect in the 1 μm guard ring region. By comparison, the SPAD with GRW = 2 μm can achieve a better trade-off between the FF and noise performance. Our study provides a design guideline for guard rings to realize a low-noise SPAD for large-array applications.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"6 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138679968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter showcases the successful fabrication of an enhancement-mode (E-mode) buried p-channel GaN field-effect-transistor on a standard p-GaN/AlGaN/GaN-on-Si power HEMT substrate. The transistor exhibits a threshold voltage (VTH) of −3.8 V, a maximum ON-state current (ION) of 1.12 mA/mm, and an impressive ION/IOFF ratio of 107. To achieve these remarkable results, an H plasma treatment was strategically applied to the gated p-GaN region, where a relatively thick GaN layer (i.e., 70 nm) was kept intact without aggressive gate recess. Through this treatment, the top portion of the GaN layer was converted to be hole-free, leaving only the bottom portion p-type and spatially separated from the etched GaN surface and gate-oxide/GaN interface. This approach allows for E-mode operation while retaining high-quality p-channel characteristics.
这封信展示了在标准 p-GaN/AlGaN/GaN-on-Si 功率 HEMT 衬底上成功制造出的增强型（E-mode）埋入式 p 沟道 GaN 场效应晶体管。该晶体管的阈值电压 (VTH) 为 -3.8 V，最大导通电流 (ION) 为 1.12 mA/mm，ION/IOFF 比为 107，令人印象深刻。为了取得这些骄人成绩，我们对栅极 p-GaN 区域进行了 H 等离子体处理，使相对较厚的 GaN 层（即 70 nm）保持完好，而不会出现栅极凹陷。通过这种处理，氮化镓层的顶部被转换为无孔，只留下底部的 p 型，并在空间上与蚀刻的氮化镓表面和栅氧化物/氮化镓界面分离。这种方法既能实现 E 模式工作，又能保持高质量的 p 沟道特性。
{"title":"Study of enhancement-mode GaN pFET with H plasma treated gate recess","authors":"Xiaotian Gao, Guohao Yu, Jiaan Zhou, Zheming Wang, Yu Li, Jijun Zhang, Xiaoyan Liang, Zhongming Zeng, Baoshun Zhang","doi":"10.1088/1674-4926/44/11/112801","DOIUrl":"https://doi.org/10.1088/1674-4926/44/11/112801","url":null,"abstract":"This letter showcases the successful fabrication of an enhancement-mode (E-mode) buried p-channel GaN field-effect-transistor on a standard p-GaN/AlGaN/GaN-on-Si power HEMT substrate. The transistor exhibits a threshold voltage (<italic toggle=\"yes\">V</italic>\u0000<sub>TH</sub>) of −3.8 V, a maximum ON-state current (<italic toggle=\"yes\">I</italic>\u0000<sub>ON</sub>) of 1.12 mA/mm, and an impressive <italic toggle=\"yes\">I</italic>\u0000<sub>ON</sub>/<italic toggle=\"yes\">I</italic>\u0000<sub>OFF</sub> ratio of 10<sup>7</sup>. To achieve these remarkable results, an H plasma treatment was strategically applied to the gated p-GaN region, where a relatively thick GaN layer (i.e., 70 nm) was kept intact without aggressive gate recess. Through this treatment, the top portion of the GaN layer was converted to be hole-free, leaving only the bottom portion p-type and spatially separated from the etched GaN surface and gate-oxide/GaN interface. This approach allows for E-mode operation while retaining high-quality p-channel characteristics.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"33 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138679955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-01DOI: 10.1088/1674-4926/44/11/111301
Haitao Chen, Hongyuan Cao, Zejie Yu, Weike Zhao, Daoxin Dai
Waveguide-integrated optical modulators are indispensable for on-chip optical interconnects and optical computing. To cope with the ever-increasing amount of data being generated and consumed, ultrafast waveguide-integrated optical modulators with low energy consumption are highly demanded. In recent years, two-dimensional (2D) materials have attracted a lot of attention and have provided tremendous opportunities for the development of high-performance waveguide-integrated optical modulators because of their extraordinary optoelectronic properties and versatile compatibility. This paper reviews the state-of-the-art waveguide-integrated optical modulators with 2D materials, providing researchers with the developing trends in the field and allowing them to identify existing challenges and promising potential solutions. First, the concept and fundamental mechanisms of optical modulation with 2D materials are summarized. Second, a review of waveguide-integrated optical modulators employing electro-optic, all-optic, and thermo-optic effects is provided. Finally, the challenges and perspectives of waveguide-integrated modulators with 2D materials are discussed.
{"title":"Waveguide-integrated optical modulators with two-dimensional materials","authors":"Haitao Chen, Hongyuan Cao, Zejie Yu, Weike Zhao, Daoxin Dai","doi":"10.1088/1674-4926/44/11/111301","DOIUrl":"https://doi.org/10.1088/1674-4926/44/11/111301","url":null,"abstract":"Waveguide-integrated optical modulators are indispensable for on-chip optical interconnects and optical computing. To cope with the ever-increasing amount of data being generated and consumed, ultrafast waveguide-integrated optical modulators with low energy consumption are highly demanded. In recent years, two-dimensional (2D) materials have attracted a lot of attention and have provided tremendous opportunities for the development of high-performance waveguide-integrated optical modulators because of their extraordinary optoelectronic properties and versatile compatibility. This paper reviews the state-of-the-art waveguide-integrated optical modulators with 2D materials, providing researchers with the developing trends in the field and allowing them to identify existing challenges and promising potential solutions. First, the concept and fundamental mechanisms of optical modulation with 2D materials are summarized. Second, a review of waveguide-integrated optical modulators employing electro-optic, all-optic, and thermo-optic effects is provided. Finally, the challenges and perspectives of waveguide-integrated modulators with 2D materials are discussed.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"23 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138679857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-01DOI: 10.1088/1674-4926/44/11/112701
Liang Wu, Peng Wang, Xingwu Zhai, Hang Wang, Wenqi Zhan, Xinfeng Tang, Qianwen Li, Min Zhou
Metallic few-layered 1T phase vanadium disulfide nanosheets have been employed for boosting sodium ion batteries. It can deliver a capacity of 241 mAh∙g−1 at 100 mA∙g−1 after 200 cycles. Such long-term stability is attributed to the facile ion diffusion and electron transport resulting from the well-designed two-dimensional (2D) electron-electron correlations among V atoms in the 1T phase and optimized in-planar electric transport. Our results highlight the phase engineering into electrode design for energy storage.
{"title":"Metallic few-layered 1T-VS2 nanosheets for enhanced sodium storage","authors":"Liang Wu, Peng Wang, Xingwu Zhai, Hang Wang, Wenqi Zhan, Xinfeng Tang, Qianwen Li, Min Zhou","doi":"10.1088/1674-4926/44/11/112701","DOIUrl":"https://doi.org/10.1088/1674-4926/44/11/112701","url":null,"abstract":"Metallic few-layered 1T phase vanadium disulfide nanosheets have been employed for boosting sodium ion batteries. It can deliver a capacity of 241 mAh∙g<sup>−1</sup> at 100 mA∙g<sup>−1</sup> after 200 cycles. Such long-term stability is attributed to the facile ion diffusion and electron transport resulting from the well-designed two-dimensional (2D) electron-electron correlations among V atoms in the 1T phase and optimized in-planar electric transport. Our results highlight the phase engineering into electrode design for energy storage.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"31 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138680346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel. For the analysis, three different channel structures are used: (a) tri-layer stack channel (TLSC) (Si–SiGe–Si), (b) double layer stack channel (DLSC) (SiGe–Si), (c) single layer channel (SLC) (Si). The I−V characteristics, subthreshold swing (SS), drain-induced barrier lowering (DIBL), threshold voltage (Vt), drain current (ION), OFF current (IOFF), and ON-OFF current ratio (ION/IOFF) are observed for the structures at a 20 nm gate length. It is seen that TLSC provides 21.3% and 14.3% more ON current than DLSC and SLC, respectively. The paper also explores the analog and RF factors such as input transconductance (gm), output transconductance (gds), gain (gm/gds), transconductance generation factor (TGF), cut-off frequency (fT), maximum oscillation frequency (fmax), gain frequency product (GFP) and linearity performance parameters such as second and third-order harmonics (gm2, gm3), voltage intercept points (VIP2, VIP3) and 1-dB compression points for the three structures. The results show that the TLSC has a high analog performance due to more gm and provides 16.3%, 48.4% more gain than SLC and DLSC, respectively and it also provides better linearity. All the results are obtained using the VisualTCAD tool.
{"title":"Performance optimization of tri-gate junctionless FinFET using channel stack engineering for digital and analog/RF design","authors":"Devenderpal Singh, Shalini Chaudhary, Basudha Dewan, Menka Yadav","doi":"10.1088/1674-4926/44/11/114103","DOIUrl":"https://doi.org/10.1088/1674-4926/44/11/114103","url":null,"abstract":"This manuscript explores the behavior of a junctionless tri-gate FinFET at the nano-scale region using SiGe material for the channel. For the analysis, three different channel structures are used: (a) tri-layer stack channel (TLSC) (Si–SiGe–Si), (b) double layer stack channel (DLSC) (SiGe–Si), (c) single layer channel (SLC) (Si). The <italic toggle=\"yes\">I</italic>−<italic toggle=\"yes\">V</italic> characteristics, subthreshold swing (SS), drain-induced barrier lowering (DIBL), threshold voltage (<italic toggle=\"yes\">V</italic>\u0000<sub>t</sub>), drain current (<italic toggle=\"yes\">I</italic>\u0000<sub>ON</sub>), OFF current (<italic toggle=\"yes\">I</italic>\u0000<sub>OFF</sub>), and ON-OFF current ratio (<italic toggle=\"yes\">I</italic>\u0000<sub>ON</sub>/<italic toggle=\"yes\">I</italic>\u0000<sub>OFF</sub>) are observed for the structures at a 20 nm gate length. It is seen that TLSC provides 21.3% and 14.3% more ON current than DLSC and SLC, respectively. The paper also explores the analog and RF factors such as input transconductance (<italic toggle=\"yes\">g</italic>\u0000<sub>m</sub>), output transconductance (<italic toggle=\"yes\">g</italic>\u0000<sub>ds</sub>), gain (<italic toggle=\"yes\">g</italic>\u0000<sub>m</sub>/<italic toggle=\"yes\">g</italic>\u0000<sub>ds</sub>), transconductance generation factor (TGF), cut-off frequency (<italic toggle=\"yes\">f</italic>\u0000<sub>T</sub>), maximum oscillation frequency (<italic toggle=\"yes\">f</italic>\u0000<sub>max</sub>), gain frequency product (GFP) and linearity performance parameters such as second and third-order harmonics (<italic toggle=\"yes\">g</italic>\u0000<sub>m2</sub>, <italic toggle=\"yes\">g</italic>\u0000<sub>m3</sub>), voltage intercept points (VIP<sub>2</sub>, VIP<sub>3</sub>) and 1-dB compression points for the three structures. The results show that the TLSC has a high analog performance due to more <italic toggle=\"yes\">g</italic>\u0000<sub>m</sub> and provides 16.3%, 48.4% more gain than SLC and DLSC, respectively and it also provides better linearity. All the results are obtained using the VisualTCAD tool.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"59 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138679848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-01DOI: 10.1088/1674-4926/44/11/114104
Xi Lu, Changju Liu, Pinyuan Zhao, Yu Zhang, Bei Li, Zhenzhen Zhang, Jiangtao Xu
CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO2 interface state traps in the charge transfer path, which reduces the charge transfer efficiency and image quality. Until now, scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition. However, the existing models have thus far ignored the charge transfer limitation due to Si/SiO2 interface state traps in the transfer gate channel, particularly under low illumination. Therefore, this paper proposes, for the first time, an analytical model for quantifying the incomplete charge transfer caused by Si/SiO2 interface state traps in the transfer gate channel under low illumination. This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution, exponential distribution and measured distribution. The model was verified with technology computer-aided design simulations, and the results showed that the simulation results exhibit the consistency with the proposed model.
{"title":"Incomplete charge transfer in CMOS image sensor caused by Si/SiO2 interface states in the TG channel","authors":"Xi Lu, Changju Liu, Pinyuan Zhao, Yu Zhang, Bei Li, Zhenzhen Zhang, Jiangtao Xu","doi":"10.1088/1674-4926/44/11/114104","DOIUrl":"https://doi.org/10.1088/1674-4926/44/11/114104","url":null,"abstract":"CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO<sub>2</sub> interface state traps in the charge transfer path, which reduces the charge transfer efficiency and image quality. Until now, scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition. However, the existing models have thus far ignored the charge transfer limitation due to Si/SiO<sub>2</sub> interface state traps in the transfer gate channel, particularly under low illumination. Therefore, this paper proposes, for the first time, an analytical model for quantifying the incomplete charge transfer caused by Si/SiO<sub>2</sub> interface state traps in the transfer gate channel under low illumination. This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution, exponential distribution and measured distribution. The model was verified with technology computer-aided design simulations, and the results showed that the simulation results exhibit the consistency with the proposed model.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"20 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138679967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-01DOI: 10.1088/1674-4926/44/11/113101
Hang Zhou, Jingrong Yan, Jialin Li, Huan Ge, Tao Zhu, Bingke Zhang, Shucheng Chang, Junmin Sun, Xue Bai, Xiaoguang Wei, Fei Yang
The comparison of domestic and foreign studies has been utilized to extensively employ junction termination extension (JTE) structures for power devices. However, achieving a gradual doping concentration change in the lateral direction is difficult for SiC devices since the diffusion constants of the implanted aluminum ions in SiC are much less than silicon. Many previously reported studies adopted many new structures to solve this problem. Additionally, the JTE structure is strongly sensitive to the ion implantation dose. Thus, GA-JTE, double-zone etched JTE structures, and SM-JTE with modulation spacing were reported to overcome the above shortcomings of the JTE structure and effectively increase the breakdown voltage. They provided a theoretical basis for fabricating terminal structures of 4H-SiC PiN diodes. This paper summarized the effects of different terminal structures on the electrical properties of SiC devices at home and abroad. Presently, the continuous development and breakthrough of terminal technology have significantly improved the breakdown voltage and terminal efficiency of 4H-SiC PiN power diodes.
{"title":"A review of the etched terminal structure of a 4H-SiC PiN diode","authors":"Hang Zhou, Jingrong Yan, Jialin Li, Huan Ge, Tao Zhu, Bingke Zhang, Shucheng Chang, Junmin Sun, Xue Bai, Xiaoguang Wei, Fei Yang","doi":"10.1088/1674-4926/44/11/113101","DOIUrl":"https://doi.org/10.1088/1674-4926/44/11/113101","url":null,"abstract":"The comparison of domestic and foreign studies has been utilized to extensively employ junction termination extension (JTE) structures for power devices. However, achieving a gradual doping concentration change in the lateral direction is difficult for SiC devices since the diffusion constants of the implanted aluminum ions in SiC are much less than silicon. Many previously reported studies adopted many new structures to solve this problem. Additionally, the JTE structure is strongly sensitive to the ion implantation dose. Thus, GA-JTE, double-zone etched JTE structures, and SM-JTE with modulation spacing were reported to overcome the above shortcomings of the JTE structure and effectively increase the breakdown voltage. They provided a theoretical basis for fabricating terminal structures of 4H-SiC PiN diodes. This paper summarized the effects of different terminal structures on the electrical properties of SiC devices at home and abroad. Presently, the continuous development and breakthrough of terminal technology have significantly improved the breakdown voltage and terminal efficiency of 4H-SiC PiN power diodes.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"16 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138692791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-01DOI: 10.1088/1674-4926/44/11/112001
Chengyun Dong, Xiang An, Zhicheng Wu, Zhiguo Zhu, Chao Xie, Jian-An Huang, Linbao Luo
Two-dimensional layered material/semiconductor heterostructures have emerged as a category of fascinating architectures for developing highly efficient and low-cost photodetection devices. Herein, we present the construction of a highly efficient flexible light detector operating in the visible-near infrared wavelength regime by integrating a PdTe2 multilayer on a thin Si film. A representative device achieves a good photoresponse performance at zero bias including a sizeable current on/off ratio exceeding 105, a decent responsivity of ~343 mA/W, a respectable specific detectivity of ~2.56 × 1012 Jones, and a rapid response time of 4.5/379 μs, under 730 nm light irradiation. The detector also displays an outstanding long-term air stability and operational durability. In addition, thanks to the excellent flexibility, the device can retain its prominent photodetection performance at various bending radii of curvature and upon hundreds of bending tests. Furthermore, the large responsivity and rapid response speed endow the photodetector with the ability to accurately probe heart rate, suggesting a possible application in the area of flexible and wearable health monitoring.
{"title":"Multilayered PdTe2/thin Si heterostructures as self-powered flexible photodetectors with heart rate monitoring ability","authors":"Chengyun Dong, Xiang An, Zhicheng Wu, Zhiguo Zhu, Chao Xie, Jian-An Huang, Linbao Luo","doi":"10.1088/1674-4926/44/11/112001","DOIUrl":"https://doi.org/10.1088/1674-4926/44/11/112001","url":null,"abstract":"Two-dimensional layered material/semiconductor heterostructures have emerged as a category of fascinating architectures for developing highly efficient and low-cost photodetection devices. Herein, we present the construction of a highly efficient flexible light detector operating in the visible-near infrared wavelength regime by integrating a PdTe<sub>2</sub> multilayer on a thin Si film. A representative device achieves a good photoresponse performance at zero bias including a sizeable current on/off ratio exceeding 10<sup>5</sup>, a decent responsivity of ~343 mA/W, a respectable specific detectivity of ~2.56 × 10<sup>12</sup> Jones, and a rapid response time of 4.5/379 <italic toggle=\"yes\">μ</italic>s, under 730 nm light irradiation. The detector also displays an outstanding long-term air stability and operational durability. In addition, thanks to the excellent flexibility, the device can retain its prominent photodetection performance at various bending radii of curvature and upon hundreds of bending tests. Furthermore, the large responsivity and rapid response speed endow the photodetector with the ability to accurately probe heart rate, suggesting a possible application in the area of flexible and wearable health monitoring.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"3 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138679676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modulation bandwidth enhancement in a directly modulated two-section distributed feedback (TS-DFB) laser based on a detuned loading effect is investigated and experimentally demonstrated. The results show that the 3-dB bandwidth of the TS-DFB laser is increased to 17.6 GHz and that chirp parameter can be reduced to 2.24. Compared to the absence of a detuned loading effect, there is a 4.6 GHz increase and a 2.45 reduction, respectively. After transmitting a 10 Gb/s non-return-to-zero (NRZ) signal through a 5-km fiber, the modulation eye diagram still achieves a large opening. Eight-channel laser arrays with precise wavelength spacing are fabricated. Each TS-DFB laser in the array has side mode suppression ratios (SMSR) > 49.093 dB and the maximum wavelength residual < 0.316 nm.
{"title":"Modulation bandwidth enhancement in monolithic integrated two-section DFB lasers based on the detuned loading effect","authors":"Yunshan Zhang, Yifan Xu, Shijian Guan, Jilin Zheng, Hongming Gu, Lianyan Li, Rulei Xiao, Tao Fang, Hui Zou, Xiangfei Chen","doi":"10.1088/1674-4926/44/11/112301","DOIUrl":"https://doi.org/10.1088/1674-4926/44/11/112301","url":null,"abstract":"Modulation bandwidth enhancement in a directly modulated two-section distributed feedback (TS-DFB) laser based on a detuned loading effect is investigated and experimentally demonstrated. The results show that the 3-dB bandwidth of the TS-DFB laser is increased to 17.6 GHz and that chirp parameter can be reduced to 2.24. Compared to the absence of a detuned loading effect, there is a 4.6 GHz increase and a 2.45 reduction, respectively. After transmitting a 10 Gb/s non-return-to-zero (NRZ) signal through a 5-km fiber, the modulation eye diagram still achieves a large opening. Eight-channel laser arrays with precise wavelength spacing are fabricated. Each TS-DFB laser in the array has side mode suppression ratios (SMSR) > 49.093 dB and the maximum wavelength residual < 0.316 nm.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"67 1","pages":""},"PeriodicalIF":5.1,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138679808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-01DOI: 10.1088/1674-4926/44/10/102801
Hao Jin, Sen Huang, Qimeng Jiang, Yingjie Wang, Jie Fan, Haibo Yin, Xinhua Wang, Ke Wei, Jianxun Liu, Yaozong Zhong, Qian Sun, Xinyu Liu
Abstract In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistor (p-FET) with a high current density of −4.9 mA/mm based on a O 3 -Al 2 O 3 /HfO 2 (5/15 nm) stacked gate dielectric was demonstrated on a p ++ -GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p ++ -GaN capping layer, a good linear ohmic I − V characteristic featuring a low-contact resistivity ( ρ c ) of 1.34 × 10 −4 Ω·cm 2 was obtained. High gate leakage associated with the HfO 2 high- k gate dielectric was effectively blocked by the 5-nm O 3 -Al 2 O 3 insertion layer grown by atomic layer deposition, contributing to a high I ON / I OFF ratio of 6 × 10 6 and a remarkably reduced subthreshold swing (SS) in the fabricated p-FETs. The proposed structure is compelling for energy-efficient GaN complementary logic (CL) circuits.
摘要在p ++ -GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si异质结构上，基于o3 - al2o3 /HfO 2 (5/15 nm)堆叠栅介质，展示了一种具有- 4.9 mA/mm高电流密度的增强模式(E-mode) GaN p沟道场效应晶体管(p- fet)。由于p ++ -GaN盖层，获得了良好的线性欧姆I−V特性，其接触电阻率(ρ c)为1.34 × 10−4 Ω·cm 2。通过原子层沉积生长的5 nm O - al - O - 3插入层有效地阻断了HfO - 2高k栅极介电介质的高栅极泄漏，使所制备的p- fet具有6 × 10.6的高I - ON / I - OFF比和显著降低的亚阈值摆幅(SS)。所提出的结构对于高能效的GaN互补逻辑(CL)电路是有吸引力的。
{"title":"High-performance enhancement-mode GaN-based p-FETs fabricated with O<sub>3</sub>-Al<sub>2</sub>O<sub>3</sub>/HfO<sub>2</sub>-stacked gate dielectric","authors":"Hao Jin, Sen Huang, Qimeng Jiang, Yingjie Wang, Jie Fan, Haibo Yin, Xinhua Wang, Ke Wei, Jianxun Liu, Yaozong Zhong, Qian Sun, Xinyu Liu","doi":"10.1088/1674-4926/44/10/102801","DOIUrl":"https://doi.org/10.1088/1674-4926/44/10/102801","url":null,"abstract":"Abstract In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistor (p-FET) with a high current density of −4.9 mA/mm based on a O 3 -Al 2 O 3 /HfO 2 (5/15 nm) stacked gate dielectric was demonstrated on a p ++ -GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p ++ -GaN capping layer, a good linear ohmic I − V characteristic featuring a low-contact resistivity ( ρ c ) of 1.34 × 10 −4 Ω·cm 2 was obtained. High gate leakage associated with the HfO 2 high- k gate dielectric was effectively blocked by the 5-nm O 3 -Al 2 O 3 insertion layer grown by atomic layer deposition, contributing to a high I ON / I OFF ratio of 6 × 10 6 and a remarkably reduced subthreshold swing (SS) in the fabricated p-FETs. The proposed structure is compelling for energy-efficient GaN complementary logic (CL) circuits.","PeriodicalId":17038,"journal":{"name":"Journal of Semiconductors","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135849814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：