Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813578
Mustazar Iqbal, A. Piacibello
This paper presents the design and realization of a highly efficient broadband class-F power amplifier (PA) with a multi-harmonic controlled output network. Optimum performance in terms of bandwidth and efficiency is targeted over the frequency band 1.1–2.1 GHz. The design is developed in the Keysight Advanced Design System (ADS) environment and verified experimentally through small- and large-signal characterization. The optimum load and source impedances are determined by performing load-pull and source-pull simulations. The output matching network is designed including harmonic resonators up to the fourth harmonic. In order to achieve broadband operation, the load impedances at harmonics are optimized. The realized PA exhibits state-of-the-art performance, with a power gain of 10–15 dB, a saturated drain efficiency of 60–73% and 10 W output power throughout the selected frequency band (1.1–2.1 GHz). Experimental results show remarkably good agreement with the simulation results.
{"title":"GaN HEMT based class-F power amplifier with broad bandwidth and high efficiency","authors":"Mustazar Iqbal, A. Piacibello","doi":"10.1109/ICAM.2016.7813578","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813578","url":null,"abstract":"This paper presents the design and realization of a highly efficient broadband class-F power amplifier (PA) with a multi-harmonic controlled output network. Optimum performance in terms of bandwidth and efficiency is targeted over the frequency band 1.1–2.1 GHz. The design is developed in the Keysight Advanced Design System (ADS) environment and verified experimentally through small- and large-signal characterization. The optimum load and source impedances are determined by performing load-pull and source-pull simulations. The output matching network is designed including harmonic resonators up to the fourth harmonic. In order to achieve broadband operation, the load impedances at harmonics are optimized. The realized PA exhibits state-of-the-art performance, with a power gain of 10–15 dB, a saturated drain efficiency of 60–73% and 10 W output power throughout the selected frequency band (1.1–2.1 GHz). Experimental results show remarkably good agreement with the simulation results.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132078639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813619
Yingying Liu, Dake Liu, Wei Wang
The recursive filter (IIR) parallel programming on SIMD is more difficult than that of nonrecursive algorithms due to data dependency. Several transformation methods for parallel coding of IIR filter on SIMD have already been proposed to deal with data dependency. However, the inherent prologue and epilogue in these methods obviously increase the complexity of control structures and induce extra hardware overhead. Hence, this paper presents a new transformation method for IIR filter parallel coding on multi-datapath SIMD DSP architecture. By this method, data dependency can thus be removed without introducing epilogue and prologue, the extra execution time of prologue and epilogue can be minimized, and the extra control induced silicon cost is eliminated. Therefore, coding for IIR filter on any normal SIMD can be in parallel.
{"title":"IIR parallelization on multi-datapath SIMD architecture","authors":"Yingying Liu, Dake Liu, Wei Wang","doi":"10.1109/ICAM.2016.7813619","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813619","url":null,"abstract":"The recursive filter (IIR) parallel programming on SIMD is more difficult than that of nonrecursive algorithms due to data dependency. Several transformation methods for parallel coding of IIR filter on SIMD have already been proposed to deal with data dependency. However, the inherent prologue and epilogue in these methods obviously increase the complexity of control structures and induce extra hardware overhead. Hence, this paper presents a new transformation method for IIR filter parallel coding on multi-datapath SIMD DSP architecture. By this method, data dependency can thus be removed without introducing epilogue and prologue, the extra execution time of prologue and epilogue can be minimized, and the extra control induced silicon cost is eliminated. Therefore, coding for IIR filter on any normal SIMD can be in parallel.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129192718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813590
Guang Mao, Lei Xie, Shangqing Ren, Ren-hua Yang, Xin Liu, L. Zhong, Qiu-Ye Lv, Yong Peng
In this paper, a novel structure named as quasidouble silicon-on-insulator metal-oxide-semiconductor transistor (SOI MOSFET) is proposed. Compared with the structure of normal SOI MOSFET, ultrathin oxide layers and p+ wells are added under the source and drain regions, which successfully isolate the source and drain from the buried oxide (BOX). The ultrathin oxide layers prevent the leakage current of the back gate and enhance its reliability. And the P+ wells acting as body ties suppress the floating body effect, but also decrease the resistance of the body contact. Transfer characteristic curve, output characteristic curve and the reliability of this structure are simulated by Sentaurus TCAD, and we compared the simulation results with that of the normal SOI MOSFET.
{"title":"Electrical property and reliability of quasi-double SOI MOSFET","authors":"Guang Mao, Lei Xie, Shangqing Ren, Ren-hua Yang, Xin Liu, L. Zhong, Qiu-Ye Lv, Yong Peng","doi":"10.1109/ICAM.2016.7813590","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813590","url":null,"abstract":"In this paper, a novel structure named as quasidouble silicon-on-insulator metal-oxide-semiconductor transistor (SOI MOSFET) is proposed. Compared with the structure of normal SOI MOSFET, ultrathin oxide layers and p+ wells are added under the source and drain regions, which successfully isolate the source and drain from the buried oxide (BOX). The ultrathin oxide layers prevent the leakage current of the back gate and enhance its reliability. And the P+ wells acting as body ties suppress the floating body effect, but also decrease the resistance of the body contact. Transfer characteristic curve, output characteristic curve and the reliability of this structure are simulated by Sentaurus TCAD, and we compared the simulation results with that of the normal SOI MOSFET.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126703111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813592
Shoucheng Wang, Jinhui Xu, Yingjian Yan, Gongli Li
With the significant attention to information security, mobile terminals such as smartphone always be demand for integrating cryptographic processor. In this paper, a high-efficiency reconfigurable cryptographic processor is presented. Integrating small amounts of computing units designed by reconfigurable technology and developing instruction level parallelism of different operations in a block and among multiple blocks, the proposed architecture can improve the performance of cryptographic algorithm under the condition of limited resources. The processor was simulated and synthesized in 65nm CMOS process. Experimental results show that the processor is small area and high throughput, and outperforms the state-of-the-art processors in area efficiency.
{"title":"A high-efficiency reconfigurable cryptographic processor","authors":"Shoucheng Wang, Jinhui Xu, Yingjian Yan, Gongli Li","doi":"10.1109/ICAM.2016.7813592","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813592","url":null,"abstract":"With the significant attention to information security, mobile terminals such as smartphone always be demand for integrating cryptographic processor. In this paper, a high-efficiency reconfigurable cryptographic processor is presented. Integrating small amounts of computing units designed by reconfigurable technology and developing instruction level parallelism of different operations in a block and among multiple blocks, the proposed architecture can improve the performance of cryptographic algorithm under the condition of limited resources. The processor was simulated and synthesized in 65nm CMOS process. Experimental results show that the processor is small area and high throughput, and outperforms the state-of-the-art processors in area efficiency.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121718543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813567
Meilin Wan, Haoshuang Gu, Zhenzhen Zhang
A new sub-1-ppm/°C curvature-compensated bandgap voltage reference (BGR) is presented in this paper. The Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT is first well balanced with a Proportional to Absolute Temperature (PTAT) voltage, leaving only a high order logarithmic error with the form of TlnT. This residual non-linear error is corrected by a difference of two CTAT voltages with different non-linear terms through controlling the collector currents of BJTs, which can achieve an ideal non-linear compensation. All the circuits are designed in a standard 0.35-pm CMOS process. The post-simulation results show the proposed BGR achieves temperature coefficient (TC) of 0.7 ppm/°C over temperature range of −40 °C to 125 °C and power supply rejection (PSR) of −104 dB at 3.6 V power supply. The line regulation of the output reference voltage is 0.1 mV/V in the supply range of 24.5 V. The maximum dissipating current from the supply is 25.45 μA.
{"title":"A sub-1-ppm/°C curvature-compensated bandgap voltage reference","authors":"Meilin Wan, Haoshuang Gu, Zhenzhen Zhang","doi":"10.1109/ICAM.2016.7813567","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813567","url":null,"abstract":"A new sub-1-ppm/°C curvature-compensated bandgap voltage reference (BGR) is presented in this paper. The Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT is first well balanced with a Proportional to Absolute Temperature (PTAT) voltage, leaving only a high order logarithmic error with the form of TlnT. This residual non-linear error is corrected by a difference of two CTAT voltages with different non-linear terms through controlling the collector currents of BJTs, which can achieve an ideal non-linear compensation. All the circuits are designed in a standard 0.35-pm CMOS process. The post-simulation results show the proposed BGR achieves temperature coefficient (TC) of 0.7 ppm/°C over temperature range of −40 °C to 125 °C and power supply rejection (PSR) of −104 dB at 3.6 V power supply. The line regulation of the output reference voltage is 0.1 mV/V in the supply range of 24.5 V. The maximum dissipating current from the supply is 25.45 μA.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125093285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813571
R. Zeng, Ping Li, G. Wang, Qingwei Zhang, Ziyi Chen
For the first time, an embedded gate graphene field-effect transistor (GFET) with a self-oxidized Al2O3 dielectric layer is proposed. The self-oxidized Al2O3 dielectric layer exhibits good quality and excellent insulation, and the self-oxidized Al2O3 dielectric layer dispels the step of depositing gate dielectrics. The gate leakage current is negligible because its value is only 0.1 nA even at Vgs=5 V. In the process flow of the GFETs, the graphene would experience much less contamination after being transferred onto a preprocessed substrate, because the following process steps is reduced when compared to those traditional top gate GFETs flows. The maximum gm is about 49 gS/gm at Vgs=1.45 V. The effective mobility is up to 2000cm2.Vs.
{"title":"An embedded gate graphene field-effect transistor with self-oxidized Al2O3 dielectrics","authors":"R. Zeng, Ping Li, G. Wang, Qingwei Zhang, Ziyi Chen","doi":"10.1109/ICAM.2016.7813571","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813571","url":null,"abstract":"For the first time, an embedded gate graphene field-effect transistor (GFET) with a self-oxidized Al<inf>2</inf>O<inf>3</inf> dielectric layer is proposed. The self-oxidized Al<inf>2</inf>O<inf>3</inf> dielectric layer exhibits good quality and excellent insulation, and the self-oxidized Al<inf>2</inf>O<inf>3</inf> dielectric layer dispels the step of depositing gate dielectrics. The gate leakage current is negligible because its value is only 0.1 nA even at V<inf>gs</inf>=5 V. In the process flow of the GFETs, the graphene would experience much less contamination after being transferred onto a preprocessed substrate, because the following process steps is reduced when compared to those traditional top gate GFETs flows. The maximum g<inf>m</inf> is about 49 gS/gm at V<inf>gs</inf>=1.45 V. The effective mobility is up to 2000cm<sup>2</sup>.V<sup>s</sup>.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121528118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813620
L. Yuanyuan, C. Hexin, Zhao Yan, Yang Chuxi
In traditional multi-dimensional discrete cosine transform (DCT) algorithm, n dimensions are processed separately. In order to realize n-D global DCT and construct the unity architectures of blocks with different sizes, we have proposed n-D DCT similar butterfly algorithm and its unit pipeline architectures. And in order to solve the problems of this algorithm hardware architectures use a lot of delayers or selectors independently and in algorithm different blocks are not easy to integrate, based on the basic principles of DCT and on the basis of the “tensor” operation, premised on the multi-dimensional DCT pipeline algorithm we have proposed, we invest algorithm architectures to save devices. Firstly, we present n-D DCT pipeline algorithm based on theory of 1-D DCT and tensor product operation in brief, and give n-D DCT similar butterfly architectures. Secondly, we propose pipeline architectures units and the corresponding whole pipeline architecture of n-D DCT. Thirdly and foremost, we set up delayers-group models by reusing delayers and selectors, the models are integrative and nested. The experimental results indicate that the reduce ratio of number of delayers and selectors increased obviously as block size increase by using our device-saving algorithm. The characteristics of our pipeline architectures algorithm are fast, low complexity, and multidimensional compatibility.
{"title":"Device-saving pipeline architectures of multi-dimensional DCT similar butterfly algorithm","authors":"L. Yuanyuan, C. Hexin, Zhao Yan, Yang Chuxi","doi":"10.1109/ICAM.2016.7813620","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813620","url":null,"abstract":"In traditional multi-dimensional discrete cosine transform (DCT) algorithm, n dimensions are processed separately. In order to realize n-D global DCT and construct the unity architectures of blocks with different sizes, we have proposed n-D DCT similar butterfly algorithm and its unit pipeline architectures. And in order to solve the problems of this algorithm hardware architectures use a lot of delayers or selectors independently and in algorithm different blocks are not easy to integrate, based on the basic principles of DCT and on the basis of the “tensor” operation, premised on the multi-dimensional DCT pipeline algorithm we have proposed, we invest algorithm architectures to save devices. Firstly, we present n-D DCT pipeline algorithm based on theory of 1-D DCT and tensor product operation in brief, and give n-D DCT similar butterfly architectures. Secondly, we propose pipeline architectures units and the corresponding whole pipeline architecture of n-D DCT. Thirdly and foremost, we set up delayers-group models by reusing delayers and selectors, the models are integrative and nested. The experimental results indicate that the reduce ratio of number of delayers and selectors increased obviously as block size increase by using our device-saving algorithm. The characteristics of our pipeline architectures algorithm are fast, low complexity, and multidimensional compatibility.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122721256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813593
Q. Tong, Donglai Zhang
There are mainly two kinds of DC power supply voltages such as 28V, 42V in small and medium power level satellites. A novel cascaded current fed DC/DC topology which can cover all these input voltages was proposed. The working principle of the cascaded topology which composed by a Buck converter cascaded with a current fed push-pull converter was analyzed. With a synchronous rectifier circuit, high output current can be offered efficiently. A unique magnetic feedback scheme for space applications was also proposed. The experimental prototype had been built here and testing results were also analyzed.
{"title":"Research on a high output current DC/DC converter with wide input voltage range for space applications","authors":"Q. Tong, Donglai Zhang","doi":"10.1109/ICAM.2016.7813593","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813593","url":null,"abstract":"There are mainly two kinds of DC power supply voltages such as 28V, 42V in small and medium power level satellites. A novel cascaded current fed DC/DC topology which can cover all these input voltages was proposed. The working principle of the cascaded topology which composed by a Buck converter cascaded with a current fed push-pull converter was analyzed. With a synchronous rectifier circuit, high output current can be offered efficiently. A unique magnetic feedback scheme for space applications was also proposed. The experimental prototype had been built here and testing results were also analyzed.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121861911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813627
Zhou Deyun, L. Xiaofeng, Ma Ling
In this paper, the problem of diagnostic strategy for multi-value attribute system is considered. Based on the principal characteristics that quasi-depth first search (QDFS) algorithm can improve the information heuristic algorithm, QDFS is used to improve the information entropy based diagnostic strategy for multi-value attribute system. Then, a new diagnostic strategy for multi-value attribute system is proposed. The theory and experiment demonstrate that, this method is much better than information entropy algorithm on optimization results and computational complexity, which can be used to design the optimal diagnostic strategy for complicated multi-value attribute systems.
研究了多值属性系统的诊断策略问题。基于准深度优先搜索(quasi-depth first search, QDFS)算法改进信息启发式算法的主要特点，将QDFS算法用于改进基于信息熵的多值属性系统诊断策略。然后，提出了一种新的多值属性系统诊断策略。理论和实验表明，该方法在优化结果和计算复杂度上都明显优于信息熵算法，可用于设计复杂多值属性系统的最优诊断策略。
{"title":"Diagnostic strategy for multi-value attribute system based on QDFS algorithm","authors":"Zhou Deyun, L. Xiaofeng, Ma Ling","doi":"10.1109/ICAM.2016.7813627","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813627","url":null,"abstract":"In this paper, the problem of diagnostic strategy for multi-value attribute system is considered. Based on the principal characteristics that quasi-depth first search (QDFS) algorithm can improve the information heuristic algorithm, QDFS is used to improve the information entropy based diagnostic strategy for multi-value attribute system. Then, a new diagnostic strategy for multi-value attribute system is proposed. The theory and experiment demonstrate that, this method is much better than information entropy algorithm on optimization results and computational complexity, which can be used to design the optimal diagnostic strategy for complicated multi-value attribute systems.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115739869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813576
Qiu Fang, Shanzhu Xiao, Huan-zhang Lu, Yabei Wu
High performance crystal oscillator is usually used as the clock source of system timer in a miniaturization space aircraft, however, it cannot overcome the effect of long-term aging on accuracy. Thus, this paper presents a simple, light and efficient circuit to calibrate the difference between the actual output frequency and the nominal frequency of a crystal oscillator periodically in real time. The experiments show that the proposed design reduces the timing deviation from more than 1614ms to less than 1ms in 5 hours. The timing error is less than the required error index, which gives strong support to the working timer of a space aircraft.
{"title":"Design and implementation of calibration circuit for crystal oscillator","authors":"Qiu Fang, Shanzhu Xiao, Huan-zhang Lu, Yabei Wu","doi":"10.1109/ICAM.2016.7813576","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813576","url":null,"abstract":"High performance crystal oscillator is usually used as the clock source of system timer in a miniaturization space aircraft, however, it cannot overcome the effect of long-term aging on accuracy. Thus, this paper presents a simple, light and efficient circuit to calibrate the difference between the actual output frequency and the nominal frequency of a crystal oscillator periodically in real time. The experiments show that the proposed design reduces the timing deviation from more than 1614ms to less than 1ms in 5 hours. The timing error is less than the required error index, which gives strong support to the working timer of a space aircraft.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123214127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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