Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813599
Prateek Sikka
With shrinking time to market for VLSI industry, there is a constant need for hardware - software codevelopment in the VLSI design flow. FPGAs and Emulation systems offer a great help to verification and validation engineers to achieve the same in the VLSI design flow. Further, to enable design verification engineers to create close to real chip scenarios and interface with external peripherals like UART, JTAG, protocol and memory solutions further increases the need for FPGA or Emulation builds earlier in the design cycle. For accelerating smaller designs like IPs, FPGAs could suffice but for running complex SoCs, multi device FPGA architectures or Emulation systems might be needed. However, these acceleration hardware resources are expensive and it is important to make efficient use of them. This invention proposes a methodology for better area utilization of emulation/FPGA resources for a verification scenario/test by creating multiple instances of the design in a single test bench environment. We are able to see 2x-6x improvement in area and verification runtime by using this methodology depending on the type of design and its size.
{"title":"Innovative method for better utilization of emulation hardware /FPGA resources","authors":"Prateek Sikka","doi":"10.1109/ICAM.2016.7813599","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813599","url":null,"abstract":"With shrinking time to market for VLSI industry, there is a constant need for hardware - software codevelopment in the VLSI design flow. FPGAs and Emulation systems offer a great help to verification and validation engineers to achieve the same in the VLSI design flow. Further, to enable design verification engineers to create close to real chip scenarios and interface with external peripherals like UART, JTAG, protocol and memory solutions further increases the need for FPGA or Emulation builds earlier in the design cycle. For accelerating smaller designs like IPs, FPGAs could suffice but for running complex SoCs, multi device FPGA architectures or Emulation systems might be needed. However, these acceleration hardware resources are expensive and it is important to make efficient use of them. This invention proposes a methodology for better area utilization of emulation/FPGA resources for a verification scenario/test by creating multiple instances of the design in a single test bench environment. We are able to see 2x-6x improvement in area and verification runtime by using this methodology depending on the type of design and its size.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122087448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813601
Xiangwei Huang, Pu Pang, Xiaoyao Liang, Li Jiang
We proposed a novel pre-bond functional test architecture for core-level partitioned 3D SoCs. In this test architecture, a new test access mechanism is built by probing functional Through Silicon Vias (TSVs) and by linking functional TSVs to all pins of IP cores under test. In order to reduce the Design-for-Test (DfT) cost, we propose a novel scheme to share the functional TSVs among pins of IP cores and reuse wires which connect pins to the same functional TSVs. Experimental results based on the MCNC benchmarks circuits demonstrate the feasibility and effectiveness of the DfT optimization methods.
{"title":"A cost-effective pre-bond functional test architecture for 3D SoCs","authors":"Xiangwei Huang, Pu Pang, Xiaoyao Liang, Li Jiang","doi":"10.1109/ICAM.2016.7813601","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813601","url":null,"abstract":"We proposed a novel pre-bond functional test architecture for core-level partitioned 3D SoCs. In this test architecture, a new test access mechanism is built by probing functional Through Silicon Vias (TSVs) and by linking functional TSVs to all pins of IP cores under test. In order to reduce the Design-for-Test (DfT) cost, we propose a novel scheme to share the functional TSVs among pins of IP cores and reuse wires which connect pins to the same functional TSVs. Experimental results based on the MCNC benchmarks circuits demonstrate the feasibility and effectiveness of the DfT optimization methods.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122299340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813565
T. Li, RuiTao Zhang
A band calibration algorithm for wide frequency coverage dual VCOs (Voltage-Controlled Oscillator) is presented. A high frequency (9.5 GHz∼12.5GHz) and a low frequency (6 GHz∼9.5GHz) VCO are integrated in PLL circuit for high-speed serial data transmission applications. Algorithm details are presented with calibration precision and time expenditure discussed. This algorithm has been successfully implemented in 55nm CMOS technology.
{"title":"Band calibration of joint dual VCOs covering wide frequency range","authors":"T. Li, RuiTao Zhang","doi":"10.1109/ICAM.2016.7813565","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813565","url":null,"abstract":"A band calibration algorithm for wide frequency coverage dual VCOs (Voltage-Controlled Oscillator) is presented. A high frequency (9.5 GHz∼12.5GHz) and a low frequency (6 GHz∼9.5GHz) VCO are integrated in PLL circuit for high-speed serial data transmission applications. Algorithm details are presented with calibration precision and time expenditure discussed. This algorithm has been successfully implemented in 55nm CMOS technology.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133570993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813587
Xiaowen Xi, C. Chai, Yin-Tang Yang, Yang Liu
This paper investigates the influence of the pulse width, pulse period, and duty ratio on the damage effect of the GaAs pseudomorphic high electron mobility transistor (PHEMT) under the injection of the repletion pulse. First, a damage model is established and verified. Then, based on this model the influence of pulse parameters on the damage effect of the GaAs PHEMT is analyzed. It can be seen that the pulse parameters can significantly affect the damage effect of the device. The increase of the pulse width can aid the damage of the device by increasing the heat of the device obtained by the signal. The influence of the pulse period depends on its variation caused by the change of the pulse width or the pulse interval. When the variation results from the change of the pulse width, the pulse period is inversely proportional to the damage time of the device. When the variation results from the change of the pulse interval, the pulse period is directly proportional to the damage time. The duty ratio is inversely proportional to the damage time of the device by affecting the heat production and dissipation simultaneously. It is found that there is a pulse period and duty ratio safe thresholds. When the injected signal is in the threshold range, the device is safe and has not potential damage under the effect of the repetition pulse.
{"title":"Influence of pulse parameters on the damage effect of the GaAs PHEMT caused by the repetition pulse","authors":"Xiaowen Xi, C. Chai, Yin-Tang Yang, Yang Liu","doi":"10.1109/ICAM.2016.7813587","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813587","url":null,"abstract":"This paper investigates the influence of the pulse width, pulse period, and duty ratio on the damage effect of the GaAs pseudomorphic high electron mobility transistor (PHEMT) under the injection of the repletion pulse. First, a damage model is established and verified. Then, based on this model the influence of pulse parameters on the damage effect of the GaAs PHEMT is analyzed. It can be seen that the pulse parameters can significantly affect the damage effect of the device. The increase of the pulse width can aid the damage of the device by increasing the heat of the device obtained by the signal. The influence of the pulse period depends on its variation caused by the change of the pulse width or the pulse interval. When the variation results from the change of the pulse width, the pulse period is inversely proportional to the damage time of the device. When the variation results from the change of the pulse interval, the pulse period is directly proportional to the damage time. The duty ratio is inversely proportional to the damage time of the device by affecting the heat production and dissipation simultaneously. It is found that there is a pulse period and duty ratio safe thresholds. When the injected signal is in the threshold range, the device is safe and has not potential damage under the effect of the repetition pulse.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123625287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813621
Yu Fang, Tang Bin
The radio frequency identification (RFID) technology has been intensively studied in different frequency bands and widely deployed across various applications. In this paper, we present a new way to observe the RCS of backscattering RFID tags. The new method obtains the relationship not only between RCS and aspect angle, between RCS and frequency, but also between RCS and the size of antenna. A tag antenna with rectangular thin flat plate specifically designed for working in the ultra-high-frequency (UHF) band is used to validate the method. The numeric results show the validity of the new method which is valuable to help the design of RFID tags.
{"title":"Research of RCS of passive UHF RFID tag","authors":"Yu Fang, Tang Bin","doi":"10.1109/ICAM.2016.7813621","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813621","url":null,"abstract":"The radio frequency identification (RFID) technology has been intensively studied in different frequency bands and widely deployed across various applications. In this paper, we present a new way to observe the RCS of backscattering RFID tags. The new method obtains the relationship not only between RCS and aspect angle, between RCS and frequency, but also between RCS and the size of antenna. A tag antenna with rectangular thin flat plate specifically designed for working in the ultra-high-frequency (UHF) band is used to validate the method. The numeric results show the validity of the new method which is valuable to help the design of RFID tags.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123774186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813570
Huaizu Wang, Dechun Guo, Li Wang
The design scheme and implementation of a PLL stepped-frequency source is herein introduced. The PLL's phase noise is first discussed. Combined with basic principles and operating characteristic of HMC703, a design is next given in Ku-band, which utilizes the external VCO chip to form the PLL. Parameters of the loop filter and the phase noise simulations are provided by HITTITE PLL Design. Through debugging the hardware circuits and writing the signal controlling program, the testing results of the real circuits controlled by FPGA finally shows the good performance in phase noise and spurious suppression.
{"title":"Design and implementation of Ku-band frequency synthesizer","authors":"Huaizu Wang, Dechun Guo, Li Wang","doi":"10.1109/ICAM.2016.7813570","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813570","url":null,"abstract":"The design scheme and implementation of a PLL stepped-frequency source is herein introduced. The PLL's phase noise is first discussed. Combined with basic principles and operating characteristic of HMC703, a design is next given in Ku-band, which utilizes the external VCO chip to form the PLL. Parameters of the loop filter and the phase noise simulations are provided by HITTITE PLL Design. Through debugging the hardware circuits and writing the signal controlling program, the testing results of the real circuits controlled by FPGA finally shows the good performance in phase noise and spurious suppression.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125467050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813583
Kun Wang, Changchun Zhang, Ying Zhang, Xincun Ji, Yi Zhang, Fengbo Yuan, Yu-feng Guo
According to the protocol of ISO/IEC 18000-6C, a monolithic UHF RFID transceiver is designed, in a standard 0.18gm RF CMOS process, in which a receiver, a transmitter and a frequency synthesizer are integrated. The direct-conversion receiver consists of a LNA, down-conversion mixers, DCOCs, LPFs and PGAs. A double-mode LNA is employed to meet the different requirements from listen and talk modes in the receiver. The direct-conversion transmitter is composed of a DA, up-conversion mixers, LPFs and PGAs, which supports three kinds of modulation, including DSB-ASK, SSB-ASK and PR-ASK, for the reader-to-tag communications. The ∑-Δ fractional-N frequency synthesizer is employed to produce high-quality I/Q local clocks for both the transmitter and the receiver. Post-simulation results show that, from a single power supply of 1.8V, a receiver sensitivity of −88dBm in listen mode, a receiver linearity (P1dB) of −2dBm in talk mode, a transmitter output power of 4.8dBm are achieved for the transceiver.
{"title":"A monolithic UHF RFID transceiver for mobile UHF RFID readers","authors":"Kun Wang, Changchun Zhang, Ying Zhang, Xincun Ji, Yi Zhang, Fengbo Yuan, Yu-feng Guo","doi":"10.1109/ICAM.2016.7813583","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813583","url":null,"abstract":"According to the protocol of ISO/IEC 18000-6C, a monolithic UHF RFID transceiver is designed, in a standard 0.18gm RF CMOS process, in which a receiver, a transmitter and a frequency synthesizer are integrated. The direct-conversion receiver consists of a LNA, down-conversion mixers, DCOCs, LPFs and PGAs. A double-mode LNA is employed to meet the different requirements from listen and talk modes in the receiver. The direct-conversion transmitter is composed of a DA, up-conversion mixers, LPFs and PGAs, which supports three kinds of modulation, including DSB-ASK, SSB-ASK and PR-ASK, for the reader-to-tag communications. The ∑-Δ fractional-N frequency synthesizer is employed to produce high-quality I/Q local clocks for both the transmitter and the receiver. Post-simulation results show that, from a single power supply of 1.8V, a receiver sensitivity of −88dBm in listen mode, a receiver linearity (P1dB) of −2dBm in talk mode, a transmitter output power of 4.8dBm are achieved for the transceiver.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124457592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813606
Shen Zhong-Hong, Jia Chun-xu
An accelerated life assessment method of microsystems products which consisted of mechanical and electrical components was studied in this paper. The temperature and vibration were chosen to be accelerated life stress according to the research result about the main failure factors of Microsystems. The way using stepwise tests to obtain the accelerated stress limits of temperature and vibration was researched. And how to get the accelerated life model under temperature and vibration stress integrated was also discussed, which gave a guideline of life evaluation of Microsystems.
{"title":"An accelerated life evaluation method of microsystems using temperature and vibration stresses","authors":"Shen Zhong-Hong, Jia Chun-xu","doi":"10.1109/ICAM.2016.7813606","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813606","url":null,"abstract":"An accelerated life assessment method of microsystems products which consisted of mechanical and electrical components was studied in this paper. The temperature and vibration were chosen to be accelerated life stress according to the research result about the main failure factors of Microsystems. The way using stepwise tests to obtain the accelerated stress limits of temperature and vibration was researched. And how to get the accelerated life model under temperature and vibration stress integrated was also discussed, which gave a guideline of life evaluation of Microsystems.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124476649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813600
Lili Guo, Yang Wang
In this paper, a Selective Adaptive Cooperative scheme based on the adaptive cooperative system is proposed to improve the system performance, which is scheduled through combining multilevel adaptive modulation (AM) at the physical layer with truncated automatic repeat request (ARQ) protocol at the data link layer. This paper derives the closedform expressions of the spectral efficiency and outage probability for the Selective adaptive cooperative scheme. It shows by simulation that the proposed system has better performance than the original adaptive cooperative system. Under outdated feedback, we also analyze the impact of the retransmission number, delay-time and the number of cooperative users on the performance of the proposed system.
{"title":"Selective adaptive cooperative design with outdated feedback","authors":"Lili Guo, Yang Wang","doi":"10.1109/ICAM.2016.7813600","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813600","url":null,"abstract":"In this paper, a Selective Adaptive Cooperative scheme based on the adaptive cooperative system is proposed to improve the system performance, which is scheduled through combining multilevel adaptive modulation (AM) at the physical layer with truncated automatic repeat request (ARQ) protocol at the data link layer. This paper derives the closedform expressions of the spectral efficiency and outage probability for the Selective adaptive cooperative scheme. It shows by simulation that the proposed system has better performance than the original adaptive cooperative system. Under outdated feedback, we also analyze the impact of the retransmission number, delay-time and the number of cooperative users on the performance of the proposed system.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131388913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813574
Lijuan Yin, Helun Song
A novel method of intrinsic parameters extraction for RF LDMOS transistors is proposed in this paper. This method uses the relationship of the two-port parameters between Cold-FET and Hot-FET to extract the intrinsic parameters directly without extracting the extrinsic parameters for RF LDMOS. It achieves a good match between the simulated and measured S-parameters in the frequency range over from 0.1 to 5 GHz. Compared with traditional extracting strategy, the proposed method is easier to implement, and the results is more accurate.
{"title":"A novel method of intrinsic parameters extraction for RF LDMOS transistors","authors":"Lijuan Yin, Helun Song","doi":"10.1109/ICAM.2016.7813574","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813574","url":null,"abstract":"A novel method of intrinsic parameters extraction for RF LDMOS transistors is proposed in this paper. This method uses the relationship of the two-port parameters between Cold-FET and Hot-FET to extract the intrinsic parameters directly without extracting the extrinsic parameters for RF LDMOS. It achieves a good match between the simulated and measured S-parameters in the frequency range over from 0.1 to 5 GHz. Compared with traditional extracting strategy, the proposed method is easier to implement, and the results is more accurate.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130628646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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