Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813618
Zhixue Chen, Jinzhao Wu, Huibo Guo, Juxia Xiong, Anping He
SAT is one of the most important basic problems of many areas of computer science and control science. SAT solvers are software or hardware to solve an SAT instance. In this paper, an instance-specified SAT solver was developed with FPGA, which implements the DPLL algorithm with our innovative random variable selection. Moreover, we also introduced an innovative tool-chain of our SAT solver, which including two types of software, e.g., the Xilinx commercial software that is organized by our own C++ parser and some pieces of scripts, and a hardware of FPGA board. With the experiments, our solver keeps quite stable for the highest frequency (200MHz) of Vertex-7 FPGA board, the largest instance under testing has 200 variables and 1200 clauses with less than 3% resources consumed on the FPGA development board.
{"title":"A FPGA based SAT solver with random variable selection","authors":"Zhixue Chen, Jinzhao Wu, Huibo Guo, Juxia Xiong, Anping He","doi":"10.1109/ICAM.2016.7813618","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813618","url":null,"abstract":"SAT is one of the most important basic problems of many areas of computer science and control science. SAT solvers are software or hardware to solve an SAT instance. In this paper, an instance-specified SAT solver was developed with FPGA, which implements the DPLL algorithm with our innovative random variable selection. Moreover, we also introduced an innovative tool-chain of our SAT solver, which including two types of software, e.g., the Xilinx commercial software that is organized by our own C++ parser and some pieces of scripts, and a hardware of FPGA board. With the experiments, our solver keeps quite stable for the highest frequency (200MHz) of Vertex-7 FPGA board, the largest instance under testing has 200 variables and 1200 clauses with less than 3% resources consumed on the FPGA development board.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123249959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813581
Xuegang Zhang, Lijuan Yang, F. Huang
A broadband noise cancelling low noise amplifier (LNA) composed of a CS stage, a single-to-differential (S-to-D) converter, a voltage combiner, a negative feedback network, and a couple of differential-to-single buffers is proposed for multi-standard radio application in this paper. Different from conventional broadband feedback LNA, the proposed LNA shows improved performance parameters including gain, noise figure (NF), 1dB compression point (P1dB), and input-referred third-order intercept point (IIP3), Especially for wideband LNA design. The LNA is fabricated in TSMC 0.13-gm process. From 0.3 to 6GHz, the simulated results show a high-gain of 20 dB, a superior low noise figure of 1.6dB at 3GHz, input power at 1dB compression point (P1dB) of −19.2dBm at 2GHz, it consume 13.2mA from a 1.2V supply and occupies an area of 0.19 mm2.
{"title":"A 0.3–6GHz broadband noise cancelling low noise amplifier","authors":"Xuegang Zhang, Lijuan Yang, F. Huang","doi":"10.1109/ICAM.2016.7813581","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813581","url":null,"abstract":"A broadband noise cancelling low noise amplifier (LNA) composed of a CS stage, a single-to-differential (S-to-D) converter, a voltage combiner, a negative feedback network, and a couple of differential-to-single buffers is proposed for multi-standard radio application in this paper. Different from conventional broadband feedback LNA, the proposed LNA shows improved performance parameters including gain, noise figure (NF), 1dB compression point (P1dB), and input-referred third-order intercept point (IIP3), Especially for wideband LNA design. The LNA is fabricated in TSMC 0.13-gm process. From 0.3 to 6GHz, the simulated results show a high-gain of 20 dB, a superior low noise figure of 1.6dB at 3GHz, input power at 1dB compression point (P1dB) of −19.2dBm at 2GHz, it consume 13.2mA from a 1.2V supply and occupies an area of 0.19 mm2.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129392089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper proposes the design and analysis of a novel micro-scale three dimensional (3D) helix inductor based on focused ion beam (FIB) technology, which is used for terahertz applications. The structure of the inductor includes two parts: the metallic helix and the coplanar waveguide (CPW). It has extremely small scale and can be integrated with other parts of on-chip circuits easily. In addition, fabricating such 3D helix inductors with high precision is much more convenient than other traditional planar spiral inductors. Good performance of quality factor and inductance value have been observed from the simulation results using High Frequency Structure Simulator (HFSS).
{"title":"A novel design of micro-scale 3D helix inductor for terahertz applications","authors":"Yingying Fan, Zhongyu Li, Xiaoyu Wang, Xusheng Tang","doi":"10.1109/ICAM.2016.7813582","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813582","url":null,"abstract":"This paper proposes the design and analysis of a novel micro-scale three dimensional (3D) helix inductor based on focused ion beam (FIB) technology, which is used for terahertz applications. The structure of the inductor includes two parts: the metallic helix and the coplanar waveguide (CPW). It has extremely small scale and can be integrated with other parts of on-chip circuits easily. In addition, fabricating such 3D helix inductors with high precision is much more convenient than other traditional planar spiral inductors. Good performance of quality factor and inductance value have been observed from the simulation results using High Frequency Structure Simulator (HFSS).","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125111245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813573
Lu Yadi, Zhigong Wang, Tang Lu
In this paper, a Broadband LC Voltage Controlled Oscillator (VCO) with low phase noise for wireless communications is realized by a 0.18-μm CMOS process. In order to optimize the turning curve, reduce the phase noise, and increase the linearity, a cross-coupled LC structure is selected. At the same time, a capacitor working in accumulation area and an inverter buffer are applied. The proposed circuit is designed and manufactured in standard 0.18-μm RF-CMOS process. To cover all the bands, the VCO should have an oscillation range of 1.9∼3.05 GHz, the relative bandwidth is 48%. With a 4-bits control word, the VCO is divided into 16 sub-bands. The experimental results show that the proposed VCO design can reach the frequency as high as 3.04 GHz, meeting the requirements of 3.05 GHz. The phase noise in the whole frequency stage is less than −122.9 dBc/Hz.
{"title":"A 1.9–3 GHz broadband LC VCO with low phase noise for wireless communications","authors":"Lu Yadi, Zhigong Wang, Tang Lu","doi":"10.1109/ICAM.2016.7813573","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813573","url":null,"abstract":"In this paper, a Broadband LC Voltage Controlled Oscillator (VCO) with low phase noise for wireless communications is realized by a 0.18-μm CMOS process. In order to optimize the turning curve, reduce the phase noise, and increase the linearity, a cross-coupled LC structure is selected. At the same time, a capacitor working in accumulation area and an inverter buffer are applied. The proposed circuit is designed and manufactured in standard 0.18-μm RF-CMOS process. To cover all the bands, the VCO should have an oscillation range of 1.9∼3.05 GHz, the relative bandwidth is 48%. With a 4-bits control word, the VCO is divided into 16 sub-bands. The experimental results show that the proposed VCO design can reach the frequency as high as 3.04 GHz, meeting the requirements of 3.05 GHz. The phase noise in the whole frequency stage is less than −122.9 dBc/Hz.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126473542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813575
Meng Chuan Gao, Kaiye Bao, F. Huang
A broadband low phase noise (PN) CMOS voltage controlled oscillator (VCO) for Ku Band was presented in this paper. 5-bit switches consisting of 1-bit varactor switch and 4-bit switch cap arrays were adopted so as to obtain a wider tune range (TR) from 11.6GHz to 14.83GHz continuously, and the measured KVCO was less than 400MHz/V. The measured PN was −110.69dBc/Hz@1MHz and the differential output power was 0.96dBm at the highest frequency of 14.83GHz. The measured current dissipation of core circuit was 10.48mA, and total current consumption including buffer was 19.8mA from a 1.2V supply. The VCO was fabricated in TSMC 0.13um 1P8M CMOS process. The die area of layout was 351um×707um.
{"title":"A broadband low phase noise CMOS voltage controlled oscillator for Ku band","authors":"Meng Chuan Gao, Kaiye Bao, F. Huang","doi":"10.1109/ICAM.2016.7813575","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813575","url":null,"abstract":"A broadband low phase noise (PN) CMOS voltage controlled oscillator (VCO) for Ku Band was presented in this paper. 5-bit switches consisting of 1-bit varactor switch and 4-bit switch cap arrays were adopted so as to obtain a wider tune range (TR) from 11.6GHz to 14.83GHz continuously, and the measured KVCO was less than 400MHz/V. The measured PN was −110.69dBc/Hz@1MHz and the differential output power was 0.96dBm at the highest frequency of 14.83GHz. The measured current dissipation of core circuit was 10.48mA, and total current consumption including buffer was 19.8mA from a 1.2V supply. The VCO was fabricated in TSMC 0.13um 1P8M CMOS process. The die area of layout was 351um×707um.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127996500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a compact and broadband ridge substrate integrated waveguide (RSIW) is analyzed, which is low-loss and easy to fabricate. The RSIW is based on substrate integrated waveguide (SIW), and can be completed by inserting a longitudinal central partial-height cuboid metal block or etching a longitudinal central partial-height cuboid then coating the outer surface with metal. Analytical relationship between cutoff frequency and ridge width, relative bandwidth and ridge height is systematically studied. According to the analytical formulas, an X band frequency multiplication RSIW is designed. The simulation results indicates that the insertion loss is lower than 0.043dB, the return loss is higher than 29.9dB, and the cutoff frequency of TE10 mode and TE20 mode respectively are 5.125 GHz and 15.375 GHz, which are in good agreement with the formulas.
{"title":"Propagation characteristic of ridge substrate integrated waveguide","authors":"Lihua Li, X. Liang, Yuxi Zhang, Xiaoguang Wang, Shiling Dong, J. Xie","doi":"10.1109/ICAM.2016.7813591","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813591","url":null,"abstract":"In this paper, a compact and broadband ridge substrate integrated waveguide (RSIW) is analyzed, which is low-loss and easy to fabricate. The RSIW is based on substrate integrated waveguide (SIW), and can be completed by inserting a longitudinal central partial-height cuboid metal block or etching a longitudinal central partial-height cuboid then coating the outer surface with metal. Analytical relationship between cutoff frequency and ridge width, relative bandwidth and ridge height is systematically studied. According to the analytical formulas, an X band frequency multiplication RSIW is designed. The simulation results indicates that the insertion loss is lower than 0.043dB, the return loss is higher than 29.9dB, and the cutoff frequency of TE10 mode and TE20 mode respectively are 5.125 GHz and 15.375 GHz, which are in good agreement with the formulas.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128646822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813556
Haoyang Li, Hong Zheng, Chuanzhao Han
In order to reduce the pressure of data storage and transmission on satellite, researchers implemented a method of object region data extraction from remote sensing image in orbit. This method stores and downloads pixels of interesting region through interesting region labeling. But encoding data volume (EDV), hardware scale and real-time property (RTP) are difficult to be balanced. To solve this problem, the paper proposes the Adaptive Run-length Encoding (ARLE) circuit which is used in target region labeling and applied in FPGA. The circuits are designed upon cascaded structure which is simple, lightweight, modular, extensible and transplantable. Experiment shows that comparing with the existing methods, ARLE circuit has better compression effect and better utilization of resource. And it does not only ensure RTP but also narrow the circuit scale (CS). The target region extraction method can be easily extended to various application scenarios of rapid target region extraction. The ARLE circuit can be directly applied to real-time dataflow encoding between FPGA and external storage devices.
{"title":"Adaptive run-length encoding circuit based on cascaded structure for target region data extraction of remote sensing image","authors":"Haoyang Li, Hong Zheng, Chuanzhao Han","doi":"10.1109/ICAM.2016.7813556","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813556","url":null,"abstract":"In order to reduce the pressure of data storage and transmission on satellite, researchers implemented a method of object region data extraction from remote sensing image in orbit. This method stores and downloads pixels of interesting region through interesting region labeling. But encoding data volume (EDV), hardware scale and real-time property (RTP) are difficult to be balanced. To solve this problem, the paper proposes the Adaptive Run-length Encoding (ARLE) circuit which is used in target region labeling and applied in FPGA. The circuits are designed upon cascaded structure which is simple, lightweight, modular, extensible and transplantable. Experiment shows that comparing with the existing methods, ARLE circuit has better compression effect and better utilization of resource. And it does not only ensure RTP but also narrow the circuit scale (CS). The target region extraction method can be easily extended to various application scenarios of rapid target region extraction. The ARLE circuit can be directly applied to real-time dataflow encoding between FPGA and external storage devices.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128689899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813614
Hu Taotao, Ding Bo
In this paper, a high isolation MIMO filter antenna based on the coupled transmission line resonant structure is proposed. There are two controllable transmission zeros in the coupled transmission line resonant structure. Based on the characteristic, slot filter antenna with high frequency edge selectivity is designed. Then through slotting and the introduction of decoupling of tree structure on the floor, it makes two port isolation reach more than 15dB. The designed MIMO filter antenna has the advantages of compact structure, good frequency selectivity, high isolation degree.
{"title":"Design of MIMO filter antenna based on coupled resonator","authors":"Hu Taotao, Ding Bo","doi":"10.1109/ICAM.2016.7813614","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813614","url":null,"abstract":"In this paper, a high isolation MIMO filter antenna based on the coupled transmission line resonant structure is proposed. There are two controllable transmission zeros in the coupled transmission line resonant structure. Based on the characteristic, slot filter antenna with high frequency edge selectivity is designed. Then through slotting and the introduction of decoupling of tree structure on the floor, it makes two port isolation reach more than 15dB. The designed MIMO filter antenna has the advantages of compact structure, good frequency selectivity, high isolation degree.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117333388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813560
Ming Qu, Yuchun Chang
Irradiation Side-Channel Attack (ISCA) is an innovation for cracking cryptosystem and circuit structure without physical damage. Based on the ISCA architecture design, we proposed an irradiation centric side-channel attack model to induce the cryptographic chip to generate soft error, and we build an irradiation soft error model to present the circuit's behavior. We design a formal verification via the model checking method to analyze and evaluate whether the result or the effect of the circuit's side-channel leakage is consistent with the predefined soft error model. On the basis of the soft error model, we build a model checking process model and an ISCA prototype to implement side-channel attack to get internal key information about chips' integrated circuits. This is illustrated using an ISCA simulation scenario on cryptographic chips' SRAM and Flash. Experimental results show that the proposed method is feasible and effective.
{"title":"Irradiation side-channel attack on cryptographic chip","authors":"Ming Qu, Yuchun Chang","doi":"10.1109/ICAM.2016.7813560","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813560","url":null,"abstract":"Irradiation Side-Channel Attack (ISCA) is an innovation for cracking cryptosystem and circuit structure without physical damage. Based on the ISCA architecture design, we proposed an irradiation centric side-channel attack model to induce the cryptographic chip to generate soft error, and we build an irradiation soft error model to present the circuit's behavior. We design a formal verification via the model checking method to analyze and evaluate whether the result or the effect of the circuit's side-channel leakage is consistent with the predefined soft error model. On the basis of the soft error model, we build a model checking process model and an ISCA prototype to implement side-channel attack to get internal key information about chips' integrated circuits. This is illustrated using an ISCA simulation scenario on cryptographic chips' SRAM and Flash. Experimental results show that the proposed method is feasible and effective.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"70 33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115691483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813579
Zhijun Zhou, P. Warr
The front-end amplifier forms the critical element for signal detection and pre-processing within neural monitoring systems. It determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a combined feedback loop-controlled approach is proposed to neutralize for the input leakage currents generated by low noise amplifiers when in integrated circuit form, alongside signal leakage into the input bias network. Significantly, this loop topology ensures the front-end amplifier maintains a high input impedance across all manufacturing and operational variations. Furthermore, this feedback loop provides the amplification for the low amplitude neural signals without significant increase in power consumption or input-referred noise.
{"title":"An analog integrated front-end amplifier for neural applications","authors":"Zhijun Zhou, P. Warr","doi":"10.1109/ICAM.2016.7813579","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813579","url":null,"abstract":"The front-end amplifier forms the critical element for signal detection and pre-processing within neural monitoring systems. It determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a combined feedback loop-controlled approach is proposed to neutralize for the input leakage currents generated by low noise amplifiers when in integrated circuit form, alongside signal leakage into the input bias network. Significantly, this loop topology ensures the front-end amplifier maintains a high input impedance across all manufacturing and operational variations. Furthermore, this feedback loop provides the amplification for the low amplitude neural signals without significant increase in power consumption or input-referred noise.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114495466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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