Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813558
Lin Zhu, Jinyan Wang, Haisang Jiang, Hongyue Wang, Wengang Wu, Yang Zhou, Gang Dai
In this paper, AlGaN/GaN HEMTs with different device dimensions were designed and fabricated to investigate the relationship between off-state breakdown voltage and gate-to-drain spacing. It is found that the off-state breakdown voltage increases almost linearly with gate-to-drain spacing with the slop of about 46.8V/gm. Sentaurus software was used to find the physical mechanism of this phenomenon. By comparing the simulation results of devices with and without deep-level acceptor traps in GaN buffer layer, it is found that the deep-level acceptor traps in GaN buffer layer underneath the gate-to-drain channel could be occupied by hot electrons created in channel, which would extend the channel depletion region and then alleviate the maximum channel electric field. The theoretical and simulation analysis show that there is a positive correlation between the depletion length and the off-state gate-drain breakdown voltage. The simulation results show that with gate-to-drain spacing increasing, the negatively charged buffer traps region spread wider and the depletion region length becomes longer, playing a key role in the linear dependence of off-state gate-drain breakdown voltage on gate-to-drain spacing.
{"title":"Theoretical analysis of buffer trapping effects on off-state breakdown between gate and drain in AlGaN/GaN HEMTs","authors":"Lin Zhu, Jinyan Wang, Haisang Jiang, Hongyue Wang, Wengang Wu, Yang Zhou, Gang Dai","doi":"10.1109/ICAM.2016.7813558","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813558","url":null,"abstract":"In this paper, AlGaN/GaN HEMTs with different device dimensions were designed and fabricated to investigate the relationship between off-state breakdown voltage and gate-to-drain spacing. It is found that the off-state breakdown voltage increases almost linearly with gate-to-drain spacing with the slop of about 46.8V/gm. Sentaurus software was used to find the physical mechanism of this phenomenon. By comparing the simulation results of devices with and without deep-level acceptor traps in GaN buffer layer, it is found that the deep-level acceptor traps in GaN buffer layer underneath the gate-to-drain channel could be occupied by hot electrons created in channel, which would extend the channel depletion region and then alleviate the maximum channel electric field. The theoretical and simulation analysis show that there is a positive correlation between the depletion length and the off-state gate-drain breakdown voltage. The simulation results show that with gate-to-drain spacing increasing, the negatively charged buffer traps region spread wider and the depletion region length becomes longer, playing a key role in the linear dependence of off-state gate-drain breakdown voltage on gate-to-drain spacing.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130227717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A high precision and portable standard equipment — humidity generator is developed by studying the key technology of divided flow method. In this system, how to control the ratio of moisture and dry gas is the key technology for humidity stability control. The system choose SHIMADEN program controller as the core control system. The program controller set the PID parameter of humidity control through the principle of mixing ratio of dry gas and moisture. The working range of this device is (20∼90) %RH, the humidity fluctuation is better than ± 0.5% RH at 20 1C. Technical indicators of this system also need to be optimized and upgraded; the control rate also needs to be further improved.
{"title":"The key technology research of humidity generator based on divided flow method","authors":"Cheng Ying-shu, Shou Wen-jie, Zhou Lian-qin, Xia Hai-lei, Zhu Ying","doi":"10.1109/ICAM.2016.7813611","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813611","url":null,"abstract":"A high precision and portable standard equipment — humidity generator is developed by studying the key technology of divided flow method. In this system, how to control the ratio of moisture and dry gas is the key technology for humidity stability control. The system choose SHIMADEN program controller as the core control system. The program controller set the PID parameter of humidity control through the principle of mixing ratio of dry gas and moisture. The working range of this device is (20∼90) %RH, the humidity fluctuation is better than ± 0.5% RH at 20 1C. Technical indicators of this system also need to be optimized and upgraded; the control rate also needs to be further improved.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"358 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116683294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813572
Junyu Shi, Dasheng Cui, X. Lv
TiSix-Si Schottky diode on an n-well is designed and fabricated. The device structure is analyzed in depth. The influence of the main parameters on the diode's cut-off frequency is investigated. The analysis shows that the cut-off frequency increases as the Schottky contact area decreases. The series resistance can be further reduced by employing a four-sided cathode. The designed diode achieves the cut-off frequency of 1.3 THz. The ideality factor is 1.34, and the barrier height is 0.38 eV. The high cut-off frequency makes the proposed diodes suitable for millimeter wave even THz detection.
{"title":"A CMOS Schottky barrier diode with the four-sided cathode","authors":"Junyu Shi, Dasheng Cui, X. Lv","doi":"10.1109/ICAM.2016.7813572","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813572","url":null,"abstract":"TiSix-Si Schottky diode on an n-well is designed and fabricated. The device structure is analyzed in depth. The influence of the main parameters on the diode's cut-off frequency is investigated. The analysis shows that the cut-off frequency increases as the Schottky contact area decreases. The series resistance can be further reduced by employing a four-sided cathode. The designed diode achieves the cut-off frequency of 1.3 THz. The ideality factor is 1.34, and the barrier height is 0.38 eV. The high cut-off frequency makes the proposed diodes suitable for millimeter wave even THz detection.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126468516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813616
Yan Ling Wang, Xiao Jin Li, Haiguang Guo, Yanling Shi
In this paper, a set of formulas which are sensitive to the shift in threshold voltage (AVth) of PMOS transistor, load capacitance (CL), and input transition (ti) have been explored to calculate the propagation delay of CMOS inverter using curved surfaces fitting. Different from conventional of focusing on load capacitance and input transition, our proposed model pay more attention to the impact of AVth variation caused by NBTI degeneration on the propagation delay. Moreover, this paper has also proposed a framework to calculate the path delay and clock skew of clock tree network based on the proposed delay model. In order to validate our proposed models and methods, the SPICE-level simulation of the benchmark circuit (s38417) has been compared with our model calculation using a 45-nm CMOS process technology, the results show that our models and methods can calculate the extra path delay and clock skew caused by the shift in threshold voltage.
{"title":"Clock skew analysis based on NBTI degeneration of pMOSFET","authors":"Yan Ling Wang, Xiao Jin Li, Haiguang Guo, Yanling Shi","doi":"10.1109/ICAM.2016.7813616","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813616","url":null,"abstract":"In this paper, a set of formulas which are sensitive to the shift in threshold voltage (AVth) of PMOS transistor, load capacitance (CL), and input transition (ti) have been explored to calculate the propagation delay of CMOS inverter using curved surfaces fitting. Different from conventional of focusing on load capacitance and input transition, our proposed model pay more attention to the impact of AVth variation caused by NBTI degeneration on the propagation delay. Moreover, this paper has also proposed a framework to calculate the path delay and clock skew of clock tree network based on the proposed delay model. In order to validate our proposed models and methods, the SPICE-level simulation of the benchmark circuit (s38417) has been compared with our model calculation using a 45-nm CMOS process technology, the results show that our models and methods can calculate the extra path delay and clock skew caused by the shift in threshold voltage.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125779460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813613
Yuanyuan Zhou, Xuejun Zhou, Zheng Zhang
Considering simple, stability and reliable power supply module for the small power equipment in underwater information network, based on constant-current power supply with submarine optical cable, the electric energy conversion methods with voltage stabilizing diodes are designed and researched. The mathematical models are established and the reliability calculation formulas are deduced for four connection modes, namely series connection, parallel connection, series-parallel connection and parallel-series connection of voltage stabilizing diodes. The simulation results show that each connection mode can obtain its highest reliability by choosing optimum number of voltage stabilizing diodes. In practical application, the most suitable electric energy conversion method can be chosen by considering the reliability of different connections and the number of devices required synthetically.
{"title":"Research on electric energy conversion methods for small power equipment based on constant-current power supply with submarine optical cable","authors":"Yuanyuan Zhou, Xuejun Zhou, Zheng Zhang","doi":"10.1109/ICAM.2016.7813613","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813613","url":null,"abstract":"Considering simple, stability and reliable power supply module for the small power equipment in underwater information network, based on constant-current power supply with submarine optical cable, the electric energy conversion methods with voltage stabilizing diodes are designed and researched. The mathematical models are established and the reliability calculation formulas are deduced for four connection modes, namely series connection, parallel connection, series-parallel connection and parallel-series connection of voltage stabilizing diodes. The simulation results show that each connection mode can obtain its highest reliability by choosing optimum number of voltage stabilizing diodes. In practical application, the most suitable electric energy conversion method can be chosen by considering the reliability of different connections and the number of devices required synthetically.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126827296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813588
R. Sun, Wei He, Jianmin Cao
To explore the influence of the interface charges on the threshold voltage of pMOSFET, we present a novel device model in this paper. By dividing the gate oxide layer into several regions, and setting different interface charges in different regions, the relationship between the interface charges' length and the threshold voltage is well simulated by using 2D numerical simulation, in which the conditions of drain biasing and interface charges' concentration are considered. At the same time, the mechanism of threshold voltage variation is also investigated by comparing the surface potentials of various models. The proposed work can promote the research on Drain Bias-Negative Bias Temperature Instability (DB-NBTI) effect.
{"title":"Numerical simulation of DB-NBTI degradation introduced by different length of interface charges","authors":"R. Sun, Wei He, Jianmin Cao","doi":"10.1109/ICAM.2016.7813588","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813588","url":null,"abstract":"To explore the influence of the interface charges on the threshold voltage of pMOSFET, we present a novel device model in this paper. By dividing the gate oxide layer into several regions, and setting different interface charges in different regions, the relationship between the interface charges' length and the threshold voltage is well simulated by using 2D numerical simulation, in which the conditions of drain biasing and interface charges' concentration are considered. At the same time, the mechanism of threshold voltage variation is also investigated by comparing the surface potentials of various models. The proposed work can promote the research on Drain Bias-Negative Bias Temperature Instability (DB-NBTI) effect.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115295707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813585
Jianxun Yang, Shan Cao
With the CMOS technology node decreasing rapidly, many homogeneous and heterogeneous cores are enabled to be integrated onto a single chip in order to improve the performance of chips. However, due to the aggressive technology scaling, following the improvement of system integration, the rise of power density increases rapidly, which causes a significant number of hot spots and poses an enormous threat to the performance and lifetime of chips. For better modulation of this problem, an accurate temperature simulation platform is urgently necessary. In this paper, based on the open-source Gem5, McPAT and Hotspot simulators, a novel simulation framework is built for accurate power and temperature simulation of Network-on-Chips. Gem5 is adopted to simulate the specified CPU model and obtained access statistics. McPAT and Hotspot are utilized to estimate the power and temperature of the corresponding architecture, respectively. Afterwards, a set of temperature-aware dynamic task scheduling algorithms are then conducted to evaluate the performance of the proposed simulation framework.
{"title":"An accurate power and temperature simulation framework for Network-on-Chip","authors":"Jianxun Yang, Shan Cao","doi":"10.1109/ICAM.2016.7813585","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813585","url":null,"abstract":"With the CMOS technology node decreasing rapidly, many homogeneous and heterogeneous cores are enabled to be integrated onto a single chip in order to improve the performance of chips. However, due to the aggressive technology scaling, following the improvement of system integration, the rise of power density increases rapidly, which causes a significant number of hot spots and poses an enormous threat to the performance and lifetime of chips. For better modulation of this problem, an accurate temperature simulation platform is urgently necessary. In this paper, based on the open-source Gem5, McPAT and Hotspot simulators, a novel simulation framework is built for accurate power and temperature simulation of Network-on-Chips. Gem5 is adopted to simulate the specified CPU model and obtained access statistics. McPAT and Hotspot are utilized to estimate the power and temperature of the corresponding architecture, respectively. Afterwards, a set of temperature-aware dynamic task scheduling algorithms are then conducted to evaluate the performance of the proposed simulation framework.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121854522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：