Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813569
Mi Lin, Haipeng Zhang, Wei-feng Lv
On the issue of the special structure of multiplevalued trigger with multiple-rail-output, a synchronous edge-triggered improved ternary JK flip-flop with three-rail output structure is presented based on the negative differential resistance (NDR) characteristic and the literal operation as well as the module operation. The ternary NDR JK flip-flop could set the logic values of the output to realize ‘0’, ‘1’ and ‘2’ which leads the circuit function more perfect and the structure more complete. The NDR JK flip-flop is simulated by using the MOS-NDR network, the results verify the correctness.
{"title":"An improved ternary three-rail JK flip-flop design","authors":"Mi Lin, Haipeng Zhang, Wei-feng Lv","doi":"10.1109/ICAM.2016.7813569","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813569","url":null,"abstract":"On the issue of the special structure of multiplevalued trigger with multiple-rail-output, a synchronous edge-triggered improved ternary JK flip-flop with three-rail output structure is presented based on the negative differential resistance (NDR) characteristic and the literal operation as well as the module operation. The ternary NDR JK flip-flop could set the logic values of the output to realize ‘0’, ‘1’ and ‘2’ which leads the circuit function more perfect and the structure more complete. The NDR JK flip-flop is simulated by using the MOS-NDR network, the results verify the correctness.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129263865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813553
Wei Han, Shan Wang, Bo Yang
This paper presents an automatic gain control (AGC) algorithm and circuit used in wireless communication receivers with high peak power to average power ratio (PAPR) signal. Combining fixed gain amplifier and programmable attenuator, the AGC function can be implemented by comparing the strength of thresholds with reading two points power detection value of radio frequency (RF) signal. The proposed method can well solve the gain jitter problem in the gain control procedure, implement gain control for each frame of input signal, and shut off the input signal channel if the SNR of input signal is small.
{"title":"Design and implementation of AGC algorithm circuit for high PAPR signal","authors":"Wei Han, Shan Wang, Bo Yang","doi":"10.1109/ICAM.2016.7813553","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813553","url":null,"abstract":"This paper presents an automatic gain control (AGC) algorithm and circuit used in wireless communication receivers with high peak power to average power ratio (PAPR) signal. Combining fixed gain amplifier and programmable attenuator, the AGC function can be implemented by comparing the strength of thresholds with reading two points power detection value of radio frequency (RF) signal. The proposed method can well solve the gain jitter problem in the gain control procedure, implement gain control for each frame of input signal, and shut off the input signal channel if the SNR of input signal is small.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114596635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813595
Xin Hu, Xian Rong Wang, Lu Wang, Hua Li
To offer flexible and programmable forwarding plane, we propose a solution from the perspective of system architecture. An extensible forwarding element architecture (EFEA) based on SDN is proposed, in which the core part is three layer forwarding element architecture (TLFEA). It also includes FE OS image service in SDN controller, FE OS image management system, FE OS development system. In order to verify the feasibility of scheme we proposed, we present the design of packet resolution instruction (PRI) which is based on the parsing method of extended protocol parsing tree model (EPPTM). The result of the experiment proves that the solution is feasible from the design of packet resolution instruction.
为了提供灵活可编程的转发平面，我们从系统架构的角度提出了一种解决方案。提出了一种基于SDN的可扩展转发元素体系结构(extensible forwarding element architecture, EFEA)，其核心部分是三层转发元素体系结构(TLFEA)。还包括SDN控制器中的feos镜像服务、feos镜像管理系统、feos开发系统。为了验证所提方案的可行性，提出了基于扩展协议解析树模型(EPPTM)解析方法的分组解析指令(PRI)设计。实验结果从分组解析指令的设计上证明了该方案的可行性。
{"title":"Design of extensible forwarding element architecture and its key technology verification","authors":"Xin Hu, Xian Rong Wang, Lu Wang, Hua Li","doi":"10.1109/ICAM.2016.7813595","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813595","url":null,"abstract":"To offer flexible and programmable forwarding plane, we propose a solution from the perspective of system architecture. An extensible forwarding element architecture (EFEA) based on SDN is proposed, in which the core part is three layer forwarding element architecture (TLFEA). It also includes FE OS image service in SDN controller, FE OS image management system, FE OS development system. In order to verify the feasibility of scheme we proposed, we present the design of packet resolution instruction (PRI) which is based on the parsing method of extended protocol parsing tree model (EPPTM). The result of the experiment proves that the solution is feasible from the design of packet resolution instruction.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122862371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813596
L. Dan
The frequency stabilization error is an important error for four frequency differential laser gyro (FFDLG). The first kind of dispersion equalization technology (FKDET) can minimize the frequency stabilization sensitivity of FFDLG essentially. From the independent dual-gyro approximation model, the principle and physical picture of FKDET are analyzed. Basing on the analysis, the calibration algorithm is put forward. At last the experimental system is set up. Experimental results show that the frequency stabilization sensitivity of FFDLG can be reduced more than 300 times by using FKDET. The startup and long term drift are also decreased of 0.00396 and 0.00152 respectively. Under temperature environment between −40 °C ∼ 60 C, the drift difference is reduced at least 0.6 by using FKDET. Therefore, FKDET is helpful to improve the performance of FFDLG for practical engineering application.
{"title":"Study on the technology of the first kind of dispersion equalization for four frequency differential laser gyro","authors":"L. Dan","doi":"10.1109/ICAM.2016.7813596","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813596","url":null,"abstract":"The frequency stabilization error is an important error for four frequency differential laser gyro (FFDLG). The first kind of dispersion equalization technology (FKDET) can minimize the frequency stabilization sensitivity of FFDLG essentially. From the independent dual-gyro approximation model, the principle and physical picture of FKDET are analyzed. Basing on the analysis, the calibration algorithm is put forward. At last the experimental system is set up. Experimental results show that the frequency stabilization sensitivity of FFDLG can be reduced more than 300 times by using FKDET. The startup and long term drift are also decreased of 0.00396 and 0.00152 respectively. Under temperature environment between −40 °C ∼ 60 C, the drift difference is reduced at least 0.6 by using FKDET. Therefore, FKDET is helpful to improve the performance of FFDLG for practical engineering application.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116184130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813580
Z. El-Khatib, L. Fuller
In this paper, the design of a fully-integrated amplifier feedback linearization is presented. Simulation results have yielded a peak S21 power gain of 10.3 dB and a unity gain bandwidth of 16 GHz with better than −10 dB S11. The simulation results show a 7 dB IIP3 improvement and IM3 improvement of 18 dBc at output power of −10 dBm. Using derivative superposition improves the feedback amplifier broadband linearity and in turn improves its dynamic range. The proposed fully-integrated amplifier feedback linearization was designed using the 0.13μm CMOS technology.
{"title":"Fully-integrated amplifier feedback linearization design analysis","authors":"Z. El-Khatib, L. Fuller","doi":"10.1109/ICAM.2016.7813580","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813580","url":null,"abstract":"In this paper, the design of a fully-integrated amplifier feedback linearization is presented. Simulation results have yielded a peak S21 power gain of 10.3 dB and a unity gain bandwidth of 16 GHz with better than −10 dB S11. The simulation results show a 7 dB IIP3 improvement and IM3 improvement of 18 dBc at output power of −10 dBm. Using derivative superposition improves the feedback amplifier broadband linearity and in turn improves its dynamic range. The proposed fully-integrated amplifier feedback linearization was designed using the 0.13μm CMOS technology.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129205875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813622
Duoli Zhang, Xiulei Shen, Y. Song
Nowadays FFT convolution is widely applied to digital signal processing (DSP), and the past few years have witnessed the development of the heterogeneous multicore programmable system (HMPS). In addition, HMPS has been the mainstream in the field of DSP. So it is very important to study the high efficient implementation of large FFT convolution on the HMPS. In this paper, a high efficient pipelined overlap-add filter based on the overlap-add FFT convolution method is designed for the input streaming data. This paper introduces the implementation of large FFT convolution on the HMPS and achieves the high accuracy of filter result. Furthermore, a pipeline technology is adopted for the filter design to improve processing speed, throughout and parallelism of tasks. The Xilinx XC7V2000T FPGA verification result shows that the larger sampling points are involved in computing, the higher task parallelism, processing speed and throughout will be obtained, using the suitable and efficient mapping scheme on the HMPS. When the sample points reach 1M, the system average task parallelism is 5.33 with 2.745E6 clock cycles and the precision of 10E-4.
{"title":"The implementation of large FFT convolution on heterogeneous multicore programmable system","authors":"Duoli Zhang, Xiulei Shen, Y. Song","doi":"10.1109/ICAM.2016.7813622","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813622","url":null,"abstract":"Nowadays FFT convolution is widely applied to digital signal processing (DSP), and the past few years have witnessed the development of the heterogeneous multicore programmable system (HMPS). In addition, HMPS has been the mainstream in the field of DSP. So it is very important to study the high efficient implementation of large FFT convolution on the HMPS. In this paper, a high efficient pipelined overlap-add filter based on the overlap-add FFT convolution method is designed for the input streaming data. This paper introduces the implementation of large FFT convolution on the HMPS and achieves the high accuracy of filter result. Furthermore, a pipeline technology is adopted for the filter design to improve processing speed, throughout and parallelism of tasks. The Xilinx XC7V2000T FPGA verification result shows that the larger sampling points are involved in computing, the higher task parallelism, processing speed and throughout will be obtained, using the suitable and efficient mapping scheme on the HMPS. When the sample points reach 1M, the system average task parallelism is 5.33 with 2.745E6 clock cycles and the precision of 10E-4.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125788342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813597
Qiang Dai, Z. Dai, Zhouchuang Wang, Wei Li
Hashing algorithms are used widely in information security area. Having studied the characteristics of traditional cryptographic hashing function and considered the features of multi-core cryptographic processor, this paper proposes a parallel algorithm for hash computation well-suited to multicore cryptographic processor. The algorithm breaks the chain dependencies of the standard hash function by implementing recursive hash to get faster hash implementation. We discuss the theoretical foundation for our mapping framework including security measure and performance measure. The experiments are performed on a PC with a PCIE card including multi-core cryptographic processor as the cipher processing engine. The results show a performance gain by an approximate factor of 7.8 when running on the 8-core cryptographic processor.
{"title":"High-speed realization of parallel algorithm for hash computation on multicore cryptographic processor","authors":"Qiang Dai, Z. Dai, Zhouchuang Wang, Wei Li","doi":"10.1109/ICAM.2016.7813597","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813597","url":null,"abstract":"Hashing algorithms are used widely in information security area. Having studied the characteristics of traditional cryptographic hashing function and considered the features of multi-core cryptographic processor, this paper proposes a parallel algorithm for hash computation well-suited to multicore cryptographic processor. The algorithm breaks the chain dependencies of the standard hash function by implementing recursive hash to get faster hash implementation. We discuss the theoretical foundation for our mapping framework including security measure and performance measure. The experiments are performed on a PC with a PCIE card including multi-core cryptographic processor as the cipher processing engine. The results show a performance gain by an approximate factor of 7.8 when running on the 8-core cryptographic processor.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133729753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813626
Tan Li, Wang Cheng-jiang
In the paper, an insulation protection system for high-voltage live working robot applicable to 10 kV distribution power systems is introduced. According to the current high-voltage live working conditions with the relevant requirements of the insulation protection system and the relevant national standards, a high-voltage insulation protection system which not only meets the needs of robot operation but also to ensure the safety of robot electrical system and the operators is designed. The insulation protection system includes the insulation design of insulation arm, working bucket and electrical system, taking the operation needs of live working robot and the safety requirements fully into account on material selection and construction design. The testing results show that the insulation properties meet the security requirements of live working.
{"title":"Research on insulation protection system for HV live working robot","authors":"Tan Li, Wang Cheng-jiang","doi":"10.1109/ICAM.2016.7813626","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813626","url":null,"abstract":"In the paper, an insulation protection system for high-voltage live working robot applicable to 10 kV distribution power systems is introduced. According to the current high-voltage live working conditions with the relevant requirements of the insulation protection system and the relevant national standards, a high-voltage insulation protection system which not only meets the needs of robot operation but also to ensure the safety of robot electrical system and the operators is designed. The insulation protection system includes the insulation design of insulation arm, working bucket and electrical system, taking the operation needs of live working robot and the safety requirements fully into account on material selection and construction design. The testing results show that the insulation properties meet the security requirements of live working.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133748046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813589
Jian Chen, Qian Dai, Bizhou Shen, Jie Deng, Qiang Xu, Zhu Shi, Libo Yu, Haizhi Song
To reveal the detailed correlation between the controllability of structure parameters in fabrication process and the homogeneity of device performance of single photon avalanche diodes (SPADs), simulations on multi-parameter fluctuations are carried out. We find that, for typical InGaAsP/InP SPADs, significant fluctuation of structure parameters cause asymmetry distribution of the dark count rate (DCR). The asymmetry distribution can be fitted by two half normal distributions with the most probable position deviating from the designed value. With the increase of parameter fluctuation degrees, the DCR-distribution asymmetry and deviation increase in nonlinear manners, implying the complexity and difficulty in simply predicting the performance fluctuations of SPADs. The mechanism is thought to be associated with the near-exponential dependence of DCR on the excess bias. This analysis is quite helpful to the design of focal plane SPAD arrays.
{"title":"Multi-parameter study on the performance fluctuation of InGaAsP/InP single photon avalanche diodes","authors":"Jian Chen, Qian Dai, Bizhou Shen, Jie Deng, Qiang Xu, Zhu Shi, Libo Yu, Haizhi Song","doi":"10.1109/ICAM.2016.7813589","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813589","url":null,"abstract":"To reveal the detailed correlation between the controllability of structure parameters in fabrication process and the homogeneity of device performance of single photon avalanche diodes (SPADs), simulations on multi-parameter fluctuations are carried out. We find that, for typical InGaAsP/InP SPADs, significant fluctuation of structure parameters cause asymmetry distribution of the dark count rate (DCR). The asymmetry distribution can be fitted by two half normal distributions with the most probable position deviating from the designed value. With the increase of parameter fluctuation degrees, the DCR-distribution asymmetry and deviation increase in nonlinear manners, implying the complexity and difficulty in simply predicting the performance fluctuations of SPADs. The mechanism is thought to be associated with the near-exponential dependence of DCR on the excess bias. This analysis is quite helpful to the design of focal plane SPAD arrays.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133956397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813594
Li Qi, Huang Pingjiang, Li Haiou, Yang Nianjiong, Zhang Fabi, Chen Yonghe
This paper introduces a new high voltage double partial SOI (DPSOI) with variable-k (permittivity) dielectric for improving breakdown voltage. The mechanism of breakdown is that the length of vertical ionization integral increases significantly, because of the two symmetrical windows results it by folding effect and the additional electric field produced from variable-k dielectric buried layer modulates surface electric field, which decreases drastically the electric field peaks near the drain and source. Furthermore, the Si window alleviates the self-heating effect while maintaining higher vertical BV. The results indicate that the breakdown voltage of DPSOI is increased by 77.5-85.8% and the on-resistance is decreased nearly by 50% compared with these for the conventional SOI.
{"title":"A new high voltage DPSOI structure with variable-k buried layer","authors":"Li Qi, Huang Pingjiang, Li Haiou, Yang Nianjiong, Zhang Fabi, Chen Yonghe","doi":"10.1109/ICAM.2016.7813594","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813594","url":null,"abstract":"This paper introduces a new high voltage double partial SOI (DPSOI) with variable-k (permittivity) dielectric for improving breakdown voltage. The mechanism of breakdown is that the length of vertical ionization integral increases significantly, because of the two symmetrical windows results it by folding effect and the additional electric field produced from variable-k dielectric buried layer modulates surface electric field, which decreases drastically the electric field peaks near the drain and source. Furthermore, the Si window alleviates the self-heating effect while maintaining higher vertical BV. The results indicate that the breakdown voltage of DPSOI is increased by 77.5-85.8% and the on-resistance is decreased nearly by 50% compared with these for the conventional SOI.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115331913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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