Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813607
Shuxiao Wu, Lei Li, Lei Ren
The reliability of SRAM used in space radiation environment is seriously decreased by single event upset (SEU) and single event transient (SET), which poses a great threat to the normal operation of aerospace equipment. In this paper, we propose a novel structure Delay Self Restoring Logic (DSRL) based on SRL. Its storage structure makes up of three Muller C-elements and two phase inverters. It separates read and write lines on the basis of structure and adds delay unit and delayed bit line to write data. This new memory cell has got the ability to immunize SET in all working period besides anti-SEU. The simulation results show that our proposed SRAM cell has a considerable lower failure probability among the considered recent radiation hardened SRAM cells.
{"title":"A radiation hardened SRAM cell-DSRL","authors":"Shuxiao Wu, Lei Li, Lei Ren","doi":"10.1109/ICAM.2016.7813607","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813607","url":null,"abstract":"The reliability of SRAM used in space radiation environment is seriously decreased by single event upset (SEU) and single event transient (SET), which poses a great threat to the normal operation of aerospace equipment. In this paper, we propose a novel structure Delay Self Restoring Logic (DSRL) based on SRL. Its storage structure makes up of three Muller C-elements and two phase inverters. It separates read and write lines on the basis of structure and adds delay unit and delayed bit line to write data. This new memory cell has got the ability to immunize SET in all working period besides anti-SEU. The simulation results show that our proposed SRAM cell has a considerable lower failure probability among the considered recent radiation hardened SRAM cells.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125095126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813605
Yibin Wang, Liang Yan, Tao Su, Zixin Wang
The two-dimension distribution of EMI in the on-chip power distribution network provides valuable information for understanding the immunity behavior of the integrated circuit. This paper presents an EMI sensor array to measure the distribution. The sensor generates periodical noise on the supply. The spectrum of generated noise is considered as the feedback signal. The power distribution network of the host integrated circuit is utilized as the propagation channel of the feedback signal. The innovation of this distribution measurement method are the following: No extra pin is required to generate any control signal or to detect the feedback signal; No modification is made on the host power distribution network; The sensor can be easily realized with standard cells. The design of sensor array is implemented with Global Foundry 180nm process. The proposed sensor array method is verified by both transistor-level simulation and hardware experiment.
{"title":"The measurement method of 2D distribution of EMI in the on-chip power distribution network","authors":"Yibin Wang, Liang Yan, Tao Su, Zixin Wang","doi":"10.1109/ICAM.2016.7813605","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813605","url":null,"abstract":"The two-dimension distribution of EMI in the on-chip power distribution network provides valuable information for understanding the immunity behavior of the integrated circuit. This paper presents an EMI sensor array to measure the distribution. The sensor generates periodical noise on the supply. The spectrum of generated noise is considered as the feedback signal. The power distribution network of the host integrated circuit is utilized as the propagation channel of the feedback signal. The innovation of this distribution measurement method are the following: No extra pin is required to generate any control signal or to detect the feedback signal; No modification is made on the host power distribution network; The sensor can be easily realized with standard cells. The design of sensor array is implemented with Global Foundry 180nm process. The proposed sensor array method is verified by both transistor-level simulation and hardware experiment.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"94 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120868657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813609
Zhao Yong-zhi, Wang Shao-dong
In this paper, we have proposed an extremely-small, low-cost and high reliability 3-dimensional micro-system which is composed of radio frequency (RF) components. The microwave monolithic integrated circuits of the T/R module are mounted onto a silicon substrate which is fabricated by MEMS technology. Some passive components, such as filters, attenuators and transmission lines, are embedded in the silicon substrate. The full T/R module consists of a low noise amplifier, two driver amplifiers, a limiter, two attenuators, two switches and a MEMS filter. The maximum of the measured noise figure of the T/R module is 3.5dB. The measured Tx and Rx gain are 35dB and 25dB respectively, and the output power at 1-dB gain compression point is 25dBm. By comparing with the samples obtained by the Surface Mount Technology (SMT) process, the volume is only half of the similar products, while the performance is basically the same, which verifies the feasibility of the technical approach.
{"title":"A novel 3D T/R module with MEMS technology","authors":"Zhao Yong-zhi, Wang Shao-dong","doi":"10.1109/ICAM.2016.7813609","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813609","url":null,"abstract":"In this paper, we have proposed an extremely-small, low-cost and high reliability 3-dimensional micro-system which is composed of radio frequency (RF) components. The microwave monolithic integrated circuits of the T/R module are mounted onto a silicon substrate which is fabricated by MEMS technology. Some passive components, such as filters, attenuators and transmission lines, are embedded in the silicon substrate. The full T/R module consists of a low noise amplifier, two driver amplifiers, a limiter, two attenuators, two switches and a MEMS filter. The maximum of the measured noise figure of the T/R module is 3.5dB. The measured Tx and Rx gain are 35dB and 25dB respectively, and the output power at 1-dB gain compression point is 25dBm. By comparing with the samples obtained by the Surface Mount Technology (SMT) process, the volume is only half of the similar products, while the performance is basically the same, which verifies the feasibility of the technical approach.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125151794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813608
H. Zhong, Qingmin Li
Given that dynamically variability and uncertainty (randomness, fuzziness, grayness and unsacertainty) exist in comprehensive evaluation of power quality, this paper described and treated the uncertainty information reasonably in index parameter, boundary and weight. Based on the variable fuzzy sets evaluation method, blind number theory was introduced into power quality evaluation to deal with the uncertainty problems, and a comprehensive evaluation model based on blind number and variable fuzzy sets theory was proposed. Superiority and effectiveness of the suggested method can be verified by case study, therefore, the model can be used to evaluate power quality in the power quality management.
{"title":"A comprehensive evaluation model of power quality based on blind number and variable fuzzy sets theory","authors":"H. Zhong, Qingmin Li","doi":"10.1109/ICAM.2016.7813608","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813608","url":null,"abstract":"Given that dynamically variability and uncertainty (randomness, fuzziness, grayness and unsacertainty) exist in comprehensive evaluation of power quality, this paper described and treated the uncertainty information reasonably in index parameter, boundary and weight. Based on the variable fuzzy sets evaluation method, blind number theory was introduced into power quality evaluation to deal with the uncertainty problems, and a comprehensive evaluation model based on blind number and variable fuzzy sets theory was proposed. Superiority and effectiveness of the suggested method can be verified by case study, therefore, the model can be used to evaluate power quality in the power quality management.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126424686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813563
Y. Bai, Yuchuan Sun, Mingjie Lin
The logic design framework based on Threshold Logic Gate (TLG), combined with emerging spintronic device technology, can achieve ultra-high-performance computing circuits. However, large-fanin threshold logic gates with emerging devices often lead to reduced variation tolerance for memristance, therefore resulting in a so-called fan-in restriction problem. This limitation prevents both large threshold logic nodes and further reduction of logic depth, both of which are critical to achieving high circuit performance. In this paper, we propose a novel stochastic-based design methodology for large-fanin threshold logic gates and two specially designed CAD algorithms to calculate probabilistic weights and threshold values. These techniques allow us to design and implement efficient and robust logic circuits with very large fanin and very shallow logic depths. Our simulation results have shown that, for seven ISCAS-85 benchmark circuits, on average, the energy consumption and delay performance can be improved by about 50% and 30% when comparing our stochastic-based design with a deterministic memristor-based threshold logic design. In addition, for the same set of benchmark circuits, our stochastic-based spintronic circuits can be more than 100x more energy efficient than the conventional CMOS-based FPGA.
{"title":"Stochastic-based logic circuit synthesis and implementation through large-fanin threshold logic with magnetic tunneling junctions","authors":"Y. Bai, Yuchuan Sun, Mingjie Lin","doi":"10.1109/ICAM.2016.7813563","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813563","url":null,"abstract":"The logic design framework based on Threshold Logic Gate (TLG), combined with emerging spintronic device technology, can achieve ultra-high-performance computing circuits. However, large-fanin threshold logic gates with emerging devices often lead to reduced variation tolerance for memristance, therefore resulting in a so-called fan-in restriction problem. This limitation prevents both large threshold logic nodes and further reduction of logic depth, both of which are critical to achieving high circuit performance. In this paper, we propose a novel stochastic-based design methodology for large-fanin threshold logic gates and two specially designed CAD algorithms to calculate probabilistic weights and threshold values. These techniques allow us to design and implement efficient and robust logic circuits with very large fanin and very shallow logic depths. Our simulation results have shown that, for seven ISCAS-85 benchmark circuits, on average, the energy consumption and delay performance can be improved by about 50% and 30% when comparing our stochastic-based design with a deterministic memristor-based threshold logic design. In addition, for the same set of benchmark circuits, our stochastic-based spintronic circuits can be more than 100x more energy efficient than the conventional CMOS-based FPGA.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125912929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813586
Qinfeng Zhang, Yingdan Jiang, Shuqin Wan, Peicheng Li, Zhang Tao
This paper presents a high performance low jitter PLL. Fully differential PFD and divider are implemented to minimize its in-band noise and to achieve high common mode and power supply noise rejection. A low jitter LC-tank VCO is used to achieve low out-of-band noise. A level shifter is inserted between the LF and VCO to optimize the VCO performance. The PLL is fabricated in SMIC 65nm CMOS low leakage process. The operating frequency range of the VCO is 2–3GHz, and the rms period jitter of the PLL at 3GHz due to supply noise is 374fs with an additive 2MHz 50mVpp sinusoidal power supply noise. The PLL has been used as a clock multiplier for a 14bit 2.5GSPS high speed high resolution DAC.
{"title":"An integrated low jitter PLL for high speed high resolution DACs","authors":"Qinfeng Zhang, Yingdan Jiang, Shuqin Wan, Peicheng Li, Zhang Tao","doi":"10.1109/ICAM.2016.7813586","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813586","url":null,"abstract":"This paper presents a high performance low jitter PLL. Fully differential PFD and divider are implemented to minimize its in-band noise and to achieve high common mode and power supply noise rejection. A low jitter LC-tank VCO is used to achieve low out-of-band noise. A level shifter is inserted between the LF and VCO to optimize the VCO performance. The PLL is fabricated in SMIC 65nm CMOS low leakage process. The operating frequency range of the VCO is 2–3GHz, and the rms period jitter of the PLL at 3GHz due to supply noise is 374fs with an additive 2MHz 50mVpp sinusoidal power supply noise. The PLL has been used as a clock multiplier for a 14bit 2.5GSPS high speed high resolution DAC.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129964811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813603
Xiaosuo Luo, Guoqing Zhou, B. Cao
In order to deal with constrained characteristics in the closed-loop industrial processes, a constrained applied predictive control(CAPC) method based on closed-loop subspace identification is proposed. The state-space model is obtained through the closed-loop subspace identification algorithm, which is regarded as the system model. Then, the model is used to design the model predictive controller which involves the solution of a quadratic program solving constraints. The paper presents a comparison of performance given by proposed control method when applied to a 2-CSTR system with an open-loop subspace CAPC method, the superiority of the proposed method is illustrated through the simulation results.
{"title":"Constrained applied predictive control based on closed-loop subspace identification","authors":"Xiaosuo Luo, Guoqing Zhou, B. Cao","doi":"10.1109/ICAM.2016.7813603","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813603","url":null,"abstract":"In order to deal with constrained characteristics in the closed-loop industrial processes, a constrained applied predictive control(CAPC) method based on closed-loop subspace identification is proposed. The state-space model is obtained through the closed-loop subspace identification algorithm, which is regarded as the system model. Then, the model is used to design the model predictive controller which involves the solution of a quadratic program solving constraints. The paper presents a comparison of performance given by proposed control method when applied to a 2-CSTR system with an open-loop subspace CAPC method, the superiority of the proposed method is illustrated through the simulation results.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"1987 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125481403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813623
Mingming Lou, Pengwei Yu, Yao Yao, Lei Zhang
The purpose of this paper is to develop both of high accuracy positioning and map building for an autonomous mobile robot working in indoor environment. A time difference of arrival (TDOA) hyperbola locating method based on ultra-wideband technology and Taylor series expansion algorithm has been proposed to reduce the indoor positioning error. A straight line matching method is raised to process the real-time laser scanned data. The parameters of matching conditions and state matrix under different motion state are deduced to improve the accuracy of line feature matching. The ultra-wideband technology with TDOA locating method and Taylor expansion algorithm proved to be accurate in determining the location and position. The map building combined with the proposed feature line matching has the potential to meet the demand for robot navigation, exploration and cognition.
{"title":"Indoor localization and map building for autonomous mobile robot","authors":"Mingming Lou, Pengwei Yu, Yao Yao, Lei Zhang","doi":"10.1109/ICAM.2016.7813623","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813623","url":null,"abstract":"The purpose of this paper is to develop both of high accuracy positioning and map building for an autonomous mobile robot working in indoor environment. A time difference of arrival (TDOA) hyperbola locating method based on ultra-wideband technology and Taylor series expansion algorithm has been proposed to reduce the indoor positioning error. A straight line matching method is raised to process the real-time laser scanned data. The parameters of matching conditions and state matrix under different motion state are deduced to improve the accuracy of line feature matching. The ultra-wideband technology with TDOA locating method and Taylor expansion algorithm proved to be accurate in determining the location and position. The map building combined with the proposed feature line matching has the potential to meet the demand for robot navigation, exploration and cognition.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123473873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813598
Juma Mary Atieno, Xuliang Zhang, H. Bai
A segmented and unsegmented 3D insulated copper through silicon vias (TSVs) of diameter 10μm, height 100μm and silicon of sizes 100μm by 100μm by 100μm are modelled using analysis system (ANSYS) and equivalent circuit using advanced design system (ADS) at frequency ranges between 100MHz and 20GHz at 10MHz step sizes. The segmented via is divided into three parts; part 1, part 2 and part 3. Each part is modelled separately. The scattering parameters especially the S21 which defines power loss in TSVs in both cases are found. The outputs are optimized to give accurate results. The results show that the outputs reflect the transmission characteristics of an ideal TSV. It's concluded that segmented TSV experiences a much lower insertion loss compared to the unsegmented one. Since insertion loss is a key reliability problem in TSVs, we propose this kind of modelling to eradicate it. However other reliability issues need to be eradicated too.
{"title":"S-parameters optimization in both segmented and unsegmented insulated TSV","authors":"Juma Mary Atieno, Xuliang Zhang, H. Bai","doi":"10.1109/ICAM.2016.7813598","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813598","url":null,"abstract":"A segmented and unsegmented 3D insulated copper through silicon vias (TSVs) of diameter 10μm, height 100μm and silicon of sizes 100μm by 100μm by 100μm are modelled using analysis system (ANSYS) and equivalent circuit using advanced design system (ADS) at frequency ranges between 100MHz and 20GHz at 10MHz step sizes. The segmented via is divided into three parts; part 1, part 2 and part 3. Each part is modelled separately. The scattering parameters especially the S21 which defines power loss in TSVs in both cases are found. The outputs are optimized to give accurate results. The results show that the outputs reflect the transmission characteristics of an ideal TSV. It's concluded that segmented TSV experiences a much lower insertion loss compared to the unsegmented one. Since insertion loss is a key reliability problem in TSVs, we propose this kind of modelling to eradicate it. However other reliability issues need to be eradicated too.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132979548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ICAM.2016.7813554
Liang-Yong Song, Yaohui Zhang
This paper reports an optimized design of internal matching circuit for RF LDMOS power transistors. Efforts are mainly focused on the implementation of output internal matching circuit design, where a Shunt-L network structure is adopted. Computer-aided design (CAD) tools are employed to help rearrange the layout of bonding wire arrays to achieve a more uniform current distribution. Consequently, better robustness and RF performance can be obtained at the same time. With this technique, a RF LDMOS power transistor used at 2.14GHz is realized with saturation power of 51.3dBm and maximum efficiency of 63.8%.
{"title":"Internal matching circuit design of RF LDMOS power transistor","authors":"Liang-Yong Song, Yaohui Zhang","doi":"10.1109/ICAM.2016.7813554","DOIUrl":"https://doi.org/10.1109/ICAM.2016.7813554","url":null,"abstract":"This paper reports an optimized design of internal matching circuit for RF LDMOS power transistors. Efforts are mainly focused on the implementation of output internal matching circuit design, where a Shunt-L network structure is adopted. Computer-aided design (CAD) tools are employed to help rearrange the layout of bonding wire arrays to achieve a more uniform current distribution. Consequently, better robustness and RF performance can be obtained at the same time. With this technique, a RF LDMOS power transistor used at 2.14GHz is realized with saturation power of 51.3dBm and maximum efficiency of 63.8%.","PeriodicalId":179100,"journal":{"name":"2016 International Conference on Integrated Circuits and Microsystems (ICICM)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133594910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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