Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189816
P. Hower
A new model is proposed that accounts for the dynamics of charge removal for a device which is initially in deep or "classical" saturation. An experimental check of the model shows good agreement with measured values of storage time and VBE(t) and vCE(t) waveforms during the turn-off interval. An additional feature of the model is the possibility of introducing the action of circuit elements in an interactive manner so that device behavior in an actual switching circuit can be predicted. Finally, the possibility of predicting the onset of second breakdown is discussed.
{"title":"A model for turn-off in bipolar transistors","authors":"P. Hower","doi":"10.1109/IEDM.1980.189816","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189816","url":null,"abstract":"A new model is proposed that accounts for the dynamics of charge removal for a device which is initially in deep or \"classical\" saturation. An experimental check of the model shows good agreement with measured values of storage time and VBE(t) and vCE(t) waveforms during the turn-off interval. An additional feature of the model is the possibility of introducing the action of circuit elements in an interactive manner so that device behavior in an actual switching circuit can be predicted. Finally, the possibility of predicting the onset of second breakdown is discussed.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133211730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189765
H. Yamasaki, G. W. Keithley
Electron beam defined 0.5 µ gate low noise FETs have been made using various types of GaAs channel layers in order to correlate the method of material preparation with device performance in the frequency range between 12 GHz and 30 GHz. The channel layers were made by vapor phase epitaxy (VPE), ion implanted liquid phase epitaxy (LPE) and direct ion implantation into boat grown (HB) Cr-doped and liquid encapsulated Czochralski (LEC) undoped substrates. The devices, which have a gate width of 300 µm, have demonstrated excellent high gain and low noise performance over a wide range of frequencies from 12 GHz through 30 GHz. Device fabricated on VPE delivered 6.2 dB gain across a 2.5 GHz bandwidth at 30 GHz. The latter result was obtained from a single stage 30 GHz Waveguide/Microstrip amplifier, This amplifier, although not optimized for noise, has demonstrated less than a 5 dB noise figure across its bandwidth, In this paper we will discuss the state-of-the-art high frequency device performance and the device characterization results as related to the method of channel layer fabrication.
{"title":"High performance low noise FETs operating from X-band through Ka-band","authors":"H. Yamasaki, G. W. Keithley","doi":"10.1109/IEDM.1980.189765","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189765","url":null,"abstract":"Electron beam defined 0.5 µ gate low noise FETs have been made using various types of GaAs channel layers in order to correlate the method of material preparation with device performance in the frequency range between 12 GHz and 30 GHz. The channel layers were made by vapor phase epitaxy (VPE), ion implanted liquid phase epitaxy (LPE) and direct ion implantation into boat grown (HB) Cr-doped and liquid encapsulated Czochralski (LEC) undoped substrates. The devices, which have a gate width of 300 µm, have demonstrated excellent high gain and low noise performance over a wide range of frequencies from 12 GHz through 30 GHz. Device fabricated on VPE delivered 6.2 dB gain across a 2.5 GHz bandwidth at 30 GHz. The latter result was obtained from a single stage 30 GHz Waveguide/Microstrip amplifier, This amplifier, although not optimized for noise, has demonstrated less than a 5 dB noise figure across its bandwidth, In this paper we will discuss the state-of-the-art high frequency device performance and the device characterization results as related to the method of channel layer fabrication.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114062535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189971
D. Lamb, P. Roberts, R. Belt, D. Bostick, H. Stevens, S. Pai, D. Burbank
{"title":"A sub-nanosecond ISL technology demonstrated in a 400 mil × 400 mil VLSI chip","authors":"D. Lamb, P. Roberts, R. Belt, D. Bostick, H. Stevens, S. Pai, D. Burbank","doi":"10.1109/IEDM.1980.189971","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189971","url":null,"abstract":"","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122387285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189896
D. Takács, U. Schwabe, U. Burker
In a 1 µm Si-gate technology, channel length and temperature have a strong impact on the electrical device parameters. Experimental data on the influence of the channel length and the temperature on threshold voltage, breakdown voltage and subthreshold currents are presented for different channel dopings and S/D junction depths. The results are discussed with regard to the electrical device tolerances and to limitations in standard Si-gate technologies.
{"title":"The influence of temperature on the tolerances of MOS-transistors in a 1 µm technology","authors":"D. Takács, U. Schwabe, U. Burker","doi":"10.1109/IEDM.1980.189896","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189896","url":null,"abstract":"In a 1 µm Si-gate technology, channel length and temperature have a strong impact on the electrical device parameters. Experimental data on the influence of the channel length and the temperature on threshold voltage, breakdown voltage and subthreshold currents are presented for different channel dopings and S/D junction depths. The results are discussed with regard to the electrical device tolerances and to limitations in standard Si-gate technologies.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124223407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189807
W. D. Raburn
A model is presented for the parasitic SCR in bulk CMOS. The model shows the exact way that the shunting resistances alter the terminal V-I characteristics. It describes a negative differential resistance (NDR) range which is the only requirement for latch-up if certain biasing conditions are met. The NDR region will start when the product of current and shunting resistance equals the built in voltage and will occur for an+ ap< 1 (or βnβp< 1). The conditions for the center junction to become forward biased are given. If these conditions are met, the SCR will latch-up. If these conditions are not met, latch-up becomes dependent on the biasing circuit.
{"title":"A model for the parasitic SCR in bulk CMOS","authors":"W. D. Raburn","doi":"10.1109/IEDM.1980.189807","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189807","url":null,"abstract":"A model is presented for the parasitic SCR in bulk CMOS. The model shows the exact way that the shunting resistances alter the terminal V-I characteristics. It describes a negative differential resistance (NDR) range which is the only requirement for latch-up if certain biasing conditions are met. The NDR region will start when the product of current and shunting resistance equals the built in voltage and will occur for an+ ap< 1 (or βnβp< 1). The conditions for the center junction to become forward biased are given. If these conditions are met, the SCR will latch-up. If these conditions are not met, latch-up becomes dependent on the biasing circuit.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121239332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189759
G. David, J. Vallée, J. Lebailly
This paper deals with the design, processing, and electrical characteristics of a new monolithic power device comprising a V.MOS Field-Effect-Transistor as the driver component, and a bipolar low Emitter Concentration Transistor as the power output component. The study of the device has been made on the base of a 3,9 × 3,9 mm2chip. The device design is such that there is a complete compatibility between processing of the multiepitaxial bipolar power transistor and of the V.MOS transistor. The influence of the main parameters of the structure was studied, including : - Channel width of the V.MOS - Gate oxide thickness - Characteristics of the epitaxial layers A diffusion processing insuring a high gain for the bipolar transistor and a low threshold voltage of the V.MOS F.E.T. has been developed. The electrical measurements exhibit nice characteristics for medium voltage applications: - low threshold voltage : Vth< 2,5 V - high forward transconductance : gm> 5 A/V - low saturation voltage drop : Vsat< 1.8 V (for Ic = 10 A, VG= 10 V) - medium breakdow-voltage : BV> 90 V.
{"title":"A new V.MOS/Bipolar Darlington transistor for power applications","authors":"G. David, J. Vallée, J. Lebailly","doi":"10.1109/IEDM.1980.189759","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189759","url":null,"abstract":"This paper deals with the design, processing, and electrical characteristics of a new monolithic power device comprising a V.MOS Field-Effect-Transistor as the driver component, and a bipolar low Emitter Concentration Transistor as the power output component. The study of the device has been made on the base of a 3,9 × 3,9 mm2chip. The device design is such that there is a complete compatibility between processing of the multiepitaxial bipolar power transistor and of the V.MOS transistor. The influence of the main parameters of the structure was studied, including : - Channel width of the V.MOS - Gate oxide thickness - Characteristics of the epitaxial layers A diffusion processing insuring a high gain for the bipolar transistor and a low threshold voltage of the V.MOS F.E.T. has been developed. The electrical measurements exhibit nice characteristics for medium voltage applications: - low threshold voltage : Vth< 2,5 V - high forward transconductance : gm> 5 A/V - low saturation voltage drop : Vsat< 1.8 V (for Ic = 10 A, VG= 10 V) - medium breakdow-voltage : BV> 90 V.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128916749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189905
J. Kupec, W. Gosney, V. McKenny, V. Kowshik
An electrically-erasable, floating-gate PROM cell utilizing three levels of polysilicon is described. The cell is programmed via a channel injection mechanism similar to EPROMS. Erasure is accomplished with the third level of polysilicon which serves as an erase electrode causing field emission of electrons from the edges of the floating-gate. Conventional NMOS processing is used and all oxides are thicker than 800A. An adaptive erase feature is used to prevent over erasure into depletion and eliminates the requirement of a gating or series enhancement transistor. Endurance (ability to program and erase repeatedly), of a single cell is greater than 1000 cycles and is limited by electron trapping. Data retention has been experimentally determined to be comparable to EPROMs (greater than 10 years).
{"title":"Triple level polysilicon E2PROM with single transistor per bit","authors":"J. Kupec, W. Gosney, V. McKenny, V. Kowshik","doi":"10.1109/IEDM.1980.189905","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189905","url":null,"abstract":"An electrically-erasable, floating-gate PROM cell utilizing three levels of polysilicon is described. The cell is programmed via a channel injection mechanism similar to EPROMS. Erasure is accomplished with the third level of polysilicon which serves as an erase electrode causing field emission of electrons from the edges of the floating-gate. Conventional NMOS processing is used and all oxides are thicker than 800A. An adaptive erase feature is used to prevent over erasure into depletion and eliminates the requirement of a gating or series enhancement transistor. Endurance (ability to program and erase repeatedly), of a single cell is greater than 1000 cycles and is limited by electron trapping. Data retention has been experimentally determined to be comparable to EPROMs (greater than 10 years).","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128538503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189744
P. Chatterjee, J. Leiss
An analytic-predictor model which describes phenomena observed in small geometry MOSFETs is presented. I-V characteristics from subthreshold through saturation are predicted within the bounds of process parameter variations using only physical and structural constants as inputs. A key to the success of this model is the Dynamic Average Doping Transformation which accounts for the doping profile within the channel and is supported by experimental data. Process-device-circuit trade-offs may be examined using this model and a desk top calculator.
{"title":"An analytic charge-sharing predictor model for submicron MOSFETs","authors":"P. Chatterjee, J. Leiss","doi":"10.1109/IEDM.1980.189744","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189744","url":null,"abstract":"An analytic-predictor model which describes phenomena observed in small geometry MOSFETs is presented. I-V characteristics from subthreshold through saturation are predicted within the bounds of process parameter variations using only physical and structural constants as inputs. A key to the success of this model is the Dynamic Average Doping Transformation which accounts for the doping profile within the channel and is supported by experimental data. Process-device-circuit trade-offs may be examined using this model and a desk top calculator.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"214 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115977533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189952
P. Shah, G. Pollack, G. Varnell, C. Rhodes, D. Kang, W. Bruncke
A 22 ns scaled 4K-bit static RAM (SRAM) has been fabricated on a 12K mil2chip demonstrating high density electron beam direct slice writing lithography and dry etch processes. This 2 µm design rule, LSI vehicle used a vector-scanned electron-beam exposure system with a capability of 2 µm feature definition, 0.25 µm level-to-level registration, and auto chip-by-chip alignment. High speed, high resolution positive and negative electron-beam resists were used for all patterning steps. All implanted scaled MOS process with dry etching techniques for Si, SiO2, and Si3N4were used to realize 22ns access time 4KSRAM at full temperature. A gate delay of 0.18ns and a speed power product of 0.08 pJ were realized on a 1 µm channel ring oscillator with this process.
{"title":"A 22ns 4K-bit SRAM fabricated with direct electron beam lithography","authors":"P. Shah, G. Pollack, G. Varnell, C. Rhodes, D. Kang, W. Bruncke","doi":"10.1109/IEDM.1980.189952","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189952","url":null,"abstract":"A 22 ns scaled 4K-bit static RAM (SRAM) has been fabricated on a 12K mil2chip demonstrating high density electron beam direct slice writing lithography and dry etch processes. This 2 µm design rule, LSI vehicle used a vector-scanned electron-beam exposure system with a capability of 2 µm feature definition, 0.25 µm level-to-level registration, and auto chip-by-chip alignment. High speed, high resolution positive and negative electron-beam resists were used for all patterning steps. All implanted scaled MOS process with dry etching techniques for Si, SiO2, and Si3N4were used to realize 22ns access time 4KSRAM at full temperature. A gate delay of 0.18ns and a speed power product of 0.08 pJ were realized on a 1 µm channel ring oscillator with this process.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117251214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/IEDM.1980.189825
G. Dohler, B. Wilson
A small signal theory of the Peniotron including space charges, is presented. The calculations show that two different modes of operation exist. The original mode (resonance mode) follows the typical gain behavior of crossed-field amplifiers, although space charge effects can be neglected. The other mode, referred to as synchronous mode, exhibits the typical dispersion of "0" type traveling wave tubes, and space charge effect are important: the bandwidth appears to be much wider, and the gain is proportional to the cubic root of the current.
{"title":"A small signal theory of the peniotron","authors":"G. Dohler, B. Wilson","doi":"10.1109/IEDM.1980.189825","DOIUrl":"https://doi.org/10.1109/IEDM.1980.189825","url":null,"abstract":"A small signal theory of the Peniotron including space charges, is presented. The calculations show that two different modes of operation exist. The original mode (resonance mode) follows the typical gain behavior of crossed-field amplifiers, although space charge effects can be neglected. The other mode, referred to as synchronous mode, exhibits the typical dispersion of \"0\" type traveling wave tubes, and space charge effect are important: the bandwidth appears to be much wider, and the gain is proportional to the cubic root of the current.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"7 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114151134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：