Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425767
Myounggon Kang, Ki-Whan Song, Hoeju Chung, Jinyoung Kim, Yeong-Taek Lee, Changhyun Kim
A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and Cin (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5 kV and MM-500 V stress. The input capacitance, Cin, was measured to be 1.5 pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277 ps (55.3% of UI) in DDR3 interface at 2 Gbps operation due to the Cin reduction effect.
{"title":"SCR-based ESD protection for high bandwidth DRAMs","authors":"Myounggon Kang, Ki-Whan Song, Hoeju Chung, Jinyoung Kim, Yeong-Taek Lee, Changhyun Kim","doi":"10.1109/ASSCC.2007.4425767","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425767","url":null,"abstract":"A modified SCR (silicon controlled rectifier) is proposed as an ESD protection for high speed signaling systems. With low voltage triggering (LVT) characteristics and good turn-on uniformity, the proposed SCR scheme accomplishes both goals, high discharging capability and Cin (input capacitance) reduction. The fabricated chips with the new ESD scheme passed the severe package level EOS test conditions such as HBM-5 kV and MM-500 V stress. The input capacitance, Cin, was measured to be 1.5 pF which satisfies the DDR3-1066 specification with enough margin. We have observed in SPICE simulation that the data eye can be enlarged to 277 ps (55.3% of UI) in DDR3 interface at 2 Gbps operation due to the Cin reduction effect.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127793009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425681
R. Casanova, Á. Diéguez, A. Sanuy, A. Arbat, O. Alonso, J. Canals, J. Samitier
This paper is focused on the main issues of designing a SoC for a completely autonomous mm3-sized microrobot. It is described how all the electronics are included in a unique chip, the special requirements in the assembly process and how the hard constraints in power consumption are managed. Power in the robot is delivered by solar cells mounted on top and two supercapacitors which act as batteries. The maximum available energy for the SoC is 400 muW for driving the robot actuators and 1 mW for data processing. The special architecture of the SoC and power awareness are required to manage the very low available power.
{"title":"An ultra low power IC for an autonomous mm3-sized microrobot","authors":"R. Casanova, Á. Diéguez, A. Sanuy, A. Arbat, O. Alonso, J. Canals, J. Samitier","doi":"10.1109/ASSCC.2007.4425681","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425681","url":null,"abstract":"This paper is focused on the main issues of designing a SoC for a completely autonomous mm3-sized microrobot. It is described how all the electronics are included in a unique chip, the special requirements in the assembly process and how the hard constraints in power consumption are managed. Power in the robot is delivered by solar cells mounted on top and two supercapacitors which act as batteries. The maximum available energy for the SoC is 400 muW for driving the robot actuators and 1 mW for data processing. The special architecture of the SoC and power awareness are required to manage the very low available power.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126432765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425682
Joo-Young Kim, H. Yoo
In this paper, we present a bitwise competition logic (BCL) for the high performance and area efficient digital comparator. It compares two integer numbers using the location of the first 1 from the MSB, without arithmetic computations. The detail circuits to implement BCL, pre-encoder and selection logics are explained. The implemented BCL comparator shows 16%, 38% and 30% improved result in propagation delay, transistor count, and physical area compared to the other types of comparators. Measurement waveforms of fabricated BCL comparator verify its feasibility and functionality.
{"title":"Bitwise Competition Logic for compact digital comparator","authors":"Joo-Young Kim, H. Yoo","doi":"10.1109/ASSCC.2007.4425682","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425682","url":null,"abstract":"In this paper, we present a bitwise competition logic (BCL) for the high performance and area efficient digital comparator. It compares two integer numbers using the location of the first 1 from the MSB, without arithmetic computations. The detail circuits to implement BCL, pre-encoder and selection logics are explained. The implemented BCL comparator shows 16%, 38% and 30% improved result in propagation delay, transistor count, and physical area compared to the other types of comparators. Measurement waveforms of fabricated BCL comparator verify its feasibility and functionality.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124699348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425728
T. Finateu, I. Miro-Panadès, F. Boissieres, J. Bégueret, Y. Deval, D. Belot, F. Badets
A SigmaDelta phase-interpolation direct digital synthesizer (DDS) is presented. This DDS generates frequencies from 400 MHz up to 500 MHz. Phase interpolation uses dual slope integration on a single capacitor and current is provided by a digital to analog converter (DAC). The SigmaDelta enables high frequency resolution and shapes quantization noise. The DDS has been integrated on a 65-nm CMOS STMicroclectronics technology. The power consumption is about 29 mVV without buffers under 1.2 V for a 500-MHz operating frequency.
{"title":"A 500-MHz ΣΔ phase-interpolation direct digital synthesizer","authors":"T. Finateu, I. Miro-Panadès, F. Boissieres, J. Bégueret, Y. Deval, D. Belot, F. Badets","doi":"10.1109/ASSCC.2007.4425728","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425728","url":null,"abstract":"A SigmaDelta phase-interpolation direct digital synthesizer (DDS) is presented. This DDS generates frequencies from 400 MHz up to 500 MHz. Phase interpolation uses dual slope integration on a single capacitor and current is provided by a digital to analog converter (DAC). The SigmaDelta enables high frequency resolution and shapes quantization noise. The DDS has been integrated on a 65-nm CMOS STMicroclectronics technology. The power consumption is about 29 mVV without buffers under 1.2 V for a 500-MHz operating frequency.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134189924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425755
T. Ogino, T. Yoshikawa, M. Nagata
A current-mode data transceiver for mobile applications is described. This transceiver has a multi-level current transmitter with simple clock recovery and a low-input impedance receiver, and realizes low-voltage swing (about 20 mV) with 150-300 muA drive current at 625 Mbps by differential manner. The transceiver operates with a 1.5-V single power supply, and consumes 3 mV including transmitter and receiver when simultaneous data and clock transmission at 625 Mbps is achieved through a single differential I/O connecting the transmitter and receiver pair.
{"title":"A low-power current-mode transceiver with simultaneous data and clock transmission at 625Mb/s, 3 mW in 1.5 V for mobile applications","authors":"T. Ogino, T. Yoshikawa, M. Nagata","doi":"10.1109/ASSCC.2007.4425755","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425755","url":null,"abstract":"A current-mode data transceiver for mobile applications is described. This transceiver has a multi-level current transmitter with simple clock recovery and a low-input impedance receiver, and realizes low-voltage swing (about 20 mV) with 150-300 muA drive current at 625 Mbps by differential manner. The transceiver operates with a 1.5-V single power supply, and consumes 3 mV including transmitter and receiver when simultaneous data and clock transmission at 625 Mbps is achieved through a single differential I/O connecting the transmitter and receiver pair.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130485760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425715
Hong-Lin Chu, Shen-Iuan Liu
This paper presents a 10 Gb/s burst-mode transimpedance amplifier (BMTIA), which has been fabricated in a 0.13 mum CMOS process. For the burst-mode receivers in passive optical networks (PONs), the preamplifier has to receive the burst-mode data packages with different amplitudes and provides a short settling time which is required for high data transmission efficiency. In this paper, a 10 Gb/s BMTIA is presented to achieve a wide dynamic range of 42.5 dB and fast settling time within Ins. It dissipates 7.2 mW excluding output buffer from a single 1.2 V supply voltage.
提出了一种以0.13 μ m CMOS工艺制作的10 Gb/s突发模跨阻放大器。对于无源光网络中的突发模式接收机，前置放大器必须接收不同幅度的突发模式数据包，并提供较短的建立时间，以保证较高的数据传输效率。本文提出了一种10gb /s的BMTIA，可实现42.5 dB的宽动态范围和在Ins内的快速稳定时间。它的功耗为7.2 mW，不包括来自单个1.2 V电源电压的输出缓冲。
{"title":"A 10Gb/s burst-mode transimpedance amplifier in 0.13μm CMOS","authors":"Hong-Lin Chu, Shen-Iuan Liu","doi":"10.1109/ASSCC.2007.4425715","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425715","url":null,"abstract":"This paper presents a 10 Gb/s burst-mode transimpedance amplifier (BMTIA), which has been fabricated in a 0.13 mum CMOS process. For the burst-mode receivers in passive optical networks (PONs), the preamplifier has to receive the burst-mode data packages with different amplitudes and provides a short settling time which is required for high data transmission efficiency. In this paper, a 10 Gb/s BMTIA is presented to achieve a wide dynamic range of 42.5 dB and fast settling time within Ins. It dissipates 7.2 mW excluding output buffer from a single 1.2 V supply voltage.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125110158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425706
Jiann-Jong Chen, F. Yang, Che-Min Kung, Bao-Peng Lai, Yuh-Shyan Hwang
A capacitor-free fast-transient-response low-dropout voltage regulator (LDO) with dual-loop controlled paths is presented in this paper. This technique can make the transient response to be faster than other LDOs with traditional controlled loop. Especially, the performance of settling time of proposed LDO is excellent without off-chip capacitors. With 1.5 V power supply voltage, the output voltage is designed as 1.2V. The prototype of the LDO is fabricated with TSMC 0.35-mum DPQM CMOS processes. The active area is only 360 mum times 345 mum.
提出了一种具有双环控制路径的无电容快速瞬态响应低降稳压器(LDO)。该技术可以使其瞬态响应速度比传统控制环的ldo更快。特别是在没有片外电容的情况下，LDO的稳定时间性能非常好。电源电压为1.5 V，输出电压设计为1.2V。LDO的原型采用台积电0.35 μ m DPQM CMOS工艺制作。活动面积只有360mm乘以345mm。
{"title":"A capacitor-free fast-transient-response LDO with dual-loop controlled paths","authors":"Jiann-Jong Chen, F. Yang, Che-Min Kung, Bao-Peng Lai, Yuh-Shyan Hwang","doi":"10.1109/ASSCC.2007.4425706","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425706","url":null,"abstract":"A capacitor-free fast-transient-response low-dropout voltage regulator (LDO) with dual-loop controlled paths is presented in this paper. This technique can make the transient response to be faster than other LDOs with traditional controlled loop. Especially, the performance of settling time of proposed LDO is excellent without off-chip capacitors. With 1.5 V power supply voltage, the output voltage is designed as 1.2V. The prototype of the LDO is fabricated with TSMC 0.35-mum DPQM CMOS processes. The active area is only 360 mum times 345 mum.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129687736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425742
Chan Tat Fu, H. Luong
This paper presents a CMOS linear-in-dB variable gain amplifier (VGA) that provides a variable gain range over 90 dB with 3 dB bandwidth greater than 400 MHz at 54 dB gain. The maximum output 1 dB compression point is 9 dBm. Maximum gain error is +/-2 dB. It consumes total 22 mW with 1.8 V supply, including control circuit. This VGA is fabricated in TSMC 0.18 um CMOS process and demonstrate the performance of the proposed dB-linear VGA.
本文介绍了一种CMOS线性-in-dB可变增益放大器(VGA)，它在54 dB增益下提供超过90db的可变增益范围，3db带宽大于400mhz。最大输出1db压缩点为9dbm。最大增益误差为+/-2 dB。它的总功耗为22mw, 1.8 V电源，包括控制电路。该VGA采用台积电0.18 um CMOS工艺制造，并展示了所提出的db线性VGA的性能。
{"title":"A CMOS linear-in-dB high-linearity variable-gain amplifier for UWB receivers","authors":"Chan Tat Fu, H. Luong","doi":"10.1109/ASSCC.2007.4425742","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425742","url":null,"abstract":"This paper presents a CMOS linear-in-dB variable gain amplifier (VGA) that provides a variable gain range over 90 dB with 3 dB bandwidth greater than 400 MHz at 54 dB gain. The maximum output 1 dB compression point is 9 dBm. Maximum gain error is +/-2 dB. It consumes total 22 mW with 1.8 V supply, including control circuit. This VGA is fabricated in TSMC 0.18 um CMOS process and demonstrate the performance of the proposed dB-linear VGA.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130059920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425753
Han Bi, Yehui Sun, Kai Lei, Zixin Wu, Xinqing Chen, Song Gao, Junning Wang, Yongyi Wu, Hui Wang
A quad 1-10 Gb/s serial transceiver in 90 nm digital CMOS technology is presented in this paper. A combination of transmitter pre-emphasis and receiver equalization is used. It can be used for different data rates and short-reach/long-reach applications with low overhead in area and power consumption. It is able to run across a 60-inch FR4 PCB trace with BER<10-12 at 3.125 Gb/s while consuming 70 mW/channel. At 10 Gb/s, it consumes 98 mW/channel to run across a 10-inch FR4 PCB trace and 90mW/channcl to run across a 4-inch FR4 PCB trace. Its die area is 1.6 mm2.
{"title":"A quad 1–10Gb/s serial transceiver in 90nm CMOS","authors":"Han Bi, Yehui Sun, Kai Lei, Zixin Wu, Xinqing Chen, Song Gao, Junning Wang, Yongyi Wu, Hui Wang","doi":"10.1109/ASSCC.2007.4425753","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425753","url":null,"abstract":"A quad 1-10 Gb/s serial transceiver in 90 nm digital CMOS technology is presented in this paper. A combination of transmitter pre-emphasis and receiver equalization is used. It can be used for different data rates and short-reach/long-reach applications with low overhead in area and power consumption. It is able to run across a 60-inch FR4 PCB trace with BER<10-12 at 3.125 Gb/s while consuming 70 mW/channel. At 10 Gb/s, it consumes 98 mW/channel to run across a 10-inch FR4 PCB trace and 90mW/channcl to run across a 4-inch FR4 PCB trace. Its die area is 1.6 mm2.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130893069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425761
Xinkai Chen, Hanjun Jiang, Xiao Wen Li, Zhihua Wang
This paper presents the design of a novel compression method for wireless image sensor node. In order to meet the requirement of the wireless image sensor node, a dedicated filtering procedure is developed for raw Bayer CFA pattern. JPEG-LS encoder follows the filtering procedure to compress the data. The parallel and pipeline structure are chosen for the purpose of high throughput and real-time operation. The compression method is implemented using UMC 0.18 mum technology. The test results shown that the image with VGA (640times480) resolution and frame rate 15 fps can be achieved with the same clock frequency with the CMOS image sensor.
{"title":"A novel compression method for wireless image sensor node","authors":"Xinkai Chen, Hanjun Jiang, Xiao Wen Li, Zhihua Wang","doi":"10.1109/ASSCC.2007.4425761","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425761","url":null,"abstract":"This paper presents the design of a novel compression method for wireless image sensor node. In order to meet the requirement of the wireless image sensor node, a dedicated filtering procedure is developed for raw Bayer CFA pattern. JPEG-LS encoder follows the filtering procedure to compress the data. The parallel and pipeline structure are chosen for the purpose of high throughput and real-time operation. The compression method is implemented using UMC 0.18 mum technology. The test results shown that the image with VGA (640times480) resolution and frame rate 15 fps can be achieved with the same clock frequency with the CMOS image sensor.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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