Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425768
K. Matsufuji, T. Namekawa, H. Nakano, H. Ito, O. Wada, N. Otsuka
A pure CMOS one-time programmable (PCOP) memory using an antifuse is presented. PCOP memory adopts two-port cell architecture implemented in a matrix structure. This architecture achieves optimization of performance both for programming and reading. Furthermore, it solves the write disturb problem and realizes pseudo "1" read test. An 8 Kbit macro is developed utilizing a 65 nm pure CMOS logic technology. The cell area and the macro size are 15.3 mum2 and 0.244 mm2, respectively.
{"title":"A 65nm Pure CMOS one-time programmable memory using a two-port antifuse cell implemented in a matrix structure","authors":"K. Matsufuji, T. Namekawa, H. Nakano, H. Ito, O. Wada, N. Otsuka","doi":"10.1109/ASSCC.2007.4425768","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425768","url":null,"abstract":"A pure CMOS one-time programmable (PCOP) memory using an antifuse is presented. PCOP memory adopts two-port cell architecture implemented in a matrix structure. This architecture achieves optimization of performance both for programming and reading. Furthermore, it solves the write disturb problem and realizes pseudo \"1\" read test. An 8 Kbit macro is developed utilizing a 65 nm pure CMOS logic technology. The cell area and the macro size are 15.3 mum2 and 0.244 mm2, respectively.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123559382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425712
Y. Kawamura
A programmable autonomous address-control-memory architecture (PA3) which supports memory based reconfigurable microcomputer (user structured microcomputer) is proposed. The PA3 provides finite autonomous device and executes the state transition control without CPU. The PA3 can be directly accessed as memory and support logic operation circuit of counter, and PWM, etc. When the logical function is mounted on silicon using the PA3, there is no need to relocate and rewire like FPGA. Each logic function module is achieved by loading the library which include logic function and wiring information. The performance depends on the characteristic of SRAM. The Standards bus interface of PA3 also supports both memory and peripheral buses in a microcomputer. The PA3 modeling and evaluation of the basic logical operation / function modules have been simulated.
{"title":"A reconfigurable microcomputer system with PA3 (Programmable Autonomous Address-control-memory Architecture)","authors":"Y. Kawamura","doi":"10.1109/ASSCC.2007.4425712","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425712","url":null,"abstract":"A programmable autonomous address-control-memory architecture (PA3) which supports memory based reconfigurable microcomputer (user structured microcomputer) is proposed. The PA3 provides finite autonomous device and executes the state transition control without CPU. The PA3 can be directly accessed as memory and support logic operation circuit of counter, and PWM, etc. When the logical function is mounted on silicon using the PA3, there is no need to relocate and rewire like FPGA. Each logic function module is achieved by loading the library which include logic function and wiring information. The performance depends on the characteristic of SRAM. The Standards bus interface of PA3 also supports both memory and peripheral buses in a microcomputer. The PA3 modeling and evaluation of the basic logical operation / function modules have been simulated.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120964305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425681
R. Casanova, Á. Diéguez, A. Sanuy, A. Arbat, O. Alonso, J. Canals, J. Samitier
This paper is focused on the main issues of designing a SoC for a completely autonomous mm3-sized microrobot. It is described how all the electronics are included in a unique chip, the special requirements in the assembly process and how the hard constraints in power consumption are managed. Power in the robot is delivered by solar cells mounted on top and two supercapacitors which act as batteries. The maximum available energy for the SoC is 400 muW for driving the robot actuators and 1 mW for data processing. The special architecture of the SoC and power awareness are required to manage the very low available power.
{"title":"An ultra low power IC for an autonomous mm3-sized microrobot","authors":"R. Casanova, Á. Diéguez, A. Sanuy, A. Arbat, O. Alonso, J. Canals, J. Samitier","doi":"10.1109/ASSCC.2007.4425681","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425681","url":null,"abstract":"This paper is focused on the main issues of designing a SoC for a completely autonomous mm3-sized microrobot. It is described how all the electronics are included in a unique chip, the special requirements in the assembly process and how the hard constraints in power consumption are managed. Power in the robot is delivered by solar cells mounted on top and two supercapacitors which act as batteries. The maximum available energy for the SoC is 400 muW for driving the robot actuators and 1 mW for data processing. The special architecture of the SoC and power awareness are required to manage the very low available power.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126432765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425728
T. Finateu, I. Miro-Panadès, F. Boissieres, J. Bégueret, Y. Deval, D. Belot, F. Badets
A SigmaDelta phase-interpolation direct digital synthesizer (DDS) is presented. This DDS generates frequencies from 400 MHz up to 500 MHz. Phase interpolation uses dual slope integration on a single capacitor and current is provided by a digital to analog converter (DAC). The SigmaDelta enables high frequency resolution and shapes quantization noise. The DDS has been integrated on a 65-nm CMOS STMicroclectronics technology. The power consumption is about 29 mVV without buffers under 1.2 V for a 500-MHz operating frequency.
{"title":"A 500-MHz ΣΔ phase-interpolation direct digital synthesizer","authors":"T. Finateu, I. Miro-Panadès, F. Boissieres, J. Bégueret, Y. Deval, D. Belot, F. Badets","doi":"10.1109/ASSCC.2007.4425728","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425728","url":null,"abstract":"A SigmaDelta phase-interpolation direct digital synthesizer (DDS) is presented. This DDS generates frequencies from 400 MHz up to 500 MHz. Phase interpolation uses dual slope integration on a single capacitor and current is provided by a digital to analog converter (DAC). The SigmaDelta enables high frequency resolution and shapes quantization noise. The DDS has been integrated on a 65-nm CMOS STMicroclectronics technology. The power consumption is about 29 mVV without buffers under 1.2 V for a 500-MHz operating frequency.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134189924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425755
T. Ogino, T. Yoshikawa, M. Nagata
A current-mode data transceiver for mobile applications is described. This transceiver has a multi-level current transmitter with simple clock recovery and a low-input impedance receiver, and realizes low-voltage swing (about 20 mV) with 150-300 muA drive current at 625 Mbps by differential manner. The transceiver operates with a 1.5-V single power supply, and consumes 3 mV including transmitter and receiver when simultaneous data and clock transmission at 625 Mbps is achieved through a single differential I/O connecting the transmitter and receiver pair.
{"title":"A low-power current-mode transceiver with simultaneous data and clock transmission at 625Mb/s, 3 mW in 1.5 V for mobile applications","authors":"T. Ogino, T. Yoshikawa, M. Nagata","doi":"10.1109/ASSCC.2007.4425755","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425755","url":null,"abstract":"A current-mode data transceiver for mobile applications is described. This transceiver has a multi-level current transmitter with simple clock recovery and a low-input impedance receiver, and realizes low-voltage swing (about 20 mV) with 150-300 muA drive current at 625 Mbps by differential manner. The transceiver operates with a 1.5-V single power supply, and consumes 3 mV including transmitter and receiver when simultaneous data and clock transmission at 625 Mbps is achieved through a single differential I/O connecting the transmitter and receiver pair.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130485760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425751
Moon-Sang Hwang, Sangyoon Lee, Jeong-Kyoum Kim, Suhwan Kim, D. Jeong
A referenceless, continuous-rate, fast-locking CDR with an operating range of 180 Mb/s to 3.2 Gb/s is presented. The harmonic lock property of a rotational frequency detector and the maximum run-length limit of 8B10B encoded data are utilized to detect a harmonic lock and to accelerate acquisition process. A separate VCO control scheme is introduced to stabilize the loop with a modest amount of on-chip capacitance.
{"title":"A 180-Mb/s to 3.2-Gb/s, continuous-rate, fast-locking CDR without using external reference clock","authors":"Moon-Sang Hwang, Sangyoon Lee, Jeong-Kyoum Kim, Suhwan Kim, D. Jeong","doi":"10.1109/ASSCC.2007.4425751","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425751","url":null,"abstract":"A referenceless, continuous-rate, fast-locking CDR with an operating range of 180 Mb/s to 3.2 Gb/s is presented. The harmonic lock property of a rotational frequency detector and the maximum run-length limit of 8B10B encoded data are utilized to detect a harmonic lock and to accelerate acquisition process. A separate VCO control scheme is introduced to stabilize the loop with a modest amount of on-chip capacitance.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116317964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425761
Xinkai Chen, Hanjun Jiang, Xiao Wen Li, Zhihua Wang
This paper presents the design of a novel compression method for wireless image sensor node. In order to meet the requirement of the wireless image sensor node, a dedicated filtering procedure is developed for raw Bayer CFA pattern. JPEG-LS encoder follows the filtering procedure to compress the data. The parallel and pipeline structure are chosen for the purpose of high throughput and real-time operation. The compression method is implemented using UMC 0.18 mum technology. The test results shown that the image with VGA (640times480) resolution and frame rate 15 fps can be achieved with the same clock frequency with the CMOS image sensor.
{"title":"A novel compression method for wireless image sensor node","authors":"Xinkai Chen, Hanjun Jiang, Xiao Wen Li, Zhihua Wang","doi":"10.1109/ASSCC.2007.4425761","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425761","url":null,"abstract":"This paper presents the design of a novel compression method for wireless image sensor node. In order to meet the requirement of the wireless image sensor node, a dedicated filtering procedure is developed for raw Bayer CFA pattern. JPEG-LS encoder follows the filtering procedure to compress the data. The parallel and pipeline structure are chosen for the purpose of high throughput and real-time operation. The compression method is implemented using UMC 0.18 mum technology. The test results shown that the image with VGA (640times480) resolution and frame rate 15 fps can be achieved with the same clock frequency with the CMOS image sensor.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425715
Hong-Lin Chu, Shen-Iuan Liu
This paper presents a 10 Gb/s burst-mode transimpedance amplifier (BMTIA), which has been fabricated in a 0.13 mum CMOS process. For the burst-mode receivers in passive optical networks (PONs), the preamplifier has to receive the burst-mode data packages with different amplitudes and provides a short settling time which is required for high data transmission efficiency. In this paper, a 10 Gb/s BMTIA is presented to achieve a wide dynamic range of 42.5 dB and fast settling time within Ins. It dissipates 7.2 mW excluding output buffer from a single 1.2 V supply voltage.
提出了一种以0.13 μ m CMOS工艺制作的10 Gb/s突发模跨阻放大器。对于无源光网络中的突发模式接收机，前置放大器必须接收不同幅度的突发模式数据包，并提供较短的建立时间，以保证较高的数据传输效率。本文提出了一种10gb /s的BMTIA，可实现42.5 dB的宽动态范围和在Ins内的快速稳定时间。它的功耗为7.2 mW，不包括来自单个1.2 V电源电压的输出缓冲。
{"title":"A 10Gb/s burst-mode transimpedance amplifier in 0.13μm CMOS","authors":"Hong-Lin Chu, Shen-Iuan Liu","doi":"10.1109/ASSCC.2007.4425715","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425715","url":null,"abstract":"This paper presents a 10 Gb/s burst-mode transimpedance amplifier (BMTIA), which has been fabricated in a 0.13 mum CMOS process. For the burst-mode receivers in passive optical networks (PONs), the preamplifier has to receive the burst-mode data packages with different amplitudes and provides a short settling time which is required for high data transmission efficiency. In this paper, a 10 Gb/s BMTIA is presented to achieve a wide dynamic range of 42.5 dB and fast settling time within Ins. It dissipates 7.2 mW excluding output buffer from a single 1.2 V supply voltage.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125110158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425690
Jinn-Shyan Wang, Chun-Yuan Cheng, Yu-Chia Liu, Yi-Ming Wang
This paper presents the design of a 1.0 V 150-550 MHz 65 nm ADDLL using a novel coarse-fine architecture and differential circuit techniques. When running at 550 MHz, this nanometer ADDLL achieves a peak-to-peak jitter of only 5 ps with the shortest 4 locking cycles, while consumes only 0.67 muW/MHz, about 72% reduction compared to the existing most power efficient ADDLL.
本文提出了一个1.0 V 150-550 MHz的65 nm ADDLL的设计，采用了一种新颖的粗精结构和差分电路技术。当工作在550mhz时，该纳米ADDLL在最短的4个锁定周期内实现了5ps的峰间抖动，而功耗仅为0.67 muW/MHz，与现有最节能的ADDLL相比降低了约72%。
{"title":"A 0.67μW/MHz, 5ps jitter, 4 locking cycles, 65nm ADDLL","authors":"Jinn-Shyan Wang, Chun-Yuan Cheng, Yu-Chia Liu, Yi-Ming Wang","doi":"10.1109/ASSCC.2007.4425690","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425690","url":null,"abstract":"This paper presents the design of a 1.0 V 150-550 MHz 65 nm ADDLL using a novel coarse-fine architecture and differential circuit techniques. When running at 550 MHz, this nanometer ADDLL achieves a peak-to-peak jitter of only 5 ps with the shortest 4 locking cycles, while consumes only 0.67 muW/MHz, about 72% reduction compared to the existing most power efficient ADDLL.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-01DOI: 10.1109/ASSCC.2007.4425706
Jiann-Jong Chen, F. Yang, Che-Min Kung, Bao-Peng Lai, Yuh-Shyan Hwang
A capacitor-free fast-transient-response low-dropout voltage regulator (LDO) with dual-loop controlled paths is presented in this paper. This technique can make the transient response to be faster than other LDOs with traditional controlled loop. Especially, the performance of settling time of proposed LDO is excellent without off-chip capacitors. With 1.5 V power supply voltage, the output voltage is designed as 1.2V. The prototype of the LDO is fabricated with TSMC 0.35-mum DPQM CMOS processes. The active area is only 360 mum times 345 mum.
提出了一种具有双环控制路径的无电容快速瞬态响应低降稳压器(LDO)。该技术可以使其瞬态响应速度比传统控制环的ldo更快。特别是在没有片外电容的情况下，LDO的稳定时间性能非常好。电源电压为1.5 V，输出电压设计为1.2V。LDO的原型采用台积电0.35 μ m DPQM CMOS工艺制作。活动面积只有360mm乘以345mm。
{"title":"A capacitor-free fast-transient-response LDO with dual-loop controlled paths","authors":"Jiann-Jong Chen, F. Yang, Che-Min Kung, Bao-Peng Lai, Yuh-Shyan Hwang","doi":"10.1109/ASSCC.2007.4425706","DOIUrl":"https://doi.org/10.1109/ASSCC.2007.4425706","url":null,"abstract":"A capacitor-free fast-transient-response low-dropout voltage regulator (LDO) with dual-loop controlled paths is presented in this paper. This technique can make the transient response to be faster than other LDOs with traditional controlled loop. Especially, the performance of settling time of proposed LDO is excellent without off-chip capacitors. With 1.5 V power supply voltage, the output voltage is designed as 1.2V. The prototype of the LDO is fabricated with TSMC 0.35-mum DPQM CMOS processes. The active area is only 360 mum times 345 mum.","PeriodicalId":186095,"journal":{"name":"2007 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129687736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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