Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705950
Li Dong, Xiaoyan Gui, Ying Xie, Li Geng
This paper presents the design of a low power biomedical front-end (BFE) for Electroencephalogram (EEG)/Electrocorticography (ECoG) acquisition applications through 0.18 $mu m$ CMOS process. By balancing the design constrains of total input-referred noise of the BFE, gain and power of multi-channel LNAs, and resolution of the ADC, the BFE achieves power consumption of 6.2 $mu W$ per channel, for an 8-channel design. In addition, a 12-bit SAR ADC with data weighted averaging (DWA) calibrations is proposed to alleviate the design burdens in the low noise amplifier (LNA).
{"title":"An 8-Channel Biomedical Front-End (BFE) with 6.2-μW Per Channel for EEG/ECoG Acquisition","authors":"Li Dong, Xiaoyan Gui, Ying Xie, Li Geng","doi":"10.1109/CICTA.2018.8705950","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705950","url":null,"abstract":"This paper presents the design of a low power biomedical front-end (BFE) for Electroencephalogram (EEG)/Electrocorticography (ECoG) acquisition applications through 0.18 $mu m$ CMOS process. By balancing the design constrains of total input-referred noise of the BFE, gain and power of multi-channel LNAs, and resolution of the ADC, the BFE achieves power consumption of 6.2 $mu W$ per channel, for an 8-channel design. In addition, a 12-bit SAR ADC with data weighted averaging (DWA) calibrations is proposed to alleviate the design burdens in the low noise amplifier (LNA).","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124968618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706057
Ken Li, Yan Song, Li Dong, Li Geng
this paper presents a low-power 10-bit 200-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. By introducing a prediction logic, the ADC only needs to sample and quantize the difference between the input signal and the prediction value which is a rather low voltage. Thus some comparison cycles can be skipped and the power consumption is greatly saved. Conversion efficiency of the predicting logic with different interpolation orders is analyzed theoretically. The maximum efficiency improvement of 23% could be achieved comparing with that of 0th-order interpolation. A prototype oversampling SAR ADC with 2nd order of interpolation is designed with a standard 180nm CMOS technology. It achieves ENOB of 9.58 with total power of 574 nW and very low figure of merit (FoM) of 3.78 fJ/conv.-step.
{"title":"An oversampling SAR ADC with 2nd-order interpolation achieving maximum efficiency improvement of 23%","authors":"Ken Li, Yan Song, Li Dong, Li Geng","doi":"10.1109/CICTA.2018.8706057","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706057","url":null,"abstract":"this paper presents a low-power 10-bit 200-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. By introducing a prediction logic, the ADC only needs to sample and quantize the difference between the input signal and the prediction value which is a rather low voltage. Thus some comparison cycles can be skipped and the power consumption is greatly saved. Conversion efficiency of the predicting logic with different interpolation orders is analyzed theoretically. The maximum efficiency improvement of 23% could be achieved comparing with that of 0th-order interpolation. A prototype oversampling SAR ADC with 2nd order of interpolation is designed with a standard 180nm CMOS technology. It achieves ENOB of 9.58 with total power of 574 nW and very low figure of merit (FoM) of 3.78 fJ/conv.-step.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116293440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706052
Kaiyou Li, Jianping Guo
This paper presents an integrated receiver with 100dB-level dynamic range and mm-level accuracy for a time-of-flight (TOF) laser radar system. In this receiver, the differential current signals generated by the photodiode are fed into a trans-impedance amplifier (TIA) and a low-impedance amplifier (LIA) separately to achieve a wide single-shot measurement dynamic range. A timing discrimination scheme based on converting the incoming unipolar pulses into bipolar ones is adopted to reduce the walk errors. Simulation results show that the proposed receiver achieves a dynamic range of more than 1:200000 (106dB) while keeping the walk error less than ±42ps (±6.3mm in distance) without any need for complicated gain control techniques or troublesome calibration methods.
{"title":"A TOF Laser Radar Receiver with 100dB-Level Dynamic Range and mm-Level Accuracy","authors":"Kaiyou Li, Jianping Guo","doi":"10.1109/CICTA.2018.8706052","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706052","url":null,"abstract":"This paper presents an integrated receiver with 100dB-level dynamic range and mm-level accuracy for a time-of-flight (TOF) laser radar system. In this receiver, the differential current signals generated by the photodiode are fed into a trans-impedance amplifier (TIA) and a low-impedance amplifier (LIA) separately to achieve a wide single-shot measurement dynamic range. A timing discrimination scheme based on converting the incoming unipolar pulses into bipolar ones is adopted to reduce the walk errors. Simulation results show that the proposed receiver achieves a dynamic range of more than 1:200000 (106dB) while keeping the walk error less than ±42ps (±6.3mm in distance) without any need for complicated gain control techniques or troublesome calibration methods.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121862629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705710
Chang Cheng, Ting Ou, Deng Luo, Milin Zhang, Zhihua Wang
This paper proposed an attention evaluation system using 8-channel differential prefrontal EEG signals acquired from the forehead. A 16-channel neural signal acquisition module was designed and fabricated in TSMC 180nm CMOS process. It consists of chopper LNAs, switched-Capacitor programmable gain amplifiers and 12-bit SAR ADC. The proposed digital attention evaluation algorithm was implemented on FPGA, including IIR filters, calculation of the filtered neural signal strength indicator, SVM-based classifier.
{"title":"Design of an Attention Evaluation System with 16-Channel Differential Signal Acquisition","authors":"Chang Cheng, Ting Ou, Deng Luo, Milin Zhang, Zhihua Wang","doi":"10.1109/CICTA.2018.8705710","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705710","url":null,"abstract":"This paper proposed an attention evaluation system using 8-channel differential prefrontal EEG signals acquired from the forehead. A 16-channel neural signal acquisition module was designed and fabricated in TSMC 180nm CMOS process. It consists of chopper LNAs, switched-Capacitor programmable gain amplifiers and 12-bit SAR ADC. The proposed digital attention evaluation algorithm was implemented on FPGA, including IIR filters, calculation of the filtered neural signal strength indicator, SVM-based classifier.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127069215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706097
Shuang Cui, Yusong Mu, Ning Ding, Jiaqi Jiang, Yuchun Chang
This paper presents a charge compensated phototransistor for a high dynamic range linear-logarithmic CMOS image sensor. The pixel is based on the four-transistor active pixel structure which can automatically switch between the linear mode and logarithmic mode according to the incident light intensity. This paper also proposes a fixed pattern noise (FPN) correction technique for the proposed pixel sensor. The FPN caused by the threshold voltage variation of the transfer gate is corrected by the calibration method of two-step charge transfer. The prototype sensor consisting of a $160 times 200$ pixel array with the pixel pitch of $8 times 8 mu m^{2}$ is fabricated with a 0.18 $mu m$ 1P6M standard CMOS process. It is found that the dynamic range is achieved 169 dB and the FPN is reduced by 80%.
{"title":"Combined Linear-Logarithmic CMOS Image Sensor with FPN Calibration","authors":"Shuang Cui, Yusong Mu, Ning Ding, Jiaqi Jiang, Yuchun Chang","doi":"10.1109/CICTA.2018.8706097","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706097","url":null,"abstract":"This paper presents a charge compensated phototransistor for a high dynamic range linear-logarithmic CMOS image sensor. The pixel is based on the four-transistor active pixel structure which can automatically switch between the linear mode and logarithmic mode according to the incident light intensity. This paper also proposes a fixed pattern noise (FPN) correction technique for the proposed pixel sensor. The FPN caused by the threshold voltage variation of the transfer gate is corrected by the calibration method of two-step charge transfer. The prototype sensor consisting of a $160 times 200$ pixel array with the pixel pitch of $8 times 8 mu m^{2}$ is fabricated with a 0.18 $mu m$ 1P6M standard CMOS process. It is found that the dynamic range is achieved 169 dB and the FPN is reduced by 80%.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"14 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132531315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706048
Xiwei Huang, Jin Chen, Jixuan Liu, Yangbo Li, Junchao Wang, W. Xuan, Jinhong Guo
One lensfree microfluidic on-chip flowing cell imaging system with integrated SAW pumping is proposed in this article. The SAW device temperature responses are characterized to be below 40 °C so as not to harm cells. Different resolution enhancing techniques are implemented and compared. It is demonstrated that machine learning based methods exceed those interpolation based ones, and a training library of individual cell type helps improve the SSIM compared with a training library of combined cell types.
{"title":"Lensfree Microfluidic On-chip Flowing Cell Imaging with Integrated Surface Acoustic Wave Pumping","authors":"Xiwei Huang, Jin Chen, Jixuan Liu, Yangbo Li, Junchao Wang, W. Xuan, Jinhong Guo","doi":"10.1109/CICTA.2018.8706048","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706048","url":null,"abstract":"One lensfree microfluidic on-chip flowing cell imaging system with integrated SAW pumping is proposed in this article. The SAW device temperature responses are characterized to be below 40 °C so as not to harm cells. Different resolution enhancing techniques are implemented and compared. It is demonstrated that machine learning based methods exceed those interpolation based ones, and a training library of individual cell type helps improve the SSIM compared with a training library of combined cell types.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131799006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705951
Na Xi, F. Lin, Tianchun Ye
This paper presents a self-injection technique used in injection-locked QVCO (IL-QVCO) with inherently perfect injection timing. In self-injection technique, injection pulse is generated using QVCO’s own oscillation signal. Two comparators and two dividers are utilized to generate two injection pulses for each core. Post simulation results show that injection spur is optimized by 20% compared with conventional QVCO and achieves -47dBc under tt process conrner. The phase noise achieves -131.4dBc/Hz at lMHz offset at 2. 4GHz oscillating frequency. Phase noise performance of proposed IL- QVCO is optimized by 7dBc/Hz compared with conventional one. The total current consumption is 4. 8mA at the supply voltage of l. 8V. It occupies area of l. 032mm2, totally.
{"title":"A low injection spur injection-locked LC-QVCO with self-injection technique","authors":"Na Xi, F. Lin, Tianchun Ye","doi":"10.1109/CICTA.2018.8705951","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705951","url":null,"abstract":"This paper presents a self-injection technique used in injection-locked QVCO (IL-QVCO) with inherently perfect injection timing. In self-injection technique, injection pulse is generated using QVCO’s own oscillation signal. Two comparators and two dividers are utilized to generate two injection pulses for each core. Post simulation results show that injection spur is optimized by 20% compared with conventional QVCO and achieves -47dBc under tt process conrner. The phase noise achieves -131.4dBc/Hz at lMHz offset at 2. 4GHz oscillating frequency. Phase noise performance of proposed IL- QVCO is optimized by 7dBc/Hz compared with conventional one. The total current consumption is 4. 8mA at the supply voltage of l. 8V. It occupies area of l. 032mm2, totally.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128215553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706093
Kaixuan Ye, Ziyan Li, Min Tan
This paper presents a novel current quantization circuit which applies the operating principles of digital low dropout regulator (DLDO). Compared with the traditional current quantization designs, the proposed circuit can save chip area as much as 66% under the same quantization range and resolution. Implemented in 130 nm CMOS process, the prototype circuit can sense current under 1 mA with 8-bit resolution, and only occupies 0.02mm2 chip area. This design can also be expanded to wider range and higher resolution.
{"title":"An Area-Efficient Current Quantization Circuit Inspired by Digital Low-Dropout Regulators","authors":"Kaixuan Ye, Ziyan Li, Min Tan","doi":"10.1109/CICTA.2018.8706093","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706093","url":null,"abstract":"This paper presents a novel current quantization circuit which applies the operating principles of digital low dropout regulator (DLDO). Compared with the traditional current quantization designs, the proposed circuit can save chip area as much as 66% under the same quantization range and resolution. Implemented in 130 nm CMOS process, the prototype circuit can sense current under 1 mA with 8-bit resolution, and only occupies 0.02mm2 chip area. This design can also be expanded to wider range and higher resolution.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131075852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706059
F. Rivet, Yoan Veyrac, Y. Deval
The Riemann Pump is an integrated CMOS wideband Arbitrary Waveform Generator (AWG) for Carrier Aggregation. It is designed to target the sub-6 GHz 5G standard and is implemented in 65nm CMOS technology from TSMC. It is based on a piecewise linear approximation of a signal, using a dedicated algorithm. Its principle is about integrating constant current steps into a capacitive load. The ability to generate multicarrier signal is demonstrated with measurements of 5G schemes with SNDR on multi-carrier signal confirming the theory and to convert very large bandwidths from analog-to-digital. EVM measurements are detailed in a large range of frequencies up to 3GHz. The Riemann Pump consumes less than 1mW for a very reduced die area and thus, is an excellent candidate for any Radio-Frequency Transceivers architecture.
{"title":"The Riemann Pump: a Technique For Carrier-Aggregation Radio-Frequency Transceivers","authors":"F. Rivet, Yoan Veyrac, Y. Deval","doi":"10.1109/CICTA.2018.8706059","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706059","url":null,"abstract":"The Riemann Pump is an integrated CMOS wideband Arbitrary Waveform Generator (AWG) for Carrier Aggregation. It is designed to target the sub-6 GHz 5G standard and is implemented in 65nm CMOS technology from TSMC. It is based on a piecewise linear approximation of a signal, using a dedicated algorithm. Its principle is about integrating constant current steps into a capacitive load. The ability to generate multicarrier signal is demonstrated with measurements of 5G schemes with SNDR on multi-carrier signal confirming the theory and to convert very large bandwidths from analog-to-digital. EVM measurements are detailed in a large range of frequencies up to 3GHz. The Riemann Pump consumes less than 1mW for a very reduced die area and thus, is an excellent candidate for any Radio-Frequency Transceivers architecture.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130580028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Some Comprehensive Understanding of 3D-NAND Technology (Invited)","authors":"J. An","doi":"10.1109/CICTA.2018.8705954","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705954","url":null,"abstract":"this paper reviews some recent 3D NAND development based on published work related to its technology, process, devices and reliability.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133255979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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