Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705946
Dixian Zhao, Peng Gu, Yongran Yi, Chongyu Yu
Key building blocks for 5G millimeter-wave (mm-Wave) phased-array transceiver including broadband high-efficiency power amplifier (PA), amplitude-invariant phase shifter and phase-invariant variable gain amplifier (VGA) are presented. Challenges remain for the design of these circuits operating at the 5G mm-Wave band. To address these challenges, techniques are proposed such as weakly-coupled inter-stage transformer for broadband PA design, triple-resonating load technique for 360° amplitude-invariant phase shifter design and dynamic elements elimination for phase-invariant VGA design. They provide possible solutions to the design of 5G mm-Wave phased-array transceiver front-end.
{"title":"Key Circuit Building Blocks for 5G Millimeter-Wave Phased-Array Transceiver Front-End (Invited)","authors":"Dixian Zhao, Peng Gu, Yongran Yi, Chongyu Yu","doi":"10.1109/CICTA.2018.8705946","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705946","url":null,"abstract":"Key building blocks for 5G millimeter-wave (mm-Wave) phased-array transceiver including broadband high-efficiency power amplifier (PA), amplitude-invariant phase shifter and phase-invariant variable gain amplifier (VGA) are presented. Challenges remain for the design of these circuits operating at the 5G mm-Wave band. To address these challenges, techniques are proposed such as weakly-coupled inter-stage transformer for broadband PA design, triple-resonating load technique for 360° amplitude-invariant phase shifter design and dynamic elements elimination for phase-invariant VGA design. They provide possible solutions to the design of 5G mm-Wave phased-array transceiver front-end.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122262174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705960
Shengli Ma, Y. Chai, Jun Yan, Han Cai, Liu-lin Hu, Shuwei He, Wei Wang, Jing Chen, Yufeng Jin
Transmitter/Receiver (T/R) is a basic part for the RF front-end module, whose miniaturization and integration are very important for the improvement in integration density, function complexity and performance. The state of art of high performance T/R is mainly realized with heterogeneous integration based on advance ceramics such as High Temperature Co-fired Ceramic (HTCC) and Low Temperature Co-fired Ceramic (LTCC). This scheme is helpful to fully utilize the excellent performance of various devices based on substrate such as GaAs, InP, and GaN substrate, however, it confronts shortcomings in re-wiring lines of low precision, shrinkage mismatch during co-firing process, low thermal conductivity. TSV interposer having its Re-wiring line realized with IC back-end metallization process, MEMS process, etc., and using Through-Silicon-Via (TSV) to achieve vertical interconnections between rewiring lines on both surface, is able to provide a good match in rewiring line with RF microelectronic chips, factoring in improvement in RF loss properties with high-resistivity Si as substrate instead of normal low resistivity Si, therefore is acknowledged to be a competitive package substrate for building a highly integrated RF system. In this context, we present a 2.5D integrated L-band Receiver based on TSV interposer, the test results prove the feasibility of 2.5D RF integration enabled by high-resistivity Si interposer.
{"title":"A 2.5D integrated L band Receiver based on High resistivity Si interposer","authors":"Shengli Ma, Y. Chai, Jun Yan, Han Cai, Liu-lin Hu, Shuwei He, Wei Wang, Jing Chen, Yufeng Jin","doi":"10.1109/CICTA.2018.8705960","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705960","url":null,"abstract":"Transmitter/Receiver (T/R) is a basic part for the RF front-end module, whose miniaturization and integration are very important for the improvement in integration density, function complexity and performance. The state of art of high performance T/R is mainly realized with heterogeneous integration based on advance ceramics such as High Temperature Co-fired Ceramic (HTCC) and Low Temperature Co-fired Ceramic (LTCC). This scheme is helpful to fully utilize the excellent performance of various devices based on substrate such as GaAs, InP, and GaN substrate, however, it confronts shortcomings in re-wiring lines of low precision, shrinkage mismatch during co-firing process, low thermal conductivity. TSV interposer having its Re-wiring line realized with IC back-end metallization process, MEMS process, etc., and using Through-Silicon-Via (TSV) to achieve vertical interconnections between rewiring lines on both surface, is able to provide a good match in rewiring line with RF microelectronic chips, factoring in improvement in RF loss properties with high-resistivity Si as substrate instead of normal low resistivity Si, therefore is acknowledged to be a competitive package substrate for building a highly integrated RF system. In this context, we present a 2.5D integrated L-band Receiver based on TSV interposer, the test results prove the feasibility of 2.5D RF integration enabled by high-resistivity Si interposer.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706117
A. Beckers, F. Jazaeri, C. Enz
This paper presents an intensive overview of the characterization and modeling of advanced 28-nm bulk and FDSOI CMOS processes operating continuously from room down to deep cryogenic temperature.
{"title":"28-nm Bulk and FDSOI Cryogenic MOSFET : (Invited Paper)","authors":"A. Beckers, F. Jazaeri, C. Enz","doi":"10.1109/CICTA.2018.8706117","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706117","url":null,"abstract":"This paper presents an intensive overview of the characterization and modeling of advanced 28-nm bulk and FDSOI CMOS processes operating continuously from room down to deep cryogenic temperature.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131723222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706066
Nian Duan, Yi Li, X. Miao, Hsiao-Cheng Chiang, T. Chang
This work reports an artificial synapse based on the dual-gate low temperature polycrystalline silicon (LTPS) thin film transistor (TFT). Basic bilingual synaptic behaviors including excitatory postsynaptic current (EPSC) and inhibitory postsynaptic current (IPSC) have been successfully realized by simple means of electric pulse stimulation. Most importantly, the strength of the excitatory and inhibitory responses can be controlled by the electrical biases at the bottom gate, which severs as a modulatory terminal. These results indicate the mature mainstream TFT technology could find its special fundamental role in the emerging non von Neumann neuromorphic computing field.
{"title":"Low Temperature Polycrystalline Silicon Thin Film Synaptic Transistor with Bilingual Plasticity for Neuromorphic Computing","authors":"Nian Duan, Yi Li, X. Miao, Hsiao-Cheng Chiang, T. Chang","doi":"10.1109/CICTA.2018.8706066","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706066","url":null,"abstract":"This work reports an artificial synapse based on the dual-gate low temperature polycrystalline silicon (LTPS) thin film transistor (TFT). Basic bilingual synaptic behaviors including excitatory postsynaptic current (EPSC) and inhibitory postsynaptic current (IPSC) have been successfully realized by simple means of electric pulse stimulation. Most importantly, the strength of the excitatory and inhibitory responses can be controlled by the electrical biases at the bottom gate, which severs as a modulatory terminal. These results indicate the mature mainstream TFT technology could find its special fundamental role in the emerging non von Neumann neuromorphic computing field.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130738941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706109
Qiwen Liao, Nan Qi, Zhao Zhang, Liyuan Liu, Jian Liu, N. Wu, Xi Xiao, P. Chiang
In this paper, some key techniques of clock and data recovery (CDR) are proposed for PAM4 format high-speed communication, including effective voltage level transitions selection, sampling location optimization and threshold adjustment. Based on these techniques, two 50Gbps PAM4 CDR were designed and fabricated in 65nm and 40nm, respectively. The measurement results show $3.4times10^{-9}$ BER of 65nm PAM4 CDR and $8times10^{-9}$ BER of 40nm PAM4 CDR.
{"title":"The Design Techniques for High-Speed PAM4 Clock and Data Recovery","authors":"Qiwen Liao, Nan Qi, Zhao Zhang, Liyuan Liu, Jian Liu, N. Wu, Xi Xiao, P. Chiang","doi":"10.1109/CICTA.2018.8706109","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706109","url":null,"abstract":"In this paper, some key techniques of clock and data recovery (CDR) are proposed for PAM4 format high-speed communication, including effective voltage level transitions selection, sampling location optimization and threshold adjustment. Based on these techniques, two 50Gbps PAM4 CDR were designed and fabricated in 65nm and 40nm, respectively. The measurement results show $3.4times10^{-9}$ BER of 65nm PAM4 CDR and $8times10^{-9}$ BER of 40nm PAM4 CDR.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114524989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705955
H. Wong
It is expected that the next device structure evolution will be the Silicon-on-Nothing (SON) Gate-All-Around (GAA) nanowire structure. In principle, the nanowire transistor should have even better scalability than the FinFET used in the state-of-the-art CMOS technology because of its fewer parasitic components on substrate and better gate electrostatics control as gate area is extended from three sides to the whole circumference. In addition, ballistic charge transport may also be possible with the ultra-short gate length. This work reports the attempt of modeling silicon GAA nanowire transistors by considering the ballistic transport and with some effective measures for accounting the subband energy level quantization under some specific surface potential profiles approximations. Good agreements with the simulation results were obtained. In particular, for the subthreshold characteristics obtained from the model, it indicates that short-channel effects will become significant again in the nanowire transistor because of the source subband energy reduction induced by the drain bias. Considering the limit of nanowire size scaling which made length-to-radius ratio not to be larger enough and the non-ideal effects such as surface scattering and gate leakage, it seems that the benefits of replacing FinFET with nanowire GAA transistor may not be that large and there is no much more generations for further scaling.
{"title":"Compact Modeling and Short-Channel Effects of Nanowire MOS Transistors (Invited)","authors":"H. Wong","doi":"10.1109/CICTA.2018.8705955","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705955","url":null,"abstract":"It is expected that the next device structure evolution will be the Silicon-on-Nothing (SON) Gate-All-Around (GAA) nanowire structure. In principle, the nanowire transistor should have even better scalability than the FinFET used in the state-of-the-art CMOS technology because of its fewer parasitic components on substrate and better gate electrostatics control as gate area is extended from three sides to the whole circumference. In addition, ballistic charge transport may also be possible with the ultra-short gate length. This work reports the attempt of modeling silicon GAA nanowire transistors by considering the ballistic transport and with some effective measures for accounting the subband energy level quantization under some specific surface potential profiles approximations. Good agreements with the simulation results were obtained. In particular, for the subthreshold characteristics obtained from the model, it indicates that short-channel effects will become significant again in the nanowire transistor because of the source subband energy reduction induced by the drain bias. Considering the limit of nanowire size scaling which made length-to-radius ratio not to be larger enough and the non-ideal effects such as surface scattering and gate leakage, it seems that the benefits of replacing FinFET with nanowire GAA transistor may not be that large and there is no much more generations for further scaling.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116933005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705956
Weipeng He, Zhiqun Li, Yan Yao, Yongbin Xue, Lei Luo, Guoxiao Cheng
A Wideband low-noise amplifier (LNA) designed and implemented in 0.13 μm SiGe BiCMOS technology is presented in this paper. The inductive peaking technology is adopted to expand the bandwidth, the resistance negative feedback technology and the emitter degeneration inductive technology are adopted to improve the flatness of gain and input matching. This LNA achieves a flat gain of 10.7∼ 12.9 dB in the frequency range of $5sim 14$ GHz. The noise figure $(NF)$ of the LNA is 3.5∼ 6.1 dB across the band. The input return losses (S11) of the LNA are better than -10 dB. The LNA dissipates 9.4mA with a 3.3 V supply.
{"title":"A 5 ∼14GHz Wideband LNA using 0.13μm SiGe BiCMOS Technology","authors":"Weipeng He, Zhiqun Li, Yan Yao, Yongbin Xue, Lei Luo, Guoxiao Cheng","doi":"10.1109/CICTA.2018.8705956","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705956","url":null,"abstract":"A Wideband low-noise amplifier (LNA) designed and implemented in 0.13 μm SiGe BiCMOS technology is presented in this paper. The inductive peaking technology is adopted to expand the bandwidth, the resistance negative feedback technology and the emitter degeneration inductive technology are adopted to improve the flatness of gain and input matching. This LNA achieves a flat gain of 10.7∼ 12.9 dB in the frequency range of $5sim 14$ GHz. The noise figure $(NF)$ of the LNA is 3.5∼ 6.1 dB across the band. The input return losses (S11) of the LNA are better than -10 dB. The LNA dissipates 9.4mA with a 3.3 V supply.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128987142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705709
Xiaofei Liao, Dixian Zhao
This paper presents the design of single-ended and push-push frequency doublers at 140 GHz. Both designs use two open quarter-wavelength fundamental frequency transmission lines at output port to provide high fundamental suppression. Compared to single-ended topology, the push-push one achieves higher fundamental suppression. The single-ended and push-push doublers show simulated fundamental suppression of 31.61 dB and 91.19 dB respectively with output power of -3.02dBm and -2.03dBm at 5dBm input power. The doublers are implemented in 100-nm GaAs technology.
{"title":"Design of 140-GHz Frequency Single-Ended and Push-Push Doublers with 31.61dB and 91.19dB Fundamental Suppression","authors":"Xiaofei Liao, Dixian Zhao","doi":"10.1109/CICTA.2018.8705709","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705709","url":null,"abstract":"This paper presents the design of single-ended and push-push frequency doublers at 140 GHz. Both designs use two open quarter-wavelength fundamental frequency transmission lines at output port to provide high fundamental suppression. Compared to single-ended topology, the push-push one achieves higher fundamental suppression. The single-ended and push-push doublers show simulated fundamental suppression of 31.61 dB and 91.19 dB respectively with output power of -3.02dBm and -2.03dBm at 5dBm input power. The doublers are implemented in 100-nm GaAs technology.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130949999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706068
Xin Ding, Jianhui Wu, Chao Chen
An agile automatic frequency calibration (AFC) technique is developed in phase locked loop (PLL) for the bluetooth low energy (BLE) applications. Instead of searching for an optimal tuning curve for 40 target frequencies in BLE, the tuning curve feature extraction (TCFE) technique is adopted to reduce necessary calibration times. Moreover, the initial value of each target frequency is adjusted dynamically according to previous result to accelerate calibration speed. The calibration is conducted foreground, then the optimal tuning curve is selected directly and the output frequency of PLL hops quickly in operation. The whole PLL was designed and fabricated in 0.18 μm CMOS technology. Measurement results show that the time for foreground calibration is about 80 μs and the frequency hops without the switch of tuning curves.
{"title":"An Agile Automatic Frequency Calibration Technique for PLL","authors":"Xin Ding, Jianhui Wu, Chao Chen","doi":"10.1109/CICTA.2018.8706068","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706068","url":null,"abstract":"An agile automatic frequency calibration (AFC) technique is developed in phase locked loop (PLL) for the bluetooth low energy (BLE) applications. Instead of searching for an optimal tuning curve for 40 target frequencies in BLE, the tuning curve feature extraction (TCFE) technique is adopted to reduce necessary calibration times. Moreover, the initial value of each target frequency is adjusted dynamically according to previous result to accelerate calibration speed. The calibration is conducted foreground, then the optimal tuning curve is selected directly and the output frequency of PLL hops quickly in operation. The whole PLL was designed and fabricated in 0.18 μm CMOS technology. Measurement results show that the time for foreground calibration is about 80 μs and the frequency hops without the switch of tuning curves.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114201917","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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