Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705949
Shuo Chen, Yu Li, M. H. Memon, F. Lin
Narrow Band Internet of Things (NB-IoT) is built on cellular network. It has the advantages of low power consumption, low cost, super coverage and large connection. Cell search is an essential component of NB-IoT and its main purpose is to obtain the Physical-layer Cell Identity. Since the cells of NB-IoT are not grouped, NB-IoT cell search is more complex than LTE systems. In this paper, we propose an effective method to reduce the complexity of NB-IoT cell search. Simulation results show that the detection accuracy reaches 80% with 10 radio frames, with a signal-to-noise ratio of -12.6dB.
{"title":"Design and Implementation of Cell Search in NB-IoT Downlink Receiver","authors":"Shuo Chen, Yu Li, M. H. Memon, F. Lin","doi":"10.1109/CICTA.2018.8705949","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705949","url":null,"abstract":"Narrow Band Internet of Things (NB-IoT) is built on cellular network. It has the advantages of low power consumption, low cost, super coverage and large connection. Cell search is an essential component of NB-IoT and its main purpose is to obtain the Physical-layer Cell Identity. Since the cells of NB-IoT are not grouped, NB-IoT cell search is more complex than LTE systems. In this paper, we propose an effective method to reduce the complexity of NB-IoT cell search. Simulation results show that the detection accuracy reaches 80% with 10 radio frames, with a signal-to-noise ratio of -12.6dB.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"3 19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134066332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706047
Zhao Zhang, C. Yue
This paper presents a low-power low-jitter full-rate linear phase detector based clock and data recovery circuit (CDR). The proposed sample-and-hold linear phase detector (SHLPD) can reduce the complexity of the conventional SHLPD to save power consumption. This CDR is designed and implemented in 40-nm CMOS process with 0.9-V supply. The simulation results show that it can operate at data rate of 12.5 Gb/s with the power consumption of 4.8 mW. The simulated peak-to-peak jitter of the recovered data and clock is 4.96 ps and 4.64 ps, respectively, with 12.5-Gb/s input data rate.
{"title":"A 12.5-Gb/s 4.8-mW Full-Rate CDR with Low-Power Sample-and-Hold Linear Phase Detector","authors":"Zhao Zhang, C. Yue","doi":"10.1109/CICTA.2018.8706047","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706047","url":null,"abstract":"This paper presents a low-power low-jitter full-rate linear phase detector based clock and data recovery circuit (CDR). The proposed sample-and-hold linear phase detector (SHLPD) can reduce the complexity of the conventional SHLPD to save power consumption. This CDR is designed and implemented in 40-nm CMOS process with 0.9-V supply. The simulation results show that it can operate at data rate of 12.5 Gb/s with the power consumption of 4.8 mW. The simulated peak-to-peak jitter of the recovered data and clock is 4.96 ps and 4.64 ps, respectively, with 12.5-Gb/s input data rate.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132480719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705715
Wenjing Yang, Yuan Li, Bo Wang, H. Qian, Jiezhi Chen
Aiming at providing insight into the reliabilities of three-dimensional NAND flash memories with poly-Si channel, this work experimentally studied the positive bias temperature instability (PBTI) in vertical gate-all-around (GAA) poly-Si nanowire field-effect transistors (FETs). On the one side, the carrier-transport properties in the poly-Si nanowire are studied in a wide temperature range. On the other side, threshold voltage shifts, subthreshold slope, and transconductance under positive bias stress are measured, showing that the interface degradation takes place in a time scale much shorter than that of the Vth shift. These findings can be rationalized by the presence of serious trap charging in the gate dielectrics.
{"title":"Positive Bias Temperature Instabilities in Vertical Gate-all-around poly-Si Nanowire Field-effect Transistors","authors":"Wenjing Yang, Yuan Li, Bo Wang, H. Qian, Jiezhi Chen","doi":"10.1109/CICTA.2018.8705715","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705715","url":null,"abstract":"Aiming at providing insight into the reliabilities of three-dimensional NAND flash memories with poly-Si channel, this work experimentally studied the positive bias temperature instability (PBTI) in vertical gate-all-around (GAA) poly-Si nanowire field-effect transistors (FETs). On the one side, the carrier-transport properties in the poly-Si nanowire are studied in a wide temperature range. On the other side, threshold voltage shifts, subthreshold slope, and transconductance under positive bias stress are measured, showing that the interface degradation takes place in a time scale much shorter than that of the Vth shift. These findings can be rationalized by the presence of serious trap charging in the gate dielectrics.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133092113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705713
Chun Zhang, F. Jazaeri, G. Borghello, S. Mattiazzo, Andrea Baschirotto, Christian Enz
Using the Y-function method, this paper experimentally investigates the effects of total ionizing dose up to 1 Grad on the channel mobility of a commercial 28-nm bulk CMOS process.
利用y函数方法，实验研究了总电离剂量高达1 Grad对28纳米CMOS工艺通道迁移率的影响。
{"title":"Mobility Degradation of 28-nm Bulk MOSFETs Irradiated to Ultrahigh Total Ionizing Doses","authors":"Chun Zhang, F. Jazaeri, G. Borghello, S. Mattiazzo, Andrea Baschirotto, Christian Enz","doi":"10.1109/CICTA.2018.8705713","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705713","url":null,"abstract":"Using the Y-function method, this paper experimentally investigates the effects of total ionizing dose up to 1 Grad on the channel mobility of a commercial 28-nm bulk CMOS process.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133625281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705723
Hongchang Qiao, Chenchang Zhan, Jun Yi, Lidan Wang
This paper presents a low power subthreshold CMOS voltage reference (CVR) with current loading capability. Based on the classical 2T CVR to achieve low temperature coefficient (TC), a sourcing PMOS is appropriately biased through a local negative feedback loop. Current loading capability is achieved without relying on an output buffer. The proposed CVR is designed in a standard 0.18-μm CMOS process. Simulation results show that the CVR is capable of delivering 300 μA while the generated Vref has less than 0.42% reduction. The minimum supply voltage is 0.5 V and typical power consumption is 3 nW. It achieves an average TC of 9 ppm/°C from -20 °C to 135 °C, line sensitivity of 0.069 %/v and power supply rejection of -65 dB@100Hz.
{"title":"A Low-Power CMOS Voltage Reference with Current Loading Capability","authors":"Hongchang Qiao, Chenchang Zhan, Jun Yi, Lidan Wang","doi":"10.1109/CICTA.2018.8705723","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705723","url":null,"abstract":"This paper presents a low power subthreshold CMOS voltage reference (CVR) with current loading capability. Based on the classical 2T CVR to achieve low temperature coefficient (TC), a sourcing PMOS is appropriately biased through a local negative feedback loop. Current loading capability is achieved without relying on an output buffer. The proposed CVR is designed in a standard 0.18-μm CMOS process. Simulation results show that the CVR is capable of delivering 300 μA while the generated Vref has less than 0.42% reduction. The minimum supply voltage is 0.5 V and typical power consumption is 3 nW. It achieves an average TC of 9 ppm/°C from -20 °C to 135 °C, line sensitivity of 0.069 %/v and power supply rejection of -65 dB@100Hz.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122374695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706119
Songyuan Yang, Weihua Yu, Xinxin Yang, X. Lv, H. Zirath, Z. He
A double-band terahertz slot transition from the substrate integrated waveguide (SIW) to the rectangular waveguide (RWG) is presented. With better than 10 dB return loss (RL) and 1.3 dB insertion loss (IL) demonstrated by full-EM simulation, the frequency bands of a designed sample are from 164.6 GHz to 182.76 GHz and from 238 GHz to 257.9 GHz. The presented transition is suitable for multilayer MMIC process, especially for the substrate with high loss and high dielectric constant.
{"title":"A Terahertz-wave Double-Band Transition from Substrate Integrated Waveguide to Rectangular Waveguide for InP MMIC","authors":"Songyuan Yang, Weihua Yu, Xinxin Yang, X. Lv, H. Zirath, Z. He","doi":"10.1109/CICTA.2018.8706119","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706119","url":null,"abstract":"A double-band terahertz slot transition from the substrate integrated waveguide (SIW) to the rectangular waveguide (RWG) is presented. With better than 10 dB return loss (RL) and 1.3 dB insertion loss (IL) demonstrated by full-EM simulation, the frequency bands of a designed sample are from 164.6 GHz to 182.76 GHz and from 238 GHz to 257.9 GHz. The presented transition is suitable for multilayer MMIC process, especially for the substrate with high loss and high dielectric constant.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127304619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705721
S. Heinen, F. Henkel
Over the last 25 years RF integrated circuits have evolved from bipolar ICs integrating a handful of transistors into highly complex RF CMOS SoCs with millions of transistors. The high volume of mobile and short-range communication terminals has been the major driving force behind the evolution. RF BiCMOS and RF CMOS have opened the stage for creativity in the implementation of RF architectures. Homodyne, Low-IF and Sliding-IF are some of the mayor milestones on the receive side. For the transmit side digital RF techniques e.g., ADPLLs and RF-DACs have matured over the last few years. The evolution of the technical capabilities described combined with market demands of high volume of mobile and short-range communication terminals are driving the complexity RF SoCs in academia and industry. The complexity of RF ICs in academia a probably an order of magnitude low than in industry, whereas the experience of experienced industrial R&D compensates this compared to student IC designers. Thus, pre-tapeout verification is a mayor challenge for both groups in order to achieve a “fully functional first-time right design” of RF SoCs.
{"title":"RFIC Complexity a Challenge for Academia and Industry","authors":"S. Heinen, F. Henkel","doi":"10.1109/CICTA.2018.8705721","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705721","url":null,"abstract":"Over the last 25 years RF integrated circuits have evolved from bipolar ICs integrating a handful of transistors into highly complex RF CMOS SoCs with millions of transistors. The high volume of mobile and short-range communication terminals has been the major driving force behind the evolution. RF BiCMOS and RF CMOS have opened the stage for creativity in the implementation of RF architectures. Homodyne, Low-IF and Sliding-IF are some of the mayor milestones on the receive side. For the transmit side digital RF techniques e.g., ADPLLs and RF-DACs have matured over the last few years. The evolution of the technical capabilities described combined with market demands of high volume of mobile and short-range communication terminals are driving the complexity RF SoCs in academia and industry. The complexity of RF ICs in academia a probably an order of magnitude low than in industry, whereas the experience of experienced industrial R&D compensates this compared to student IC designers. Thus, pre-tapeout verification is a mayor challenge for both groups in order to achieve a “fully functional first-time right design” of RF SoCs.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116804101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706062
Zishang He, Yizhou Jiang, Ikwan Kim, Han Jin, Chenjie Dong, Junshang Li, Z. Zou, Lirong Zheng, Yajie Qin
A wireless-powered implantable sensor tag for neural recording and brain stimulation (NRS) based on standard Near Field Communication (NFC) protocol is presented. A NRS system is thus established with this dedicated but flexible sensor tag and a Proximity Coupling Device (PCD), which can be replaced with an NFC smart phone. The flexible printed sensor tag consists of a customized NRS System on Chip (SoC) and a customized NFC Proximity Card (PICC) SoC. Neural signals are captured by the sensor tag and transmitted to the PCD wirelessly. The measured signal-to-noise-and-distortion-rate (SNDR) was 35 dB in vitro.
{"title":"A Wireless Powered Implantable and Flexible Neural Recording and Stimulating System Based on NFC Protocol","authors":"Zishang He, Yizhou Jiang, Ikwan Kim, Han Jin, Chenjie Dong, Junshang Li, Z. Zou, Lirong Zheng, Yajie Qin","doi":"10.1109/CICTA.2018.8706062","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706062","url":null,"abstract":"A wireless-powered implantable sensor tag for neural recording and brain stimulation (NRS) based on standard Near Field Communication (NFC) protocol is presented. A NRS system is thus established with this dedicated but flexible sensor tag and a Proximity Coupling Device (PCD), which can be replaced with an NFC smart phone. The flexible printed sensor tag consists of a customized NRS System on Chip (SoC) and a customized NFC Proximity Card (PICC) SoC. Neural signals are captured by the sensor tag and transmitted to the PCD wirelessly. The measured signal-to-noise-and-distortion-rate (SNDR) was 35 dB in vitro.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116725364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706102
Shiquan Fan, Jun Dong, Rui Zhang, Yang Zhao, Li Geng
In this paper, an on-chip low-power current sensor with auto-accuracy adjustment is proposed for current monitor applications, which is composed by a sensing element and a quantizer. The sensing element is designed as a current mirror with auto-adjustable current ratio of K determined by the value of sensing current. When the current is larger than a threshold value, K changes from 1000 to 2000 to reduce the power consumption. The quantizer includes a comparator, two current-source arrays and two successive approximation register (SAR) logic circuits. The main 8-bit SAR logic is adopted to control a current-source array to realize current quantized range, the auxiliary 4-bit SAR logic is employed to control another current.
{"title":"A Low-Power 0.8% Sensing Error On-Chip Current Sensor with Auto-Accuracy Adjustment","authors":"Shiquan Fan, Jun Dong, Rui Zhang, Yang Zhao, Li Geng","doi":"10.1109/CICTA.2018.8706102","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706102","url":null,"abstract":"In this paper, an on-chip low-power current sensor with auto-accuracy adjustment is proposed for current monitor applications, which is composed by a sensing element and a quantizer. The sensing element is designed as a current mirror with auto-adjustable current ratio of K determined by the value of sensing current. When the current is larger than a threshold value, K changes from 1000 to 2000 to reduce the power consumption. The quantizer includes a comparator, two current-source arrays and two successive approximation register (SAR) logic circuits. The main 8-bit SAR logic is adopted to control a current-source array to realize current quantized range, the auxiliary 4-bit SAR logic is employed to control another current.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125562271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the post-Moore era, integrated circuits based on complementary metal oxide semiconductor (CMOS) are faced with the energy bottleneck. Spintronics is recognized as one of the most promising technologies for overcoming this issue. Here we focus on two emerging spintronic devices, double-barrier double-free-layer magnetic tunnel junction (DDMTJ) and ring-shaped racetrack memory (RM), which can be used for building ultra-high-density non-volatile memories and logic-in-memory circuits. A systematic study has been carried out from device level to system level. Through increasing density and reducing data traffic distance, the performance and energy of the memory and logic applications can be improved significantly.
{"title":"Emerging Spintronic Devices: From Ultra-High-Density Memory to Logic-In-Memory","authors":"Yue Zhang, Guanda Wang, Zhe Huang, Zhizhong Zhang, Jinkai Wang, Youguang Zhang, Weisheng Zhao","doi":"10.1109/CICTA.2018.8706056","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706056","url":null,"abstract":"In the post-Moore era, integrated circuits based on complementary metal oxide semiconductor (CMOS) are faced with the energy bottleneck. Spintronics is recognized as one of the most promising technologies for overcoming this issue. Here we focus on two emerging spintronic devices, double-barrier double-free-layer magnetic tunnel junction (DDMTJ) and ring-shaped racetrack memory (RM), which can be used for building ultra-high-density non-volatile memories and logic-in-memory circuits. A systematic study has been carried out from device level to system level. Through increasing density and reducing data traffic distance, the performance and energy of the memory and logic applications can be improved significantly.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132476997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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