Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706103
Fanyang Li, Xiaoquan Liu, Jiwei Huang, Tao Yang
A 1.2V rail to rail output driving amplifier used to drive the hearing aid loudspeaker is proposed in this paper. Since the linearity of the cascoded amplifier degrades with the supply voltage decreasing, a three-stage cascaded amplifier is adopted. For the rail to rail output signal with high linearity, a special folded class-AB output stage current control circuit is incorporated in the amplifier. The minimum supply voltage can be reduced to VGS+2|Vdsat|. Fabricated with a 0.18 $mu mathrm{m}$ CMOS process, the amplifier with the loading resistance 100ohm achieves -85dB THD while operating from a 1.2V supply and using a 1kHz input sine wave.
{"title":"A 1.2V rail to rail output driving amplifier with a folded Class-AB output stage control circuit","authors":"Fanyang Li, Xiaoquan Liu, Jiwei Huang, Tao Yang","doi":"10.1109/CICTA.2018.8706103","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706103","url":null,"abstract":"A 1.2V rail to rail output driving amplifier used to drive the hearing aid loudspeaker is proposed in this paper. Since the linearity of the cascoded amplifier degrades with the supply voltage decreasing, a three-stage cascaded amplifier is adopted. For the rail to rail output signal with high linearity, a special folded class-AB output stage current control circuit is incorporated in the amplifier. The minimum supply voltage can be reduced to VGS+2|Vdsat|. Fabricated with a 0.18 $mu mathrm{m}$ CMOS process, the amplifier with the loading resistance 100ohm achieves -85dB THD while operating from a 1.2V supply and using a 1kHz input sine wave.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116152397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706049
Cheng Chen, Daquan Yu, L. Wan
A novel embedded silicon fan-out wafer level packaging (eSiFO), which was proposed by Huatian Technology in 2015 and now in production, has a relatively simple manufacturing process eliminating molding and de-bonding process compared to typical fan-out process. This paper briefly introduces eSiFO technology at first, and then mainly studies its electrical and thermal performance, as well as RDL reliability. This study finds that eSiFO technology has a good package performance, and can further provide optimal performance for mobile electronics and potential IoT and 5G applications.
{"title":"Electrical, Thermal and Mechanical Simulation for Embedded Silicon Fan-out Wafer Level Packaging","authors":"Cheng Chen, Daquan Yu, L. Wan","doi":"10.1109/CICTA.2018.8706049","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706049","url":null,"abstract":"A novel embedded silicon fan-out wafer level packaging (eSiFO), which was proposed by Huatian Technology in 2015 and now in production, has a relatively simple manufacturing process eliminating molding and de-bonding process compared to typical fan-out process. This paper briefly introduces eSiFO technology at first, and then mainly studies its electrical and thermal performance, as well as RDL reliability. This study finds that eSiFO technology has a good package performance, and can further provide optimal performance for mobile electronics and potential IoT and 5G applications.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115354955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706042
Xiaojian Hong, Longzhao Shi, Qingkun Chen, Danyu Yan
High-efficiency video coding, as a new generation of multimedia video standard, has doubled the compression ratio and increased the computational complexity by 2–3 times of the same image quality in the previous H.264 video standard. The interpolation filter is one of the most complicated parts of motion estimation. However, meeting the requirements of real-time performance is difficult to realize by using a software. Thus, we propose in this paper an architecture for the interpolation filter that is easy to implement by using a hardware, and this newly designed architecture has high utilization of hardware resources. The design uses QUARTUS II integrated on Altera’s Stratix V series chips. The findings show that the utilization of hardware resources in this study is less than those reported in the existing literature. The maximum operating frequency of the hardware architecture proposed in this paper can reach 420.71 MHz, which supports real-time processing of 4K videos.
{"title":"Hardware implementation for the interpolation filter in HEVC standard","authors":"Xiaojian Hong, Longzhao Shi, Qingkun Chen, Danyu Yan","doi":"10.1109/CICTA.2018.8706042","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706042","url":null,"abstract":"High-efficiency video coding, as a new generation of multimedia video standard, has doubled the compression ratio and increased the computational complexity by 2–3 times of the same image quality in the previous H.264 video standard. The interpolation filter is one of the most complicated parts of motion estimation. However, meeting the requirements of real-time performance is difficult to realize by using a software. Thus, we propose in this paper an architecture for the interpolation filter that is easy to implement by using a hardware, and this newly designed architecture has high utilization of hardware resources. The design uses QUARTUS II integrated on Altera’s Stratix V series chips. The findings show that the utilization of hardware resources in this study is less than those reported in the existing literature. The maximum operating frequency of the hardware architecture proposed in this paper can reach 420.71 MHz, which supports real-time processing of 4K videos.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122764368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706051
Jiahao Liu, Ye Liu, Xinchun Liu, Jun Zhou
this paper proposes a reconfigurable processor for matrix inversion (MI). Two techniques have been proposed for the MI processor: the proposed reconfigurable architecture allows the processor to support different matrix size. The proposed data scaling technique solves the intermediate date size issue, and therefore supports computation of large matrices. For demonstration, the proposed reconfigurable MI processor has been implemented on FPGA. It is able to compute MI for different matrix size with small mean error and short computation time.
{"title":"A Reconfigurable Processor for Matrix Inversion Computation","authors":"Jiahao Liu, Ye Liu, Xinchun Liu, Jun Zhou","doi":"10.1109/CICTA.2018.8706051","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706051","url":null,"abstract":"this paper proposes a reconfigurable processor for matrix inversion (MI). Two techniques have been proposed for the MI processor: the proposed reconfigurable architecture allows the processor to support different matrix size. The proposed data scaling technique solves the intermediate date size issue, and therefore supports computation of large matrices. For demonstration, the proposed reconfigurable MI processor has been implemented on FPGA. It is able to compute MI for different matrix size with small mean error and short computation time.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125330352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706101
Zuxiong Tan, W. Guo, Guoliang Gong, Huaxiang Lu
The linear shift feedback register (LFSR) are widely used in pseudo random number generator (PRNG). Through parallelization, the generation rate can achieve unprecedented speeds. Based on the leap-ahead LFSR architecture, this paper proposed a new parallel architecture which can improve the randomness significantly without changing the output bit-width. Compared with two latest high-quality PRNGs, the proposed architecture in this paper has advantages in randomness, resource utilization and output bandwidth. Especially, the proposed architecture reduces the occupancy of resources up to 62% and lower the area-time up to 53% compared to the recent architecture.
{"title":"A New Pseudo-Random Number Generator Based On The Leap-Ahead LFSR Architecture","authors":"Zuxiong Tan, W. Guo, Guoliang Gong, Huaxiang Lu","doi":"10.1109/CICTA.2018.8706101","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706101","url":null,"abstract":"The linear shift feedback register (LFSR) are widely used in pseudo random number generator (PRNG). Through parallelization, the generation rate can achieve unprecedented speeds. Based on the leap-ahead LFSR architecture, this paper proposed a new parallel architecture which can improve the randomness significantly without changing the output bit-width. Compared with two latest high-quality PRNGs, the proposed architecture in this paper has advantages in randomness, resource utilization and output bandwidth. Especially, the proposed architecture reduces the occupancy of resources up to 62% and lower the area-time up to 53% compared to the recent architecture.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128391091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705722
Changli Ge, M. Tang, Junfa Mao
A novel approach for modeling through-silicon-via (TSV) structure with equivalent thermal conductivity is proposed in this paper. The basic principle of this method is to replace the original copper via surrounded with silicon-dioxide material by a square column with equivalent thermal conductivity. Based on the curve fitting technique, the empirical formulas for the anisotropic equivalent thermal conductivity are obtained. With the proposed model, the computational resources can be reduced significantly for simulating complicated 3-D structures with arbitrary distributed TSVs. The validity and efficiency of the proposed method are illustrated by the numerical examples.
{"title":"Equivalent Thermal Conductivity Modeling of Through-Silicon Via (TSV) Structures","authors":"Changli Ge, M. Tang, Junfa Mao","doi":"10.1109/CICTA.2018.8705722","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705722","url":null,"abstract":"A novel approach for modeling through-silicon-via (TSV) structure with equivalent thermal conductivity is proposed in this paper. The basic principle of this method is to replace the original copper via surrounded with silicon-dioxide material by a square column with equivalent thermal conductivity. Based on the curve fitting technique, the empirical formulas for the anisotropic equivalent thermal conductivity are obtained. With the proposed model, the computational resources can be reduced significantly for simulating complicated 3-D structures with arbitrary distributed TSVs. The validity and efficiency of the proposed method are illustrated by the numerical examples.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123771119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706069
Rui Wang, Nan Qi, Liyuan Liu, Jian Liu, N. Wu
In this paper, the physical process of laser transmitting is modelled and analyzed, and this model is very helpful to analyze the requirements of different pixel structures on the frequency of laser emitter. In order to design the active quench circuit better, an accurate SPAD model is built with the Verilog-A description language. Then the circuit is presented and designed in 0.13um SiGe BiCMOS technology.
{"title":"Models of laser transmission of ToF and SPAD for the quench circuit design of LiDAR","authors":"Rui Wang, Nan Qi, Liyuan Liu, Jian Liu, N. Wu","doi":"10.1109/CICTA.2018.8706069","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706069","url":null,"abstract":"In this paper, the physical process of laser transmitting is modelled and analyzed, and this model is very helpful to analyze the requirements of different pixel structures on the frequency of laser emitter. In order to design the active quench circuit better, an accurate SPAD model is built with the Verilog-A description language. Then the circuit is presented and designed in 0.13um SiGe BiCMOS technology.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122618626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/cicta.2018.8706050
{"title":"[Title page]","authors":"","doi":"10.1109/cicta.2018.8706050","DOIUrl":"https://doi.org/10.1109/cicta.2018.8706050","url":null,"abstract":"","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134267320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706075
Minjie Ye, Yulong Zhang, Cinan Wu, Junfeng Cheng, Zewen Liu
A novel dual-band inverted-F antenna (IFA) with tunable inductor and capacitor (TIC) for 5G mobile communication is proposed. The tuning ranges of two tunable capacitors (C1 and C2) and one tunable inductor (L) are 0.1-1.0 pF, 1.3-4.8 pF, and 2-6 nH respectively. Simulation results of the dual-band IFA with TIC are obtained by using HFSS. It shows that two frequency ranges of the dual-band IFA with TIC are 2.74-3.74 GHz and 4.44-5.0 GHz at the return loss better than -15 dB. The frequency of the dual-band IFA with TIC can fully cover the 5G spectrum in China.
{"title":"Dual-band Inverted-F Antenna with Tunable Inductor and Capacitor for 5G Mobile Communication","authors":"Minjie Ye, Yulong Zhang, Cinan Wu, Junfeng Cheng, Zewen Liu","doi":"10.1109/CICTA.2018.8706075","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706075","url":null,"abstract":"A novel dual-band inverted-F antenna (IFA) with tunable inductor and capacitor (TIC) for 5G mobile communication is proposed. The tuning ranges of two tunable capacitors (C1 and C2) and one tunable inductor (L) are 0.1-1.0 pF, 1.3-4.8 pF, and 2-6 nH respectively. Simulation results of the dual-band IFA with TIC are obtained by using HFSS. It shows that two frequency ranges of the dual-band IFA with TIC are 2.74-3.74 GHz and 4.44-5.0 GHz at the return loss better than -15 dB. The frequency of the dual-band IFA with TIC can fully cover the 5G spectrum in China.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134268012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705718
Z. Wu, Xu Liu, Milin Zhang, Wensi Wang
An exponential current generation circuit for neural stimulators is presented. Compared to the conventional exponential current generation circuits, the proposed circuit features higher bandwidth and a smaller error of 2.34%. The output of the proposed exponential current generation circuit ranges from 1.16 to 75.36 $mu A$. This circuit is designed in a 180-nm CMOS technology under 1.8-V supply voltage.
{"title":"An Exponential Current Generation Circuit Using the Taylor Series Approximation for Neural Stimulators","authors":"Z. Wu, Xu Liu, Milin Zhang, Wensi Wang","doi":"10.1109/CICTA.2018.8705718","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705718","url":null,"abstract":"An exponential current generation circuit for neural stimulators is presented. Compared to the conventional exponential current generation circuits, the proposed circuit features higher bandwidth and a smaller error of 2.34%. The output of the proposed exponential current generation circuit ranges from 1.16 to 75.36 $mu A$. This circuit is designed in a 180-nm CMOS technology under 1.8-V supply voltage.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133137707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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