Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706092
Liu Wang, Jun Liu, Wenyong Zhou
In this letter, we proposed the small-signal models of AlGaN/GaN fin-shaped field-effect transistors (FinFETs) and AlGaN/GaN high electron mobility transistors (HEMTs). The parasitic parameters of device been extracted from small signal model, respectively. The comparisons of parasitic parameters and S-parameters between planer and 3D GaN device also are shown in this work.
{"title":"The Small-Signal Model Comparison and Analysis between AlGaN/GaN FinFETs and HEMTs on the Same Wafer","authors":"Liu Wang, Jun Liu, Wenyong Zhou","doi":"10.1109/CICTA.2018.8706092","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706092","url":null,"abstract":"In this letter, we proposed the small-signal models of AlGaN/GaN fin-shaped field-effect transistors (FinFETs) and AlGaN/GaN high electron mobility transistors (HEMTs). The parasitic parameters of device been extracted from small signal model, respectively. The comparisons of parasitic parameters and S-parameters between planer and 3D GaN device also are shown in this work.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122391634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705720
Zhen Li, G. Cao, Haiou Li, M. Xiao, G. Guo
The gate-defined semiconductor quantum dot system, which can be manipulated electrically and fabricated using modern microelectronic technology, is considered as an ideal platform for quantum computation. The efficiency of quantum computation depends on the speed of gate operation. And charge qubit has quick operational speed and strong inter-qubit strength but with technical challenges. In this talk, I will introduce our experiments on ultrafast quantum control in semiconductor charge qubits including ultrafast universal quantum control of single charge qubit using LZS(Landau-Zener-Stückelberg) interference, conditional rotation of two strongly coupled qubits and static Toffoli gate of three qubits. Furthermore, to find a balance between coherence and operation speed we experimentally demonstrated tunable hybrid qubit in GaAs quantum dots system. Finally, we also focuse on cryogenic electronics for quantum computing, we have measured and modeled standard process CMOS at 77K, 4.2K and 300mK. CryoCMOS can be applied to the readout and control system of quantum chips in the future.
门定义半导体量子点系统是一种理想的量子计算平台，它可以被电操纵并使用现代微电子技术制造。量子计算的效率取决于门运算的速度。电荷量子位具有运算速度快、量子位间强度强的特点，但在技术上存在一定的挑战。在这次演讲中，我将介绍我们在半导体电荷量子位中的超快量子控制实验，包括利用LZS(landau - zener - st ckelberg)干涉、两个强耦合量子位的条件旋转和三个量子位的静态Toffoli门对单电荷量子位的超快通用量子控制。此外，为了在相干性和运算速度之间找到平衡，我们在GaAs量子点系统中实验展示了可调谐混合量子比特。最后，我们也专注于量子计算的低温电子，我们测量和模拟了77K, 4.2K和300mK的标准工艺CMOS。CryoCMOS可以应用于量子芯片的读出和控制系统中。
{"title":"Fast Quantum Control of Semiconductor Qubit","authors":"Zhen Li, G. Cao, Haiou Li, M. Xiao, G. Guo","doi":"10.1109/CICTA.2018.8705720","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705720","url":null,"abstract":"The gate-defined semiconductor quantum dot system, which can be manipulated electrically and fabricated using modern microelectronic technology, is considered as an ideal platform for quantum computation. The efficiency of quantum computation depends on the speed of gate operation. And charge qubit has quick operational speed and strong inter-qubit strength but with technical challenges. In this talk, I will introduce our experiments on ultrafast quantum control in semiconductor charge qubits including ultrafast universal quantum control of single charge qubit using LZS(Landau-Zener-Stückelberg) interference, conditional rotation of two strongly coupled qubits and static Toffoli gate of three qubits. Furthermore, to find a balance between coherence and operation speed we experimentally demonstrated tunable hybrid qubit in GaAs quantum dots system. Finally, we also focuse on cryogenic electronics for quantum computing, we have measured and modeled standard process CMOS at 77K, 4.2K and 300mK. CryoCMOS can be applied to the readout and control system of quantum chips in the future.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129205506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706129
Yongxin Xu, N. Yan, Lei Ma, Hao Min
An improved Vernier time-to-digital converter (TDC) with overflow bits is designed for low power applications. The overflow bits are added to the Vernier-TDC to reduce the stages of the TDC, thus saving power. A digital-to-time convertor is employed to realize the fractional division and reduce the stages of TDC. Fabricated in 55-nm CMOS, TDC together with DTC consumes only 360 μW when operating at 24 MHz. With the help of the TDC, the ADPLL achieves 1.69-psrms jitter with a 24-MHz reference clock and a 1.8GHz output RF clock.
{"title":"A 360μW Vernier Time-to-Digital Converter for ADPLL in IoT Applications","authors":"Yongxin Xu, N. Yan, Lei Ma, Hao Min","doi":"10.1109/CICTA.2018.8706129","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706129","url":null,"abstract":"An improved Vernier time-to-digital converter (TDC) with overflow bits is designed for low power applications. The overflow bits are added to the Vernier-TDC to reduce the stages of the TDC, thus saving power. A digital-to-time convertor is employed to realize the fractional division and reduce the stages of TDC. Fabricated in 55-nm CMOS, TDC together with DTC consumes only 360 μW when operating at 24 MHz. With the help of the TDC, the ADPLL achieves 1.69-psrms jitter with a 24-MHz reference clock and a 1.8GHz output RF clock.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128599316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/cicta.2018.8706031
{"title":"[Copyright notice]","authors":"","doi":"10.1109/cicta.2018.8706031","DOIUrl":"https://doi.org/10.1109/cicta.2018.8706031","url":null,"abstract":"","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116888846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706060
Han Yin, Xiaoxiang Wu, Jun Xu, Kunji Chen, Linwei Yu
One-dimensional (1D) nanostructures, such as semiconductor nanowires (NWs), nanobelts (NBs), and carbon nanotubes (CNTs), could be of ideal building blocks for electronic devices and might extend the remarkably successful scaling of microelectronics industry [3–6]. While the benefits of fin-gate field effective transistors (FET) have been very well established and implemented in micro-electronics, the same quasi-1D nano channel (diameter $lt100$ nm) technology is hard to apply in large area electronics where the resolution of lithography is only 2 or 3 um. Self-assembly growth mediated by nano metal droplets can offer a low cost and high throughput solution to manufacture of tiny crystalline silicon nanowires (SiNWs). However, a precise location and orientation control of the self-assembly SiNWs over large area are still difficult to achieve with the common vapor-liquid-solid (VLS) growth mechanism. In this work, we will introduce a new in-plane solid-liquid-solid (IPSLS) growth, [1] which enables a precise growth routine and geometry controls over the self-assembly SiNWs. During an IPSLS growth, an amorphous Si (a-Si) thin film is used as the precursor layer that is absorbed by nano droplets of indium (In) to move laterally and produce continuous crystalline SiNWs behind. This growth can be activated at a rather low temperature $lt 350$ °C in conventional PECVD system. Based on this unique capability, orderly crystalline SiNW channels can be easily manufactured over glass substrate, providing a key basis to fabricate high mobility fin-like thin film transistors (TFTs) for large area and high resolution display. Initial integration of the in-plane SiNWs for Fin-FETs has demonstrated a high hole mobility of $gt150$ cm2V–1s–1, high on/off ratio $gt 10^{6}$ and excellent subthreshold swing of only 120 mV/dec, via a low temperature procedure fully compatible to a-Si TFT technology. More importantly, thanks to a precise position and compositional controls over the tiny SiNWs [2–6], primitive logics can be constructed over the SiNW channels. Finally, a programmable geometry and line-shape engineering of the in-plane SiNWs will be showcased, which enables a reliable and low-cost fabrication of highly stretchable c-Si nano springs for high performance flexible and stretchable electronics. The SiNW logic device performance and the key control parameters of this IPSLS growth strategy, as well as its unique potentials in advanced 3D microelectronics, will be addressed.
{"title":"Deterministic deployment of in-plane silicon nanowires for high performance large area electronics","authors":"Han Yin, Xiaoxiang Wu, Jun Xu, Kunji Chen, Linwei Yu","doi":"10.1109/CICTA.2018.8706060","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706060","url":null,"abstract":"One-dimensional (1D) nanostructures, such as semiconductor nanowires (NWs), nanobelts (NBs), and carbon nanotubes (CNTs), could be of ideal building blocks for electronic devices and might extend the remarkably successful scaling of microelectronics industry [3–6]. While the benefits of fin-gate field effective transistors (FET) have been very well established and implemented in micro-electronics, the same quasi-1D nano channel (diameter $lt100$ nm) technology is hard to apply in large area electronics where the resolution of lithography is only 2 or 3 um. Self-assembly growth mediated by nano metal droplets can offer a low cost and high throughput solution to manufacture of tiny crystalline silicon nanowires (SiNWs). However, a precise location and orientation control of the self-assembly SiNWs over large area are still difficult to achieve with the common vapor-liquid-solid (VLS) growth mechanism. In this work, we will introduce a new in-plane solid-liquid-solid (IPSLS) growth, [1] which enables a precise growth routine and geometry controls over the self-assembly SiNWs. During an IPSLS growth, an amorphous Si (a-Si) thin film is used as the precursor layer that is absorbed by nano droplets of indium (In) to move laterally and produce continuous crystalline SiNWs behind. This growth can be activated at a rather low temperature $lt 350$ °C in conventional PECVD system. Based on this unique capability, orderly crystalline SiNW channels can be easily manufactured over glass substrate, providing a key basis to fabricate high mobility fin-like thin film transistors (TFTs) for large area and high resolution display. Initial integration of the in-plane SiNWs for Fin-FETs has demonstrated a high hole mobility of $gt150$ cm2V–1s–1, high on/off ratio $gt 10^{6}$ and excellent subthreshold swing of only 120 mV/dec, via a low temperature procedure fully compatible to a-Si TFT technology. More importantly, thanks to a precise position and compositional controls over the tiny SiNWs [2–6], primitive logics can be constructed over the SiNW channels. Finally, a programmable geometry and line-shape engineering of the in-plane SiNWs will be showcased, which enables a reliable and low-cost fabrication of highly stretchable c-Si nano springs for high performance flexible and stretchable electronics. The SiNW logic device performance and the key control parameters of this IPSLS growth strategy, as well as its unique potentials in advanced 3D microelectronics, will be addressed.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127561439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705712
A. Ruffino, Yatao Peng, E. Charbon
This work describes a basic interface between solidstate quantum bits (qubits) and classical environments. We describe a multiplexer, a circulator, and a low noise amplifier, designed for cryogenic temperature operation in a 40 nm CMOS technology node. The circuits take advantage of traditional design styles, such as transmission gates, passive LC filters and switches, and recent developments, such as differential noise cancelling with six-port transformers, while exploiting new cryogenic CMOS (cryo-CMOS) modeling for design and verification purposes.
{"title":"Interfacing Qubits via Cryo-CMOS Front Ends","authors":"A. Ruffino, Yatao Peng, E. Charbon","doi":"10.1109/CICTA.2018.8705712","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705712","url":null,"abstract":"This work describes a basic interface between solidstate quantum bits (qubits) and classical environments. We describe a multiplexer, a circulator, and a low noise amplifier, designed for cryogenic temperature operation in a 40 nm CMOS technology node. The circuits take advantage of traditional design styles, such as transmission gates, passive LC filters and switches, and recent developments, such as differential noise cancelling with six-port transformers, while exploiting new cryogenic CMOS (cryo-CMOS) modeling for design and verification purposes.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127025422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705724
Bo Pang, Shouxian Mou, F. Meng, Kaixue Ma
This paper presents a low voltage ultra-low power VCO for IEEE 802.11p vehicular communications application based on a 0.13-$mu$m CMOS technology. Compact and multiple strongly-coupled LC tanks are adopted for the frequency selection with improved quality factor and low phase noise. The cross-coupled transistors of VCO core work in the sub-threshold region rather than saturation to further reduce the current dissipation. The proposed VCO achieves −113.9 dBc/Hz phase noise at 1 MHz offset at center frequency 5.9 GHz and 11.1% tuning range with only 334 $mu$W power consumption and 0.13 mm$^{2}$ compact chip area.
{"title":"A Transformer Based Low Phase Noise Ultra-Low Power VCO for Vehicular Communication System","authors":"Bo Pang, Shouxian Mou, F. Meng, Kaixue Ma","doi":"10.1109/CICTA.2018.8705724","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705724","url":null,"abstract":"This paper presents a low voltage ultra-low power VCO for IEEE 802.11p vehicular communications application based on a 0.13-$mu$m CMOS technology. Compact and multiple strongly-coupled LC tanks are adopted for the frequency selection with improved quality factor and low phase noise. The cross-coupled transistors of VCO core work in the sub-threshold region rather than saturation to further reduce the current dissipation. The proposed VCO achieves −113.9 dBc/Hz phase noise at 1 MHz offset at center frequency 5.9 GHz and 11.1% tuning range with only 334 $mu$W power consumption and 0.13 mm$^{2}$ compact chip area.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128133061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706064
Xiayuan Wen, Hanwei Wang, Shuyang Jin, Jun Lin, Zhongfeng Wang
Burrows-Wheeler Transform (BWT) is an important algorithm in many fields including string matching for genome sequences. However, the implementations of BWT-based algorithms are limited due to the complexity of its sorting process. This paper presents a novel hardware architecture which can significantly reduce the number of sorting iterations. Experimental results show a significant reduction in both cycles and time to compute the BWT. Moreover, with the increase of Longest Common Prefix (LCP), our proposed architecture outperforms the traditional implementations further. In the worst case, it achieves 75.1× and 33.2× speedup compared with the Wavesorter architecture and the traditional parallel sorting network architecture respectively.
{"title":"A Novel Hardware Architecture to Accelerate Burrows-Wheeler Transform","authors":"Xiayuan Wen, Hanwei Wang, Shuyang Jin, Jun Lin, Zhongfeng Wang","doi":"10.1109/CICTA.2018.8706064","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706064","url":null,"abstract":"Burrows-Wheeler Transform (BWT) is an important algorithm in many fields including string matching for genome sequences. However, the implementations of BWT-based algorithms are limited due to the complexity of its sorting process. This paper presents a novel hardware architecture which can significantly reduce the number of sorting iterations. Experimental results show a significant reduction in both cycles and time to compute the BWT. Moreover, with the increase of Longest Common Prefix (LCP), our proposed architecture outperforms the traditional implementations further. In the worst case, it achieves 75.1× and 33.2× speedup compared with the Wavesorter architecture and the traditional parallel sorting network architecture respectively.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129644883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706087
Jingwei Wei, Xuan Li, Dongmei Li
A novel high dynamic range high speed column parallel single-slope ADC for CMOS image sensors is proposed. A gain adaptive structure is realized employing column lateral capacitors. With the help of a configurable up/down counter, this structure is compatible with dual correlated double sampling (CDS) scheme which acquires a capability of high noise suppression with no additional memories used. The nonlinearity of the proposed ADC is within 0.73% without extra calibration. Compared with conventional single-slope ADCs, the gain adaptive ADC extends dynamic range by 12dB in the same conversion time.
{"title":"A Gain-Adaptive Single-Slope ADC Employing Column Lateral Capacitors for CMOS Image Sensors","authors":"Jingwei Wei, Xuan Li, Dongmei Li","doi":"10.1109/CICTA.2018.8706087","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706087","url":null,"abstract":"A novel high dynamic range high speed column parallel single-slope ADC for CMOS image sensors is proposed. A gain adaptive structure is realized employing column lateral capacitors. With the help of a configurable up/down counter, this structure is compatible with dual correlated double sampling (CDS) scheme which acquires a capability of high noise suppression with no additional memories used. The nonlinearity of the proposed ADC is within 0.73% without extra calibration. Compared with conventional single-slope ADCs, the gain adaptive ADC extends dynamic range by 12dB in the same conversion time.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130020621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705948
Jiawang Hu, Shu Xu, Cong Zhang
In order to insure the message security between smart card and reader, a novel architecture of Elliptic Curve Cryptography (ECC) coprocessor for spin-torque transfer magnetic random access memory (STT-MRAM) based smart card chip is presented in this paper. By ingenious simplification of the formula and flexible conversion from affine coordinate to projective coordinate, several efficient algorithms are given from point multiplication operations to finite field computations. An elaborate module called modular arithmetic logical unit (MALU) is presented to effectively perform finite field computations over binary extension field GF($2^{163}$). Simulation and hardware implementation results show that the proposed ECC coprocessor can complete an encryption in only 3.3ms with only 1621 LUTs and 654 slices. The coprocessor is both compact and efficient, thus verify its feasibility and coordination with STT-MRAM in smart card chip.
{"title":"A Novel Architecture of ECC Coprocessor for STT-MRAM Based Smart Card Chip","authors":"Jiawang Hu, Shu Xu, Cong Zhang","doi":"10.1109/CICTA.2018.8705948","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705948","url":null,"abstract":"In order to insure the message security between smart card and reader, a novel architecture of Elliptic Curve Cryptography (ECC) coprocessor for spin-torque transfer magnetic random access memory (STT-MRAM) based smart card chip is presented in this paper. By ingenious simplification of the formula and flexible conversion from affine coordinate to projective coordinate, several efficient algorithms are given from point multiplication operations to finite field computations. An elaborate module called modular arithmetic logical unit (MALU) is presented to effectively perform finite field computations over binary extension field GF($2^{163}$). Simulation and hardware implementation results show that the proposed ECC coprocessor can complete an encryption in only 3.3ms with only 1621 LUTs and 654 slices. The coprocessor is both compact and efficient, thus verify its feasibility and coordination with STT-MRAM in smart card chip.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114338294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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