Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706116
Yifan Zhang, Min Tan
This paper presents a monolithic buck converter using a fully-integrated current-mode Type-III compensator for envelope tracking (ET) power amplifiers (PAs) in narrowband IoT (NB-IoT) applications. A dual-path current-mode compensator that combines a gain-boosting path and a phaseboosting path is proposed to reduce the area of the compensation network. The effectiveness of the proposed design is verified by extensive simulation results. With the proposed compensator, this design achieves 400 kHz crossover frequency at 2MHz switching frequency ($f_{SW}$).
{"title":"A Buck Converter Using A Fully-Integrated Current-Mode Dual-Path Type-III Compensator for NB-IoT Applications","authors":"Yifan Zhang, Min Tan","doi":"10.1109/CICTA.2018.8706116","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706116","url":null,"abstract":"This paper presents a monolithic buck converter using a fully-integrated current-mode Type-III compensator for envelope tracking (ET) power amplifiers (PAs) in narrowband IoT (NB-IoT) applications. A dual-path current-mode compensator that combines a gain-boosting path and a phaseboosting path is proposed to reduce the area of the compensation network. The effectiveness of the proposed design is verified by extensive simulation results. With the proposed compensator, this design achieves 400 kHz crossover frequency at 2MHz switching frequency ($f_{SW}$).","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130415911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706025
Md. Sadek Ali, M. K. H. Jewel, F. Lin
In this paper, a novel low-complexity channel estimation algorithm with estimation error suppression based on the conventional least squares (LS) method is proposed for downlink narrowband internet of things (NB-IoT) systems. This algorithm suppresses channel estimation error by employing additional operations on conventional LS method without exploiting extra frequency-band resources. The potentiality of the proposed algorithm is substantiated through extensive simulations in terms of channel mean square error (MSE) and block error rate (BLER) against signal-to-noise ratio (SNR). Simulation results vindicate that our proposed algorithm outperforms the conventional LS algorithm.
{"title":"An Efficient Channel Estimation Technique in NB-IoT Systems","authors":"Md. Sadek Ali, M. K. H. Jewel, F. Lin","doi":"10.1109/CICTA.2018.8706025","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706025","url":null,"abstract":"In this paper, a novel low-complexity channel estimation algorithm with estimation error suppression based on the conventional least squares (LS) method is proposed for downlink narrowband internet of things (NB-IoT) systems. This algorithm suppresses channel estimation error by employing additional operations on conventional LS method without exploiting extra frequency-band resources. The potentiality of the proposed algorithm is substantiated through extensive simulations in terms of channel mean square error (MSE) and block error rate (BLER) against signal-to-noise ratio (SNR). Simulation results vindicate that our proposed algorithm outperforms the conventional LS algorithm.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131397940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706054
M. J. Asadi, R. Jin, Z. Cao, G. Ding, V. Gholizadeh, H. F. Nied, J. Hwang, C. Goldsmith
To make MEMS varactors more robust and reliable, a closed-loop control circuit was designed to sense the varactor capacitance and tune the MEMS bias in real time to adjust the capacitance to the desired value within 1 fF and in 200 $mu$s. The designed circuit was successfully implemented in a standard RF CMOS technology despite the challenge for handling high voltage at high speed and for suppressing the substrate-coupled noise. The fabricated chip was tested to function according to the design simulation and to be capable of switching 150 V repeatedly.
{"title":"Mixed-Signal High-Voltage CMOS Control Circuit For RF MEMS Varactors","authors":"M. J. Asadi, R. Jin, Z. Cao, G. Ding, V. Gholizadeh, H. F. Nied, J. Hwang, C. Goldsmith","doi":"10.1109/CICTA.2018.8706054","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706054","url":null,"abstract":"To make MEMS varactors more robust and reliable, a closed-loop control circuit was designed to sense the varactor capacitance and tune the MEMS bias in real time to adjust the capacitance to the desired value within 1 fF and in 200 $mu$s. The designed circuit was successfully implemented in a standard RF CMOS technology despite the challenge for handling high voltage at high speed and for suppressing the substrate-coupled noise. The fabricated chip was tested to function according to the design simulation and to be capable of switching 150 V repeatedly.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123611543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706044
Xuepeng Zhan, F. Ma, Yuan Li, Jiezhi Chen, Huailiang Xu
In order to investigate the non-thermal ultrafast crystallization process, amorphous silicon films on two different substrates were subjected to femtosecond laser pulses. Phase transition was demonstrated by forming a new peak in Raman spectroscopy corresponding to single-crystalline silicon phase under stress. Surface morphologies of the pristine and processed amorphous silicon film were characterized by SEM and AFM, confirming the formation of nanocrystalline silicon. The ultrafast phase transition process were comparatively investigated on single-crystalline silicon substrates with and without cover oxide layer, indicating the non-thermal crystallizing amorphous silicon process via femtosecond laser pulses.
{"title":"Crystallizing amorphous silicon film by using femtosecond laser pulses","authors":"Xuepeng Zhan, F. Ma, Yuan Li, Jiezhi Chen, Huailiang Xu","doi":"10.1109/CICTA.2018.8706044","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706044","url":null,"abstract":"In order to investigate the non-thermal ultrafast crystallization process, amorphous silicon films on two different substrates were subjected to femtosecond laser pulses. Phase transition was demonstrated by forming a new peak in Raman spectroscopy corresponding to single-crystalline silicon phase under stress. Surface morphologies of the pristine and processed amorphous silicon film were characterized by SEM and AFM, confirming the formation of nanocrystalline silicon. The ultrafast phase transition process were comparatively investigated on single-crystalline silicon substrates with and without cover oxide layer, indicating the non-thermal crystallizing amorphous silicon process via femtosecond laser pulses.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124970956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705961
Yu Li, Shuo Chen, F. Lin
in this paper, the problem of coarse timing synchronization of low signal-to-noise radio (SNR) wireless orthogonal frequency-division-multiplexing systems (OFDM) for Internet of Things (IoT) is investigated. When OFDM is applied in IoT scenarios, the system needs to work at quite low SNR to achieve extended coverage. The proposed coarse synchronization method can response efficiently to the aforementioned challenge with a noise-eliminated timing metric. The simulation results of detection failure probability at different SNRs and number of processed frames indicate that significant performance improvement is obtained with the proposed scheme.
{"title":"A Coarse Timing Synchronization Method of Low SNR OFDM Systems for IoT","authors":"Yu Li, Shuo Chen, F. Lin","doi":"10.1109/CICTA.2018.8705961","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705961","url":null,"abstract":"in this paper, the problem of coarse timing synchronization of low signal-to-noise radio (SNR) wireless orthogonal frequency-division-multiplexing systems (OFDM) for Internet of Things (IoT) is investigated. When OFDM is applied in IoT scenarios, the system needs to work at quite low SNR to achieve extended coverage. The proposed coarse synchronization method can response efficiently to the aforementioned challenge with a noise-eliminated timing metric. The simulation results of detection failure probability at different SNRs and number of processed frames indicate that significant performance improvement is obtained with the proposed scheme.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"416 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116703729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a low power low frequency (LF) wake-up receiver was presented. To achieve high sensitivity, a selective amplifier, implemented in an architecture of three-stage fully differential cascade amplifier, utilized neutralization technique and high pass filters to achieve a maximum gain of 50 dB at 125 kHz while maintaining low power. The whole receiver was designed and fabricated in SMIC 0.18 $mu$m CMOS process with a total size of 0.96 m$mathrm{m}^{2}$. As a result, the measurements showed that the design achieved a sensitivity of 0.4 mVpp while dissipating just 4.2 $mu$A from a 3.3 V supply voltage.
{"title":"A 13. 8 μW Wake-Up Receiver With 0.4 mVpp Sensitivity For Low Frequency Applications","authors":"Wentao Xu, Zhige Zou, Jianming Lei, Qiaoling Tong, Wenhai Wu","doi":"10.1109/CICTA.2018.8706076","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706076","url":null,"abstract":"In this paper, a low power low frequency (LF) wake-up receiver was presented. To achieve high sensitivity, a selective amplifier, implemented in an architecture of three-stage fully differential cascade amplifier, utilized neutralization technique and high pass filters to achieve a maximum gain of 50 dB at 125 kHz while maintaining low power. The whole receiver was designed and fabricated in SMIC 0.18 $mu$m CMOS process with a total size of 0.96 m$mathrm{m}^{2}$. As a result, the measurements showed that the design achieved a sensitivity of 0.4 mVpp while dissipating just 4.2 $mu$A from a 3.3 V supply voltage.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116731316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706088
Jian He, Nan Qi, N. Yu, Liji Wu, P. Chiang, Xi Xiao, N. Wu
In this paper, we presented a low frequency equalizing continuous time linear equalizer (LFEQ-CTLE). It can compensate not only the low-frequency channel loss but also the high-frequency channel loss. The LFEQ-CTLE adopts the degeneration R-C and negative feedback loop to generate the high frequency zero/pole and low frequency zero/pole. Based on Global Foundry $130nm$ SiGe BiCMOS process to achieve the overall design, the proposed CTLE compensates for the 17dB channel loss at Nyquist frequency for 50GBaud PAM4 data rates.
{"title":"A 2nd-order CTLE in 130nm SiGe BiCMOS for a 50GBaud PAM4 Optical Driver","authors":"Jian He, Nan Qi, N. Yu, Liji Wu, P. Chiang, Xi Xiao, N. Wu","doi":"10.1109/CICTA.2018.8706088","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706088","url":null,"abstract":"In this paper, we presented a low frequency equalizing continuous time linear equalizer (LFEQ-CTLE). It can compensate not only the low-frequency channel loss but also the high-frequency channel loss. The LFEQ-CTLE adopts the degeneration R-C and negative feedback loop to generate the high frequency zero/pole and low frequency zero/pole. Based on Global Foundry $130nm$ SiGe BiCMOS process to achieve the overall design, the proposed CTLE compensates for the 17dB channel loss at Nyquist frequency for 50GBaud PAM4 data rates.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130849033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706071
O. J. Famoriji, Zhong-xiang Zhang, A. Fadamiro, Zakir Khan, F. Lin
A procedure based on Bayesian compressive sensing (BCS) is presented for faster and robust diagnosis of failed elements in large planar antenna arrays. The traditional approaches exhibit some drawbacks in effectiveness and reliability in noisy data. From measured samples of the far-field pattern, planar array diagnosis is formulated within the Bayesian framework and solved with a fast relevance vector machine (RVM). A 10GHz 10 by 10 rectangular microstrip patch antenna array that emulates element failure via zero excitation is then considered to test the proposed procedure. BCS approach provides faster diagnosis and robust to additive noise.
{"title":"Active Antenna Array Diagnosis from Far-Field Measurements","authors":"O. J. Famoriji, Zhong-xiang Zhang, A. Fadamiro, Zakir Khan, F. Lin","doi":"10.1109/CICTA.2018.8706071","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706071","url":null,"abstract":"A procedure based on Bayesian compressive sensing (BCS) is presented for faster and robust diagnosis of failed elements in large planar antenna arrays. The traditional approaches exhibit some drawbacks in effectiveness and reliability in noisy data. From measured samples of the far-field pattern, planar array diagnosis is formulated within the Bayesian framework and solved with a fast relevance vector machine (RVM). A 10GHz 10 by 10 rectangular microstrip patch antenna array that emulates element failure via zero excitation is then considered to test the proposed procedure. BCS approach provides faster diagnosis and robust to additive noise.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122124360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706045
Chi Zhang, Zhiqun Li, Guoxiao Cheng, Huan Wang, Zhennan Li
A 26.5-40 GHz broadband stacked power amplifier (PA) is designed in 130 nm SiGe BiCMOS process. By using triple-stacked HBTs, both output power and optimal load impedance increase, which is beneficial for wideband output matching. A low loss wideband two-way Wilkinson power combiner is used for on-chip power dividing and combining. EM simulation results show that from 26.5 to 40 GHz, the output 1- dB compressed power (PldB) and saturated output power (PSAT) are greater than 20.1dBm and 23.4dBm, respectively. The 40% fractional bandwidth PA has a gain over 15.9dB and peak power added efficiency (PAE) is greater than 19.2%. Static current is 58 mA for a supply voltage of 4.8 V. The chip size is 1.3 mm × 1.25 mm including all pads.
{"title":"A 26.5-40 GHz Stacked Power Amplifier in 130 nm SiGe BiCMOS Technology","authors":"Chi Zhang, Zhiqun Li, Guoxiao Cheng, Huan Wang, Zhennan Li","doi":"10.1109/CICTA.2018.8706045","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706045","url":null,"abstract":"A 26.5-40 GHz broadband stacked power amplifier (PA) is designed in 130 nm SiGe BiCMOS process. By using triple-stacked HBTs, both output power and optimal load impedance increase, which is beneficial for wideband output matching. A low loss wideband two-way Wilkinson power combiner is used for on-chip power dividing and combining. EM simulation results show that from 26.5 to 40 GHz, the output 1- dB compressed power (PldB) and saturated output power (PSAT) are greater than 20.1dBm and 23.4dBm, respectively. The 40% fractional bandwidth PA has a gain over 15.9dB and peak power added efficiency (PAE) is greater than 19.2%. Static current is 58 mA for a supply voltage of 4.8 V. The chip size is 1.3 mm × 1.25 mm including all pads.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122643302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706057
Ken Li, Yan Song, Li Dong, Li Geng
this paper presents a low-power 10-bit 200-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. By introducing a prediction logic, the ADC only needs to sample and quantize the difference between the input signal and the prediction value which is a rather low voltage. Thus some comparison cycles can be skipped and the power consumption is greatly saved. Conversion efficiency of the predicting logic with different interpolation orders is analyzed theoretically. The maximum efficiency improvement of 23% could be achieved comparing with that of 0th-order interpolation. A prototype oversampling SAR ADC with 2nd order of interpolation is designed with a standard 180nm CMOS technology. It achieves ENOB of 9.58 with total power of 574 nW and very low figure of merit (FoM) of 3.78 fJ/conv.-step.
{"title":"An oversampling SAR ADC with 2nd-order interpolation achieving maximum efficiency improvement of 23%","authors":"Ken Li, Yan Song, Li Dong, Li Geng","doi":"10.1109/CICTA.2018.8706057","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706057","url":null,"abstract":"this paper presents a low-power 10-bit 200-kS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. By introducing a prediction logic, the ADC only needs to sample and quantize the difference between the input signal and the prediction value which is a rather low voltage. Thus some comparison cycles can be skipped and the power consumption is greatly saved. Conversion efficiency of the predicting logic with different interpolation orders is analyzed theoretically. The maximum efficiency improvement of 23% could be achieved comparing with that of 0th-order interpolation. A prototype oversampling SAR ADC with 2nd order of interpolation is designed with a standard 180nm CMOS technology. It achieves ENOB of 9.58 with total power of 574 nW and very low figure of merit (FoM) of 3.78 fJ/conv.-step.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116293440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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