Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705952
Liu Qiang, Xia Jianwen, Huang Mingqi, L. Jinhui, Zhang Guopingi
with the development of semiconductor industry, temporary bonding materials become more and more widely used in various process applications, such as wafer thinning, ultra-thin device preparation, thin wafers handing and so on. Different process applications may need different requirements for the application performance of materials. For example, the temporary bonding adhesive may be bonded with different surface of device wafer like gold layer, silicon and glass, which may also show different adhesive property. What needs to be emphasized is that the bonding wafers are easily peeling off with lower bonding strength, which may lead to low yield. And the bonding wafers with higher bonding strength may difficult to be released and cleaned. Therefore, the bonding strength of temporary bonding adhesive applied to different substrates should be considered as a crucial factor for application. There are several methods to release the wafers when de-bonding such as thermal sliding, mechanical peeling, solvent release and laser irradiation. In this paper, UV laser release systems with release layer and adhesive layer was focused. We studied several adhesive materials (both Adhesive B and Adhesive C were modified by Adhesive A) which showed different shearing strength with different substrates such as gold, silicon and glass. The shearing strength was studied by thrust force shearing force tester (DAGE 4000, USA). The chip with the size of 1mm ×1 mm was bonded on the substrates by the same pressure. The study showed that Adhesive C has higher shearing strength on different substrate. In addition, thermal stability was investigated by thermal gravimetric analyzer (TGA/DSC 2, Germany).
{"title":"Shearing strength of temporary bonding adhesive applied to different substrates","authors":"Liu Qiang, Xia Jianwen, Huang Mingqi, L. Jinhui, Zhang Guopingi","doi":"10.1109/CICTA.2018.8705952","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705952","url":null,"abstract":"with the development of semiconductor industry, temporary bonding materials become more and more widely used in various process applications, such as wafer thinning, ultra-thin device preparation, thin wafers handing and so on. Different process applications may need different requirements for the application performance of materials. For example, the temporary bonding adhesive may be bonded with different surface of device wafer like gold layer, silicon and glass, which may also show different adhesive property. What needs to be emphasized is that the bonding wafers are easily peeling off with lower bonding strength, which may lead to low yield. And the bonding wafers with higher bonding strength may difficult to be released and cleaned. Therefore, the bonding strength of temporary bonding adhesive applied to different substrates should be considered as a crucial factor for application. There are several methods to release the wafers when de-bonding such as thermal sliding, mechanical peeling, solvent release and laser irradiation. In this paper, UV laser release systems with release layer and adhesive layer was focused. We studied several adhesive materials (both Adhesive B and Adhesive C were modified by Adhesive A) which showed different shearing strength with different substrates such as gold, silicon and glass. The shearing strength was studied by thrust force shearing force tester (DAGE 4000, USA). The chip with the size of 1mm ×1 mm was bonded on the substrates by the same pressure. The study showed that Adhesive C has higher shearing strength on different substrate. In addition, thermal stability was investigated by thermal gravimetric analyzer (TGA/DSC 2, Germany).","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128405172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705711
Zongming Duan, Dongfang Pan, Yan Wang, Bingbing Liao, Yuefei Dai, F. Lin
a 76-81 GHz receiver (Rx) front-end is implemented in 65-nm COMS for automotive radar. The front-end consists of a low noise amplifier (LNA), an interstage network with two-stage transformer, and a mixer core with transconductance (Gm) stage and quad-switch. Flyback transformer-feedback technique is adopted for the three-stage common source (CS) LNA. Traditional Gilbert-mixer is improved by inset a transformer balun between Gm stage and switch stage. Therefore, high-linearity performance can be achieved. The Rx front-end consumes 22mW and the input 1dB compression point (P1dB) is - 15.5 dBm at 80 GHz. The conversion gain (CG) is 8.5-11.5 dB at 76-81 GHz, while noise figure is 7.2-8.7 dB. The chip size is only 0.23 mm2 excluding PADs.
{"title":"A 76-81GHz High-linearity CMOS Receiver Front-end for Automotive Radar","authors":"Zongming Duan, Dongfang Pan, Yan Wang, Bingbing Liao, Yuefei Dai, F. Lin","doi":"10.1109/CICTA.2018.8705711","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705711","url":null,"abstract":"a 76-81 GHz receiver (Rx) front-end is implemented in 65-nm COMS for automotive radar. The front-end consists of a low noise amplifier (LNA), an interstage network with two-stage transformer, and a mixer core with transconductance (Gm) stage and quad-switch. Flyback transformer-feedback technique is adopted for the three-stage common source (CS) LNA. Traditional Gilbert-mixer is improved by inset a transformer balun between Gm stage and switch stage. Therefore, high-linearity performance can be achieved. The Rx front-end consumes 22mW and the input 1dB compression point (P1dB) is - 15.5 dBm at 80 GHz. The conversion gain (CG) is 8.5-11.5 dB at 76-81 GHz, while noise figure is 7.2-8.7 dB. The chip size is only 0.23 mm2 excluding PADs.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"17 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123521159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706074
Wei Zhang, Xiulan Cheng, Xiaodong Wang
Low compensation Ti/TiN/Al film resistor including resistance and two pads was designed and fabricated with one step of lithography and metal sputter. The fabricated 8$mu$m width near 50$Omega$ resistor was stable and precise after annealing, which can be loaded with 8V DC voltage for over 60 minutes.
{"title":"Development and Characterization of Ti/TiN/Al Film Compensation Resistor with Low Resistance","authors":"Wei Zhang, Xiulan Cheng, Xiaodong Wang","doi":"10.1109/CICTA.2018.8706074","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706074","url":null,"abstract":"Low compensation Ti/TiN/Al film resistor including resistance and two pads was designed and fabricated with one step of lithography and metal sputter. The fabricated 8$mu$m width near 50$Omega$ resistor was stable and precise after annealing, which can be loaded with 8V DC voltage for over 60 minutes.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121351941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706094
Liang Zhao, Xiaobing Ding, Jiaqi Yang, F. Lin
A 2b/cycle nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this brief. Two capacitor DACs, a Signal-DAC (SIG-DAC) and a Reference-DAC (REF-DAC), which are used to implement the 2b/cycle architecture, are designed to be nonbinary weighted. Such an approach can make the ADC robust enough to comparator offset variations and mismatch between DACs. In DAC settling phase, with splitting capacitors array, both the SIGDAC and REF-DAC capacitors use monotonic switching method, which can reduce the power dissipation and speed up the conversion. A prototype 9b ADC using 130-nm Silicon-On-Insulator (SOI) CMOS process works at 80MS/s from 1.2V supply, the simulation results shows a signal-to-noise plus distortion ratio (SNDR) of 50.40dB and a spurious-free dynamic range (SFDR) of 52.94dB. The total power consumption of the ADC is 0.696mW and the FoM is 32 fJ/conversion-step.
{"title":"A 0.696-mW 9-bit 80-MS/s 2-b/cycle Nonbinary SAR ADC in 130-nm SOI CMOS","authors":"Liang Zhao, Xiaobing Ding, Jiaqi Yang, F. Lin","doi":"10.1109/CICTA.2018.8706094","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706094","url":null,"abstract":"A 2b/cycle nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this brief. Two capacitor DACs, a Signal-DAC (SIG-DAC) and a Reference-DAC (REF-DAC), which are used to implement the 2b/cycle architecture, are designed to be nonbinary weighted. Such an approach can make the ADC robust enough to comparator offset variations and mismatch between DACs. In DAC settling phase, with splitting capacitors array, both the SIGDAC and REF-DAC capacitors use monotonic switching method, which can reduce the power dissipation and speed up the conversion. A prototype 9b ADC using 130-nm Silicon-On-Insulator (SOI) CMOS process works at 80MS/s from 1.2V supply, the simulation results shows a signal-to-noise plus distortion ratio (SNDR) of 50.40dB and a spurious-free dynamic range (SFDR) of 52.94dB. The total power consumption of the ADC is 0.696mW and the FoM is 32 fJ/conversion-step.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124606409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706055
King Zeng, Xiaojun Bi
A slotline-based balun with wide bandwidth and high isolation is proposed in this paper. The proposed balun integrates Wilkinson power divider, which is devoted to improving the isolation between the differential output ports. By utilizing asymmetrical slotline and symmetrical output microstrip, the implemented balun achieves excellent balance performance and wideband response. The simulation results demonstrate a wideband property with a return loss better than 10 dB from 4.4 GHz to 20.4 GHz, an improved minimum isolation of 10 dB as well as competitive balance performances including 0.5 dB amplitude imbalance and 3. 7 phase imbalance.
{"title":"Slotline-Based Balun with Wide Bandwidth and High Isolation","authors":"King Zeng, Xiaojun Bi","doi":"10.1109/CICTA.2018.8706055","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706055","url":null,"abstract":"A slotline-based balun with wide bandwidth and high isolation is proposed in this paper. The proposed balun integrates Wilkinson power divider, which is devoted to improving the isolation between the differential output ports. By utilizing asymmetrical slotline and symmetrical output microstrip, the implemented balun achieves excellent balance performance and wideband response. The simulation results demonstrate a wideband property with a return loss better than 10 dB from 4.4 GHz to 20.4 GHz, an improved minimum isolation of 10 dB as well as competitive balance performances including 0.5 dB amplitude imbalance and 3. 7 phase imbalance.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115722439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706067
F. Farrukh, Tuo Xie, Chun Zhang, Zhihua Wang
Deep neural networks (DNN) have been a hot research topic in recent years. The key element of DNN is to explore the real time hardware implementation. However, it requires a complete knowledge of hardware where the DNN is going to be implemented. The computational complexity and resource consumption of DNN is increasing by the time. Convolutional Neural Network (CNN) is the popular architecture of DNN especially for image classification. One requires an efficient implementation strategy of CNN to incorporate more computations in real time. Field Programmable Gate Array (FPGA) is considered to be the energy efficient choice for CNN as compared to Graphical Processing Units (GPUs). In this paper, new idea is explored and implemented for basic Processing Element (PE) of CNN. FPGA has limited built-in multiplier accumulator (MAC) units. In this work, MAC units are replaced by Wallace Tree based Multiplier which belongs to the family of log time array multipliers. The resources are saved in terms of MAC units and we can implement more processing elements on FPGA.
{"title":"Optimization for Efficient Hardware Implementation of CNN on FPGA","authors":"F. Farrukh, Tuo Xie, Chun Zhang, Zhihua Wang","doi":"10.1109/CICTA.2018.8706067","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706067","url":null,"abstract":"Deep neural networks (DNN) have been a hot research topic in recent years. The key element of DNN is to explore the real time hardware implementation. However, it requires a complete knowledge of hardware where the DNN is going to be implemented. The computational complexity and resource consumption of DNN is increasing by the time. Convolutional Neural Network (CNN) is the popular architecture of DNN especially for image classification. One requires an efficient implementation strategy of CNN to incorporate more computations in real time. Field Programmable Gate Array (FPGA) is considered to be the energy efficient choice for CNN as compared to Graphical Processing Units (GPUs). In this paper, new idea is explored and implemented for basic Processing Element (PE) of CNN. FPGA has limited built-in multiplier accumulator (MAC) units. In this work, MAC units are replaced by Wallace Tree based Multiplier which belongs to the family of log time array multipliers. The resources are saved in terms of MAC units and we can implement more processing elements on FPGA.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127070391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706096
Qi Lin, Qu Cheng, H. Tong, X. Miao
In this letter, we proposed a special design method to realize both high on-current and selectivity of selectors. By introducing CuS as ion supply layer, our proposed selector supplies limited Cu ions to form weak filament to switch on at voltage over Vth, and effectively retract Cu ions to break down the filament to switch off at voltage lower than Vhold. Meanwhile, high-defect-density and wide-band-gap chalcogenide GeSe assists the diffusion process of Cu atoms and enhance selectivity.
{"title":"A Selector with Special Design for High on-current and Selectivity","authors":"Qi Lin, Qu Cheng, H. Tong, X. Miao","doi":"10.1109/CICTA.2018.8706096","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706096","url":null,"abstract":"In this letter, we proposed a special design method to realize both high on-current and selectivity of selectors. By introducing CuS as ion supply layer, our proposed selector supplies limited Cu ions to form weak filament to switch on at voltage over Vth, and effectively retract Cu ions to break down the filament to switch off at voltage lower than Vhold. Meanwhile, high-defect-density and wide-band-gap chalcogenide GeSe assists the diffusion process of Cu atoms and enhance selectivity.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114254662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706070
Guanhua Wang, Chenchang Zhan, Junyao Tang, Ning Zhang
An NMOS LDO regulator using a dynamic replica to significantly improve the regulation precision is presented. By sensing the load current and dynamically adjusting the replica current, the power transistor is biased properly to improve regulation without compromising the all-condition stability of a classical fixed-replica regulator. The proposed LDO regulator is implemented in a 0.18-μm CMOS process, occupying an active chip area of 0.039 mm2. With 1.2 V input and 1.1 V nominal output voltage, the proposed design achieves 5 times improved load regulation, at the same time demonstrating stable and fast transient responses over the wide load capacitance range from 0 to virtually infinity.
{"title":"Dynamic-Replica-Based All-Condition-Stable LDO Regulator with 5X Improved Load Regulation","authors":"Guanhua Wang, Chenchang Zhan, Junyao Tang, Ning Zhang","doi":"10.1109/CICTA.2018.8706070","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706070","url":null,"abstract":"An NMOS LDO regulator using a dynamic replica to significantly improve the regulation precision is presented. By sensing the load current and dynamically adjusting the replica current, the power transistor is biased properly to improve regulation without compromising the all-condition stability of a classical fixed-replica regulator. The proposed LDO regulator is implemented in a 0.18-μm CMOS process, occupying an active chip area of 0.039 mm2. With 1.2 V input and 1.1 V nominal output voltage, the proposed design achieves 5 times improved load regulation, at the same time demonstrating stable and fast transient responses over the wide load capacitance range from 0 to virtually infinity.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124321957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8705947
Ke Xu, Yu Li, Bin Han, Xiao Zhang, Xin Liu, Jisong Ai
this paper presents the design and VLSI implementation of a CVE (Computer Vision Engine) for real-time video analysis. It offloads CPU/GPU for the power-hungry computation for various vision tasks such as face detection, object detection, motion tracking, etc. The design features 22 computation kernels and is divided into three main categories. The proposed CVE is integrated in a smart video surveillance SoC (System on Chip) and fabricated with TSMC 28nm technology. The total hardware costs are 392K gates and 75.5 KB memory. The measured results show that the design is able to achieve $1920times1080$ 30fps real-time video analysis when running at 400MHz. The total power consumption is 20mW and 0.32nJ/pixel of energy efficiency.
{"title":"A Low-power Computer Vision Engine for Video Surveillance","authors":"Ke Xu, Yu Li, Bin Han, Xiao Zhang, Xin Liu, Jisong Ai","doi":"10.1109/CICTA.2018.8705947","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8705947","url":null,"abstract":"this paper presents the design and VLSI implementation of a CVE (Computer Vision Engine) for real-time video analysis. It offloads CPU/GPU for the power-hungry computation for various vision tasks such as face detection, object detection, motion tracking, etc. The design features 22 computation kernels and is divided into three main categories. The proposed CVE is integrated in a smart video surveillance SoC (System on Chip) and fabricated with TSMC 28nm technology. The total hardware costs are 392K gates and 75.5 KB memory. The measured results show that the design is able to achieve $1920times1080$ 30fps real-time video analysis when running at 400MHz. The total power consumption is 20mW and 0.32nJ/pixel of energy efficiency.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115028266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CICTA.2018.8706118
L. Xue, N. Yan, Yun Yin, Hongtao Xu
a robust low-pass filter (LPF) with bandgap reference for automotive and industrial applications is proposed in this paper. Bandgap reference provides suitable bias current for LPF. The low-pass filter consists of transimpedance amplifier (TIA) and programmable gain amplifier (PGA). A three-stage fully differential amplifier is used in both TIA and PGA. Common-mode Level Controlling Block (CLCB) and Resistor Controlling Block (RCB) are designed to adjust the input common-mode level and gain of LPF, respectively. According to the post layout simulation results, maximum of LPF gain achieves 21.42dB on nominal corner, while the proposed LPF is robust enough to work and keep stable gain over different process corners and across a wide temperature range.
{"title":"Robust Low-Pass Filter Design with Bandgap Reference for Automotive and Industrial Applications","authors":"L. Xue, N. Yan, Yun Yin, Hongtao Xu","doi":"10.1109/CICTA.2018.8706118","DOIUrl":"https://doi.org/10.1109/CICTA.2018.8706118","url":null,"abstract":"a robust low-pass filter (LPF) with bandgap reference for automotive and industrial applications is proposed in this paper. Bandgap reference provides suitable bias current for LPF. The low-pass filter consists of transimpedance amplifier (TIA) and programmable gain amplifier (PGA). A three-stage fully differential amplifier is used in both TIA and PGA. Common-mode Level Controlling Block (CLCB) and Resistor Controlling Block (RCB) are designed to adjust the input common-mode level and gain of LPF, respectively. According to the post layout simulation results, maximum of LPF gain achieves 21.42dB on nominal corner, while the proposed LPF is robust enough to work and keep stable gain over different process corners and across a wide temperature range.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123813852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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