Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510284
S. Clerc, F. Abouzeid, V. Heinrich, A. Jain, A. Veggetti, D. Crippa, P. Roche, G. Sicard
Following the will to answer to the energy constrained applications requirements, an Ultra-Low Voltage (ULV) 40nm Bose-Chaudhuri-Hocquenghem (BCH) error-correcting circuit is presented. Mapped on a ULV specific standard cells library, the circuit was designed following standard industrial implementation and verification flows. The BCH circuit runs at 0.330V, 600kHz frequency and needs 1.27nJ to decode a 252bits frame. With 14% of extra power compared to typical process, applying forward bias enables to compensate temperature and skewed process effects, regaining 150mV minimum operating voltage.
{"title":"A 40nm CMOS, 1.27nJ, 330mV, 600kHz, Bose Chaudhuri Hocquenghem 252 bits frame decoder","authors":"S. Clerc, F. Abouzeid, V. Heinrich, A. Jain, A. Veggetti, D. Crippa, P. Roche, G. Sicard","doi":"10.1109/ICICDT.2010.5510284","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510284","url":null,"abstract":"Following the will to answer to the energy constrained applications requirements, an Ultra-Low Voltage (ULV) 40nm Bose-Chaudhuri-Hocquenghem (BCH) error-correcting circuit is presented. Mapped on a ULV specific standard cells library, the circuit was designed following standard industrial implementation and verification flows. The BCH circuit runs at 0.330V, 600kHz frequency and needs 1.27nJ to decode a 252bits frame. With 14% of extra power compared to typical process, applying forward bias enables to compensate temperature and skewed process effects, regaining 150mV minimum operating voltage.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124629193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510264
M. Tack
An overview is given of the main technology trends and innovations in Power MOSFET transistors ranging from LV(<50V), MV (50V-200V) to HV (200V-1000V), in view of the needs for high energy efficient power management systems. Alternatives to MOSFET, like IGBT and GaN-HEMT, are briefly highlighted and discussed.
{"title":"Energy efficient power MOSFETs","authors":"M. Tack","doi":"10.1109/ICICDT.2010.5510264","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510264","url":null,"abstract":"An overview is given of the main technology trends and innovations in Power MOSFET transistors ranging from LV(<50V), MV (50V-200V) to HV (200V-1000V), in view of the needs for high energy efficient power management systems. Alternatives to MOSFET, like IGBT and GaN-HEMT, are briefly highlighted and discussed.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127225010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510255
Y. Sun, Minxuan Zhang, Shaoqing Li, Yali Zhao
Soft errors in combinational logic have been considered as an important challenge for VLSI circuit design. As a kind of representative element of combinational logic, adders are widely used in arithmetic units. This paper presents a cost effective soft error mitigation technique for high speed parallel adders. By exploiting inherent hardware redundancy and temporal redundancy of circuit, this technique greatly reduces area overhead and delay overhead of fault tolerance. We also combine C-element-based error correction techniques with inherent hardware and temporal redundancy to enhance error correction capability of adders. In addition, we propose a new metric ADP to evaluate global overheads of soft error mitigation. Experiments show that the proposed technique can correct 93.76% of soft errors only with 12.23% of area and 6.41% of delay overhead. The proposed adder has the least ADP and best tradeoff between area and delay overhead of all previous designs.
{"title":"Cost effective soft error mitigation for parallel adders by exploiting inherent redundancy","authors":"Y. Sun, Minxuan Zhang, Shaoqing Li, Yali Zhao","doi":"10.1109/ICICDT.2010.5510255","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510255","url":null,"abstract":"Soft errors in combinational logic have been considered as an important challenge for VLSI circuit design. As a kind of representative element of combinational logic, adders are widely used in arithmetic units. This paper presents a cost effective soft error mitigation technique for high speed parallel adders. By exploiting inherent hardware redundancy and temporal redundancy of circuit, this technique greatly reduces area overhead and delay overhead of fault tolerance. We also combine C-element-based error correction techniques with inherent hardware and temporal redundancy to enhance error correction capability of adders. In addition, we propose a new metric ADP to evaluate global overheads of soft error mitigation. Experiments show that the proposed technique can correct 93.76% of soft errors only with 12.23% of area and 6.41% of delay overhead. The proposed adder has the least ADP and best tradeoff between area and delay overhead of all previous designs.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510296
G. Langguth, C. Russ, W. Soldner, B. Stein, H. Gossner
State-of-the-art Systems on Chip (SoC) for mobile phone applications integrate on one single chip the digital baseband core with analog blocks like power management unit, RF transceiver and mixed-signal sub-circuits. Performance considerations in such complex SoC designs include the use of ESD sensitive circuit topologies, such as thin oxide devices directly connected to I/O pads or implemented within high voltage domains, which both create new ESD challenges in advanced CMOS technology nodes. Based on 65 nm CMOS SoCs, we summarize known ESD challenges and unveil hidden issues. While advanced CMOS technology nodes already present very delicate environments with an extremely narrow window for ESD design, CDM discharge currents reach 5 to 10 A due to increased chip area. Different ESD protection concepts for a low noise amplifier (LNA) are compared where the RF-input pin connects directly to a thin oxide gate. Very-fast TLP results are correlated to on-product CDM performance. A slow turn-on behavior under fast-transient ESD stress makes the ICs particularly sensitive. In mixed device design, thin oxide devices are used in high voltage domains for which these devices are natively not suited. Reliability is ensured by extensive precautions in circuit design such no critical voltage is exceeded. ESD results of typical mixed device topologies will be discussed by associated failure modes and a protection strategy will be developed.
{"title":"ESD challenges in advanced CMOS systems on chip","authors":"G. Langguth, C. Russ, W. Soldner, B. Stein, H. Gossner","doi":"10.1109/ICICDT.2010.5510296","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510296","url":null,"abstract":"State-of-the-art Systems on Chip (SoC) for mobile phone applications integrate on one single chip the digital baseband core with analog blocks like power management unit, RF transceiver and mixed-signal sub-circuits. Performance considerations in such complex SoC designs include the use of ESD sensitive circuit topologies, such as thin oxide devices directly connected to I/O pads or implemented within high voltage domains, which both create new ESD challenges in advanced CMOS technology nodes. Based on 65 nm CMOS SoCs, we summarize known ESD challenges and unveil hidden issues. While advanced CMOS technology nodes already present very delicate environments with an extremely narrow window for ESD design, CDM discharge currents reach 5 to 10 A due to increased chip area. Different ESD protection concepts for a low noise amplifier (LNA) are compared where the RF-input pin connects directly to a thin oxide gate. Very-fast TLP results are correlated to on-product CDM performance. A slow turn-on behavior under fast-transient ESD stress makes the ICs particularly sensitive. In mixed device design, thin oxide devices are used in high voltage domains for which these devices are natively not suited. Reliability is ensured by extensive precautions in circuit design such no critical voltage is exceeded. ESD results of typical mixed device topologies will be discussed by associated failure modes and a protection strategy will be developed.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"259 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133848120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510252
M. Nicolaidis
In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft-errors, a concern in the past for space applications, became a reliability issue at ground-level. Alpha particles and atmospheric neutrons induce single event upsets (SEU) affecting memory cells, latches and flip-flops, and single event transients (SET) initiated in the combinational logic and captured by the associated latches and flip-flops. To face this challenge, a designer must dispose a variety of soft-error mitigation schemes adapted to various circuit structures, design architectures and design constraints. In this paper, we describe several SEU and SET mitigation schemes that could help designers to meet their reliability constraints.
{"title":"Design techniques for soft-error mitigation","authors":"M. Nicolaidis","doi":"10.1109/ICICDT.2010.5510252","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510252","url":null,"abstract":"In nanometric technologies, circuits are increasingly sensitive to various kinds of perturbations. Soft-errors, a concern in the past for space applications, became a reliability issue at ground-level. Alpha particles and atmospheric neutrons induce single event upsets (SEU) affecting memory cells, latches and flip-flops, and single event transients (SET) initiated in the combinational logic and captured by the associated latches and flip-flops. To face this challenge, a designer must dispose a variety of soft-error mitigation schemes adapted to various circuit structures, design architectures and design constraints. In this paper, we describe several SEU and SET mitigation schemes that could help designers to meet their reliability constraints.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124822471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510268
J. Keane, Xiaofei Wang, D. Persaud, C. Kim
We present an on-chip reliability monitor capable of separating the aging effects of Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time Dependent Dielectric Breakdown (TDDB) with high frequency resolution. Sub-µs measurements are controlled by on-chip logic in order to avoid excessive unwanted BTI recovery during stress interruptions. Frequency shift measurement resolution of down to the error floor of 0.07% is achieved during these short interruptions using a beat frequency detection system, and we automate the experiments through a simple digital interface. Measurement results are presented from a 65 nm test chip.
{"title":"A high resolution on-chip beat frequency detection system for measuring BTI, HCI, and TDDB","authors":"J. Keane, Xiaofei Wang, D. Persaud, C. Kim","doi":"10.1109/ICICDT.2010.5510268","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510268","url":null,"abstract":"We present an on-chip reliability monitor capable of separating the aging effects of Hot Carrier Injection (HCI), Bias Temperature Instability (BTI), and Time Dependent Dielectric Breakdown (TDDB) with high frequency resolution. Sub-µs measurements are controlled by on-chip logic in order to avoid excessive unwanted BTI recovery during stress interruptions. Frequency shift measurement resolution of down to the error floor of 0.07% is achieved during these short interruptions using a beat frequency detection system, and we automate the experiments through a simple digital interface. Measurement results are presented from a 65 nm test chip.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126051062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510299
S. Thijs, D. Trémouilles, D. Linten, N. M. Iyer, A. Griffoni, G. Groeseneken
Two novel ESD power clamp design techniques for SOI FinFET CMOS technology are reported. First, a layout improvement technique is discussed for stacked gated diodes, which reduces the required area for a given ESD robustness and at the same time reduces the on-resistance of the clamp. Secondly, circuit design techniques are used to convert a standard RC-triggered active ESD clamp into a bi-directional design, thereby alleviating the need for a separate reverse protection diode. The concepts can be applied for planar SOI as well.
{"title":"Advanced ESD power clamp design for SOI FinFET CMOS technology","authors":"S. Thijs, D. Trémouilles, D. Linten, N. M. Iyer, A. Griffoni, G. Groeseneken","doi":"10.1109/ICICDT.2010.5510299","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510299","url":null,"abstract":"Two novel ESD power clamp design techniques for SOI FinFET CMOS technology are reported. First, a layout improvement technique is discussed for stacked gated diodes, which reduces the required area for a given ESD robustness and at the same time reduces the on-resistance of the clamp. Secondly, circuit design techniques are used to convert a standard RC-triggered active ESD clamp into a bi-directional design, thereby alleviating the need for a separate reverse protection diode. The concepts can be applied for planar SOI as well.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116007042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510280
K. Eriguchi, M. Kamei, Y. Takao, K. Ono
This paper presents the impacts of plasma-induced damage on an off-state leakage current increase in scaled MOSFETs. Si recess structure in the source/drain extension region formed by high-energy ion bombardment is focused on. In addition to the effect of gate length shrinkage on subthreshold leakage current (Ioff) increase discussed so far, plasma-induced damage (PID) is found to increase Ioff drastically, in particular, for the MOSFET with a gate length shorter than 65 nm. Technology CAD simulations were performed to verify the effect. Since the recess depth is modeled by an analytical expression with the energy of ion from plasma on the basis of a modified range theory, the increase in Ioff can be estimated from plasma process condition. A scenario for significant enhancement in the statistical Ioff-distribution by PID is also discussed.
{"title":"Modeling the effects of plasma-induced physical damage on subthreshold leakage current in scaled MOSFETs","authors":"K. Eriguchi, M. Kamei, Y. Takao, K. Ono","doi":"10.1109/ICICDT.2010.5510280","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510280","url":null,"abstract":"This paper presents the impacts of plasma-induced damage on an off-state leakage current increase in scaled MOSFETs. Si recess structure in the source/drain extension region formed by high-energy ion bombardment is focused on. In addition to the effect of gate length shrinkage on subthreshold leakage current (Ioff) increase discussed so far, plasma-induced damage (PID) is found to increase Ioff drastically, in particular, for the MOSFET with a gate length shorter than 65 nm. Technology CAD simulations were performed to verify the effect. Since the recess depth is modeled by an analytical expression with the energy of ion from plasma on the basis of a modified range theory, the increase in Ioff can be estimated from plasma process condition. A scenario for significant enhancement in the statistical Ioff-distribution by PID is also discussed.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134026310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510257
D. Alexandrescu
Single Event Effects (SEEs) may cause system downtime, data corruption and maintenance incidents. Thus, the SEE are a threat to the overall system reliability, causing designers to be increasingly concerned about the analysis and the mitigation of radiation-induced failures, even for commercial systems performing in a natural working environment. Experts and reliability engineers are called in to support chip designers in the management of Single Event Effects. To this goal, we present a design-flow-oriented Soft Error Rate analysis methodology geared to allow practical and concrete decisions concerning implementation, design and functional choices in order to minimize SEEs impact on circuit and system behavior.
{"title":"Reflections on a SER-aware design flow","authors":"D. Alexandrescu","doi":"10.1109/ICICDT.2010.5510257","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510257","url":null,"abstract":"Single Event Effects (SEEs) may cause system downtime, data corruption and maintenance incidents. Thus, the SEE are a threat to the overall system reliability, causing designers to be increasingly concerned about the analysis and the mitigation of radiation-induced failures, even for commercial systems performing in a natural working environment. Experts and reliability engineers are called in to support chip designers in the management of Single Event Effects. To this goal, we present a design-flow-oriented Soft Error Rate analysis methodology geared to allow practical and concrete decisions concerning implementation, design and functional choices in order to minimize SEEs impact on circuit and system behavior.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123933693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510256
L. Wernersson, M. Egard, M. Arlelid, E. Lind
We describe the implementation of a gated resonant tunneling diode and its application in a wavelet generator. The GaAs-based device is fabricated by embedding a metal gate directly above a double barrier heterostructure with a peak current of 120 kA/cm2. The gate is used to modulate the tunneling current via the Schottky depletion around the buried metal. We integrate the gated tunnel diodes in oscillator circuits and use the gate to form RF-bursts or wavelets. Measured data in the K- and V-band verify a good control of the length, phase, and pulse position reaching for pulses with lengths well below 100 ps.
{"title":"Tunneling-based devices and circuits","authors":"L. Wernersson, M. Egard, M. Arlelid, E. Lind","doi":"10.1109/ICICDT.2010.5510256","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510256","url":null,"abstract":"We describe the implementation of a gated resonant tunneling diode and its application in a wavelet generator. The GaAs-based device is fabricated by embedding a metal gate directly above a double barrier heterostructure with a peak current of 120 kA/cm2. The gate is used to modulate the tunneling current via the Schottky depletion around the buried metal. We integrate the gated tunnel diodes in oscillator circuits and use the gate to form RF-bursts or wavelets. Measured data in the K- and V-band verify a good control of the length, phase, and pulse position reaching for pulses with lengths well below 100 ps.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"177 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132387498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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