Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510267
P. Gentric
Emerging screen technologies, such as Electrophoretic Displays (EPD) used in E-book Readers, are changing product power requirements due to their advantageous properties such as bi-stability (effective "zero power" static display) and reflective mode of operation (no backlight). We will first review the emerging screen technologies under the angle of system and IC design impact. We will explain power management consequences for IC design, with a focus on Application Engine SOCs for the wireless/portable markets.
{"title":"Emerging screen technologies impact on application engine IC power","authors":"P. Gentric","doi":"10.1109/ICICDT.2010.5510267","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510267","url":null,"abstract":"Emerging screen technologies, such as Electrophoretic Displays (EPD) used in E-book Readers, are changing product power requirements due to their advantageous properties such as bi-stability (effective \"zero power\" static display) and reflective mode of operation (no backlight). We will first review the emerging screen technologies under the angle of system and IC design impact. We will explain power management consequences for IC design, with a focus on Application Engine SOCs for the wireless/portable markets.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115591942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510288
Dong-Won Kim, K. Yeo, S. Suk, Ming Li, Y. Yeoh, D. Sohn, C. Chung
We have proposed gate-all-around Silicon nanowire MOSFET (SNWFET) on bulk Si as an ultimate transistor. Well controlled processes are used to achieve gate length (LG) of sub-10nm and narrow nanowire widths. Excellent performance with reasonable VTH and short channel immunity are achieved owing to thin nanowire channel, self-aligned gate, and GAA structure. Transistor performance with gate length of 10nm has been demonstrated and nanowire size (DNW) dependency of various electrical characteristics has been investigated. Random telegraph noise (RTN) in SNWFET is studied as well.
{"title":"Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)","authors":"Dong-Won Kim, K. Yeo, S. Suk, Ming Li, Y. Yeoh, D. Sohn, C. Chung","doi":"10.1109/ICICDT.2010.5510288","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510288","url":null,"abstract":"We have proposed gate-all-around Silicon nanowire MOSFET (SNWFET) on bulk Si as an ultimate transistor. Well controlled processes are used to achieve gate length (LG) of sub-10nm and narrow nanowire widths. Excellent performance with reasonable VTH and short channel immunity are achieved owing to thin nanowire channel, self-aligned gate, and GAA structure. Transistor performance with gate length of 10nm has been demonstrated and nanowire size (DNW) dependency of various electrical characteristics has been investigated. Random telegraph noise (RTN) in SNWFET is studied as well.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510291
F. Clermidy, C. Bernard, R. Lemaire, Jérôme Martin, I. Miro-Panadès, Y. Thonnart, P. Vivet, N. Wehn
Chips for digital baseband processing have long been based on simple fixed pipeline structures connecting processing elements. The emergence of complex multi-modes applications like 3GPP-LTE, Software Defined Radio or Cognitive Radio leads to fast handover need between Telecommunication protocols. On one hand, to fulfill these new requirements, more flexible architectures are required. On the other hand, such applications demand more computing performance, and thus power consumption is a concern. In this paper, we present a new chip dedicated to baseband processing. Based on an asynchronous Network-on-Chip and 23 processing units, it delivers 37 GOPS of peak performance. A dynamic reconfiguration management is deployed on the chip for fast handover between modes, with less than 50 µs of full reconfiguration. The asynchronous Network-on-Chip used to communicate allows a complete frequency decoupling between the units. A distributed power management strategy leads to less than 500 mW power consumption in typical use.
{"title":"MAGALI: A Network-on-Chip based multi-core system-on-chip for MIMO 4G SDR","authors":"F. Clermidy, C. Bernard, R. Lemaire, Jérôme Martin, I. Miro-Panadès, Y. Thonnart, P. Vivet, N. Wehn","doi":"10.1109/ICICDT.2010.5510291","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510291","url":null,"abstract":"Chips for digital baseband processing have long been based on simple fixed pipeline structures connecting processing elements. The emergence of complex multi-modes applications like 3GPP-LTE, Software Defined Radio or Cognitive Radio leads to fast handover need between Telecommunication protocols. On one hand, to fulfill these new requirements, more flexible architectures are required. On the other hand, such applications demand more computing performance, and thus power consumption is a concern. In this paper, we present a new chip dedicated to baseband processing. Based on an asynchronous Network-on-Chip and 23 processing units, it delivers 37 GOPS of peak performance. A dynamic reconfiguration management is deployed on the chip for fast handover between modes, with less than 50 µs of full reconfiguration. The asynchronous Network-on-Chip used to communicate allows a complete frequency decoupling between the units. A distributed power management strategy leads to less than 500 mW power consumption in typical use.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114174868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510295
F. Andrieu, O. Weber, S. Baudot, C. Fenouillet-Béranger, O. Rozeau, J. Mazurier, P. Perreau, J. Eymery, O. Faynot
We demonstrate that planar Fully Depleted Silicon-On-Insulator (FDSOI) architectures allow improving the electrostatic control (and in turn the dynamic performance by 22%) and the variability of Complementary Metal-Oxide-Semiconductors (CMOS) devices, compared to the bulk technology. It is thus an ideal solution for Low Power (LP) applications and SRAM stability at the 22nm node and below. Moreover, integrated on both Ultra-Thin Body and Buried oxide (UTB2), it enables the use of standard power management technique (Reverse Back or Source Biasing) with a high efficiency. Finally, some technological options exist in order to boost its ON-state current (ION) like strained SOI substrates for nMOS and embedded SiGe source/drain for pMOS.
{"title":"Fully depleted Silicon-On-Insulator with back bias and strain for low power and high performance applications","authors":"F. Andrieu, O. Weber, S. Baudot, C. Fenouillet-Béranger, O. Rozeau, J. Mazurier, P. Perreau, J. Eymery, O. Faynot","doi":"10.1109/ICICDT.2010.5510295","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510295","url":null,"abstract":"We demonstrate that planar Fully Depleted Silicon-On-Insulator (FDSOI) architectures allow improving the electrostatic control (and in turn the dynamic performance by 22%) and the variability of Complementary Metal-Oxide-Semiconductors (CMOS) devices, compared to the bulk technology. It is thus an ideal solution for Low Power (LP) applications and SRAM stability at the 22nm node and below. Moreover, integrated on both Ultra-Thin Body and Buried oxide (UTB2), it enables the use of standard power management technique (Reverse Back or Source Biasing) with a high efficiency. Finally, some technological options exist in order to boost its ON-state current (ION) like strained SOI substrates for nMOS and embedded SiGe source/drain for pMOS.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123097176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510245
François Belmas, F. Hameau, J. Fournier
In this paper we present a new method for controlling the performance of a Differential Active Inductor (DAI) used as resonating output load of an RF amplifier and working at Ultra Low Power (ULP) consumption. A new solution is proposed for linearity improvement without extra power consumption and without SNR degradation. For a given impedance value at the resonance frequency of the DAI (corresponding to a given amplifier gain), tradeoff between quality factor Q and IIP3 is highlighted. Then, an optimization method is proposed which takes into account the power consumption. A simulated DAI presents -2.7 dBm IIP3, 40nV/Hz noise voltage density and almost 3.0kΩ load at the resonance frequency of 2.45GHz. The total power consumption is 0.8 mW under 1V power supply of a 65nm CMOS technology, and the circuit occupies 0.0012 mm² of silicon area.
{"title":"A new method for performance control of a differential active inductor for low power 2.4GHz applications","authors":"François Belmas, F. Hameau, J. Fournier","doi":"10.1109/ICICDT.2010.5510245","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510245","url":null,"abstract":"In this paper we present a new method for controlling the performance of a Differential Active Inductor (DAI) used as resonating output load of an RF amplifier and working at Ultra Low Power (ULP) consumption. A new solution is proposed for linearity improvement without extra power consumption and without SNR degradation. For a given impedance value at the resonance frequency of the DAI (corresponding to a given amplifier gain), tradeoff between quality factor Q and IIP3 is highlighted. Then, an optimization method is proposed which takes into account the power consumption. A simulated DAI presents -2.7 dBm IIP3, 40nV/Hz noise voltage density and almost 3.0kΩ load at the resonance frequency of 2.45GHz. The total power consumption is 0.8 mW under 1V power supply of a 65nm CMOS technology, and the circuit occupies 0.0012 mm² of silicon area.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115370845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510263
J. Le Coz, A. Valentian, P. Flatresse, M. Belleville
In this paper, several power gating solutions are analysed in 65nm PDSOI technology, taking into account the implementation area. A new figure of merit has been proposed to easily determine the best tradeoff between leakage, drive current and area. It shows that the best solution is to use a Body-Contacted transistor with a non-minimal gate length, enabling leakage currents of the same order of magnitude than in Bulk. A second analysis on specific PD-SOI Logic CORE electrical behaviour has been performed. This analysis allows determining the power switch network sizing implementation taking into account decoupling capacitance, ON Logic CORE current and equivalent parasitic supply inductance.
{"title":"Power switch optimization and sizing in 65nm PD-SOI considering supply voltage noise","authors":"J. Le Coz, A. Valentian, P. Flatresse, M. Belleville","doi":"10.1109/ICICDT.2010.5510263","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510263","url":null,"abstract":"In this paper, several power gating solutions are analysed in 65nm PDSOI technology, taking into account the implementation area. A new figure of merit has been proposed to easily determine the best tradeoff between leakage, drive current and area. It shows that the best solution is to use a Body-Contacted transistor with a non-minimal gate length, enabling leakage currents of the same order of magnitude than in Bulk. A second analysis on specific PD-SOI Logic CORE electrical behaviour has been performed. This analysis allows determining the power switch network sizing implementation taking into account decoupling capacitance, ON Logic CORE current and equivalent parasitic supply inductance.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115588465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510271
Y. Weng, H. Tsai, M. Ker
A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide overstress problem in low-voltage CMOS process. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide reliability problem, the new proposed charge pump circuit is suitable for the applications in low-voltage CMOS IC products.
{"title":"Design of charge pump circuit in low-voltage CMOS process with suppressed return-back leakage current","authors":"Y. Weng, H. Tsai, M. Ker","doi":"10.1109/ICICDT.2010.5510271","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510271","url":null,"abstract":"A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide overstress problem in low-voltage CMOS process. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide reliability problem, the new proposed charge pump circuit is suitable for the applications in low-voltage CMOS IC products.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129578739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510289
Nabila Moubdi, P. Maurine, Robin Wilson, N. Azémard, S. Engels, L. Rolíndez, V. Heinrich
This paper aims at introducing a safe voltage scaling and body biasing methodology for Low-Density Parity Check (LDPC) hard-wired IP. The proposed methodology allows an efficient post-silicon tuning of the LDPC, and the performances can be adapted to High Speed mode, or Low Operating Power mode, or Low Standby Power mode requirements. Concrete 45nm silicon results are introduced in this paper to demonstrate the added value of the methodology. More precisely, it is shown that running the High Performance mode leads to +24% on circuit maximum operating frequency. And the Low Standby Power mode results on x0.73 leakage minimization. The proposed adaptive LDPC encoder/decoder can remove some barriers to the adoption of long LDPC codes on portable devices.
{"title":"Voltage scaling and body biasing methodology for high performance hardwired LDPC","authors":"Nabila Moubdi, P. Maurine, Robin Wilson, N. Azémard, S. Engels, L. Rolíndez, V. Heinrich","doi":"10.1109/ICICDT.2010.5510289","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510289","url":null,"abstract":"This paper aims at introducing a safe voltage scaling and body biasing methodology for Low-Density Parity Check (LDPC) hard-wired IP. The proposed methodology allows an efficient post-silicon tuning of the LDPC, and the performances can be adapted to High Speed mode, or Low Operating Power mode, or Low Standby Power mode requirements. Concrete 45nm silicon results are introduced in this paper to demonstrate the added value of the methodology. More precisely, it is shown that running the High Performance mode leads to +24% on circuit maximum operating frequency. And the Low Standby Power mode results on x0.73 leakage minimization. The proposed adaptive LDPC encoder/decoder can remove some barriers to the adoption of long LDPC codes on portable devices.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128936236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510277
Zeqin Wu, P. Maurine, N. Azémard, G. Ducharme
Statistical Static Timing Analysis (SSTA) is becoming necessary, but has not been widely adopted due to various weaknesses. In this paper, we address one of the challenging problems in SSTA: computation of correlations between cell delays. With the help of conditional moments, cell-to-cell and path-to-path delay correlations are computed by propagating iteratively means and variances of cell delays. This technique of computation allows considering the effects of cell topology, input slope and output load values. Numerical results are presented to quantify its accuracy.
{"title":"Computing delay correlations in SSTA","authors":"Zeqin Wu, P. Maurine, N. Azémard, G. Ducharme","doi":"10.1109/ICICDT.2010.5510277","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510277","url":null,"abstract":"Statistical Static Timing Analysis (SSTA) is becoming necessary, but has not been widely adopted due to various weaknesses. In this paper, we address one of the challenging problems in SSTA: computation of correlations between cell delays. With the help of conditional moments, cell-to-cell and path-to-path delay correlations are computed by propagating iteratively means and variances of cell delays. This technique of computation allows considering the effects of cell topology, input slope and output load values. Numerical results are presented to quantify its accuracy.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122935057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510261
X. Jehl, M. Sanquer
Large scale production of single-electron transistors (SETs) is now possible with a standard fully-depleted SOI process. Although the operating temperature is limited to approximately 10 K for now, this opens new opportunities for implementing on-chip hybrid designs combining the benefits of Coulomb blockade with regular FET-based electronics. Moreover, the continuous shrinking of CMOS devices tends to bridge the gap between FETs and SETs, because of a necessary compromise between switching energy and switching speed. Devices designed for very low power applications will naturally feature Coulomb blockade at moderate temperature, as a result of very small dimensions and underlapped geometry. A promising outcome is the possibility to drive such devices at high frequency, as embedded FET-based electronics can be designed in very close vicinity of the SET. In parallel with our mainstream microelectronics approach, several groups have recently made significant advances towards high temperature (above 77 K) silicon based SETs. In this article we summarize the basic characteristics and behaviour of our MOS-SET design, its charge sensitivity and its remarkable long term stability and the coupling between several MOS-SETs associated in series.
{"title":"Progress on single-electron transistors","authors":"X. Jehl, M. Sanquer","doi":"10.1109/ICICDT.2010.5510261","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510261","url":null,"abstract":"Large scale production of single-electron transistors (SETs) is now possible with a standard fully-depleted SOI process. Although the operating temperature is limited to approximately 10 K for now, this opens new opportunities for implementing on-chip hybrid designs combining the benefits of Coulomb blockade with regular FET-based electronics. Moreover, the continuous shrinking of CMOS devices tends to bridge the gap between FETs and SETs, because of a necessary compromise between switching energy and switching speed. Devices designed for very low power applications will naturally feature Coulomb blockade at moderate temperature, as a result of very small dimensions and underlapped geometry. A promising outcome is the possibility to drive such devices at high frequency, as embedded FET-based electronics can be designed in very close vicinity of the SET. In parallel with our mainstream microelectronics approach, several groups have recently made significant advances towards high temperature (above 77 K) silicon based SETs. In this article we summarize the basic characteristics and behaviour of our MOS-SET design, its charge sensitivity and its remarkable long term stability and the coupling between several MOS-SETs associated in series.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130675247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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