Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510251
L. Gallin-Martel, D. Dzahini, F. Rarbi, O. Rossetto
The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to the calibration. We present a 14 bit DAC, designed in a CMOS 0.35 µm process and based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. This DAC features an INL lower than 0.5 LSB at 5 MHz, and dissipates less than 7 mW.
{"title":"A low power 5 MS/s 14 bit switched capacitors digital to analog converter","authors":"L. Gallin-Martel, D. Dzahini, F. Rarbi, O. Rossetto","doi":"10.1109/ICICDT.2010.5510251","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510251","url":null,"abstract":"The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to the calibration. We present a 14 bit DAC, designed in a CMOS 0.35 µm process and based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. This DAC features an INL lower than 0.5 LSB at 5 MHz, and dissipates less than 7 mW.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127018883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510750
C. Augustine, Xuanyao Fong, K. Roy
Transistor scaling has enabled more memory to be embedded on-chip to accelerate large scale applications. However, increased leakage current in scaled technologies resulted in higher standby power consumption in volatile memories. Nonvolatile memories have been researched and developed as solutions to these problems. However, non-volatile memories such as Flash or magnetic spin torque memories require large drive currents. On the other hand, ferroelectric capacitors take advantage of non-linear capacitance to store data and are compatible with CMOS fabrication process. Furthermore, dual ferroelectric capacitor (DFeCAP) architecture was developed to implement low-power logic/memory functional units. This paper evaluates a TAG RAM implementation based on DFeCAP architecture using a generic, HSPICE compatible ferroelectric capacitor model. The paper also discusses the impact of parametric process variations on the performance of DFeCAP cell and proposes design methodologies to achieve variation-tolerance. Our simulations demonstrate that compared to 130nm CMOS implementation, the ferroelectric memory architecture is 97% better in terms of power and 37% better in terms of area.
{"title":"Dual ferroelectric capacitor architecture and its application to TAG RAM","authors":"C. Augustine, Xuanyao Fong, K. Roy","doi":"10.1109/ICICDT.2010.5510750","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510750","url":null,"abstract":"Transistor scaling has enabled more memory to be embedded on-chip to accelerate large scale applications. However, increased leakage current in scaled technologies resulted in higher standby power consumption in volatile memories. Nonvolatile memories have been researched and developed as solutions to these problems. However, non-volatile memories such as Flash or magnetic spin torque memories require large drive currents. On the other hand, ferroelectric capacitors take advantage of non-linear capacitance to store data and are compatible with CMOS fabrication process. Furthermore, dual ferroelectric capacitor (DFeCAP) architecture was developed to implement low-power logic/memory functional units. This paper evaluates a TAG RAM implementation based on DFeCAP architecture using a generic, HSPICE compatible ferroelectric capacitor model. The paper also discusses the impact of parametric process variations on the performance of DFeCAP cell and proposes design methodologies to achieve variation-tolerance. Our simulations demonstrate that compared to 130nm CMOS implementation, the ferroelectric memory architecture is 97% better in terms of power and 37% better in terms of area.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125198507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510250
S. Martinie, S. Uznanski, J. Autran, P. Roche, G. Gasiot, D. Munteanu, S. Sauze, P. Loaiza, G. Warot, M. Zampaolo
This work reports a long-duration (> 2 years) realtime characterization study of SRAM memories at the underground laboratory of Modane (LSM) to quantify alphaemitter radioactive impurities present in the circuit materials and responsible of soft-errors detected in absence of atmospheric neutrons. Experimental data have been obtained using ∼3.5 Gbit of SRAMs manufactured in CMOS 130 nm technology. In a second part of this work, the underground experiment is simulated using a Monte-Carlo code to extract the contamination level related to the disintegration chain of uranium in silicon at secular equilibrium. Results are finally compared to data obtained from experimental counting experiments using an ultra low background alpha-particle gas proportional counter.
{"title":"Alpha-emitter induced soft-errors in CMOS 130nm SRAM: Real-time underground experiment and Monte-Carlo simulation","authors":"S. Martinie, S. Uznanski, J. Autran, P. Roche, G. Gasiot, D. Munteanu, S. Sauze, P. Loaiza, G. Warot, M. Zampaolo","doi":"10.1109/ICICDT.2010.5510250","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510250","url":null,"abstract":"This work reports a long-duration (> 2 years) realtime characterization study of SRAM memories at the underground laboratory of Modane (LSM) to quantify alphaemitter radioactive impurities present in the circuit materials and responsible of soft-errors detected in absence of atmospheric neutrons. Experimental data have been obtained using ∼3.5 Gbit of SRAMs manufactured in CMOS 130 nm technology. In a second part of this work, the underground experiment is simulated using a Monte-Carlo code to extract the contamination level related to the disintegration chain of uranium in silicon at secular equilibrium. Results are finally compared to data obtained from experimental counting experiments using an ultra low background alpha-particle gas proportional counter.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121821554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510301
D. Linten, S. Thijs, G. Groeseneken
Providing ESD protection for wideband RF CMOS LNAs is a challenging task: it requires both ESD and RF design skills in order to achieve high ESD robustness, while maintaining the overall RF performance. In this paper, an overview of the different wideband RF ESD protection strategies used in the literature is presented.
{"title":"ESD protection for wideband RF CMOS LNAs","authors":"D. Linten, S. Thijs, G. Groeseneken","doi":"10.1109/ICICDT.2010.5510301","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510301","url":null,"abstract":"Providing ESD protection for wideband RF CMOS LNAs is a challenging task: it requires both ESD and RF design skills in order to achieve high ESD robustness, while maintaining the overall RF performance. In this paper, an overview of the different wideband RF ESD protection strategies used in the literature is presented.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122439447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510246
E. Monaco, M. Pozzoni, F. Svelto, A. Mazzanti
A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.
{"title":"A 6mW, 115GHz CMOS injection-locked frequency doubler with differential output","authors":"E. Monaco, M. Pozzoni, F. Svelto, A. Mazzanti","doi":"10.1109/ICICDT.2010.5510246","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510246","url":null,"abstract":"A millimeter-wave CMOS frequency multiplier by two (doubler) is reported. The circuit consists of a Pierce oscillator injection-locked by a push-push pair. Compared to traditional frequency multipliers, which exploit the non-linearity of active devices to produce harmonics of the input signal, this technique provides a differential output with balanced signals, low core power dissipation and large swing. A model of the circuit is proposed to derive a closed form expression for the frequency locking range. Prototypes of the frequency doubler have been realized in a 65nm CMOS technology, show an operation bandwidth from 106GHz to 128GHz, with 6mW core power dissipation. With 0dBm input power, the output peak voltage swing, is 330mV, at 115GHz.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"156 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128763424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510298
Yi-Hsuan Chiu, Yi-Bo Liao, M. Chiang, C. Lin, W. Hsu, P. Chiang, Y. Hsu, Wenhsing Liu, S. Sheu, K. Su, M. Kao, M. Tsai
Design issues and insights of multilevel phase change memory are presented. Based on a proposed compact model calibrated to measured data, we assess the impact of resistance drift on multilevel cell design. It is found that special care has to be taken to develop a viable multilevel design as the design window could be degraded and worsened at high temperature.
{"title":"Impact of resistance drift on multilevel PCM design","authors":"Yi-Hsuan Chiu, Yi-Bo Liao, M. Chiang, C. Lin, W. Hsu, P. Chiang, Y. Hsu, Wenhsing Liu, S. Sheu, K. Su, M. Kao, M. Tsai","doi":"10.1109/ICICDT.2010.5510298","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510298","url":null,"abstract":"Design issues and insights of multilevel phase change memory are presented. Based on a proposed compact model calibrated to measured data, we assess the impact of resistance drift on multilevel cell design. It is found that special care has to be taken to develop a viable multilevel design as the design window could be degraded and worsened at high temperature.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131010367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510290
Chua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu
A 1.0 V to 1.8 V mixed-voltage I/O buffer implemented with 90-nm 1-V standard CMOS devices is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 2×VDD voltage level signal without any gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to be 340 MHz and 450 MHz for 1.8 V and 1.0 V, respectively, with a given capacitive load of 20 pF.
{"title":"450 MHz 1.0 V to 1.8 V bidirectional mixed-voltage I/O buffer using 90-nm process","authors":"Chua-Chin Wang, Ron-Chi Kuo, Jen-Wei Liu","doi":"10.1109/ICICDT.2010.5510290","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510290","url":null,"abstract":"A 1.0 V to 1.8 V mixed-voltage I/O buffer implemented with 90-nm 1-V standard CMOS devices is proposed. By using a dynamic gate bias generator to provide appropriate gate drive voltages for the output stage, the I/O buffer can transmit 2×VDD voltage level signal without any gate-oxide overstress hazard. Besides, the leakage current is eliminated by adopting a floating N-well circuit. The maximum data rate is simulated to be 340 MHz and 450 MHz for 1.8 V and 1.0 V, respectively, with a given capacitive load of 20 pF.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132381256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510278
Hao-I Yang, C. Chuang, W. Hwang
The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gateoxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.
{"title":"Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM","authors":"Hao-I Yang, C. Chuang, W. Hwang","doi":"10.1109/ICICDT.2010.5510278","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510278","url":null,"abstract":"The gate-oxide breakdowns (BD) of the power-switches have severe and even detrimental effects on the margin, stability, and performance of the power-gated SRAM. This paper proposes and evaluates several techniques to mitigate the power-switch gate-oxide BD, including adding a gate series resistance to the power switch, dual threshold voltage power switch, thick gate-oxide power switch, and dual gateoxide thickness power switch. It is shown that dual gate-oxide thickness power switch improves the time-to-dielectric-breakdown of the power switch while maintaining the performance without side effect.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134021573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510283
M. Sadaka, I. Radu, L. Di Cioccio
The microelectronic industry has arrived at a crossroads. There is the challenge of continued Moore's Law scaling and the ever-growing consumer demand for smaller, faster electronics with extended and new functionalities. 3D integration is a promising and fast-growing field that addresses the convergence of Moore's Law and more than Moore. 3D integration offers a path for higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction. Through this emerging field, new and improved technologies and integration schemes will be necessary to meet the associated manufacturing challenges; this paper describes the advantages of 3D integration, enabling technologies & the driver applications.
{"title":"3D integration: Advantages, enabling technologies & applications","authors":"M. Sadaka, I. Radu, L. Di Cioccio","doi":"10.1109/ICICDT.2010.5510283","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510283","url":null,"abstract":"The microelectronic industry has arrived at a crossroads. There is the challenge of continued Moore's Law scaling and the ever-growing consumer demand for smaller, faster electronics with extended and new functionalities. 3D integration is a promising and fast-growing field that addresses the convergence of Moore's Law and more than Moore. 3D integration offers a path for higher performance, higher density, higher functionality, smaller form factor, and potential cost reduction. Through this emerging field, new and improved technologies and integration schemes will be necessary to meet the associated manufacturing challenges; this paper describes the advantages of 3D integration, enabling technologies & the driver applications.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122614451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510285
J. Ackaert, B. Greenwood
ESD problems are commonly thought to be an electrostatic discharge event through the device pins. All known models like HBM, MM, CDM are based on this assumption. During assembly discharge into devices, directly into the surface is also well known. Pad – related, ESD protective structures are useless against this ESD-surface-discharge-path, called ESDFOS [1]. Little is known however on the impact of simple wafer cleaning/spraying as used frequently during the wafer manufacturing itself. In many cases these processes do include high risks of generating electrostatic charge; subsequent discharge into devices and can easily induce ESD-like events internally in the interconnect circuitry of a device. In this paper, charging induced damage (CID) into common metal interconnect is reported. The damage is caused by the build up of charges on a resist surface during a water rinsing step. This charging is inducing a mirror charge on the interconnect circuitry and results in a discharge through the inter metal dielectric layer (IMD) towards a grounded structure. This CID can lead to direct severe yield loss. In milder cases the damage is difficult to detect but is proven to result in reliability issues. The charging has been detected, measured and evaluated with the help of a non contact surface potential measurement. The phenomena has been characterized and quantified. This paper is describing the occurrence of the failures, the design of the test structures, the measurement results. This work is concluding on how a design can be made safe from ESDFOS during processing by applying the popper layout rules.
{"title":"Design solutions for preventing process induced ESD damage during manufacturing of interconnects","authors":"J. Ackaert, B. Greenwood","doi":"10.1109/ICICDT.2010.5510285","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510285","url":null,"abstract":"ESD problems are commonly thought to be an electrostatic discharge event through the device pins. All known models like HBM, MM, CDM are based on this assumption. During assembly discharge into devices, directly into the surface is also well known. Pad – related, ESD protective structures are useless against this ESD-surface-discharge-path, called ESDFOS [1]. Little is known however on the impact of simple wafer cleaning/spraying as used frequently during the wafer manufacturing itself. In many cases these processes do include high risks of generating electrostatic charge; subsequent discharge into devices and can easily induce ESD-like events internally in the interconnect circuitry of a device. In this paper, charging induced damage (CID) into common metal interconnect is reported. The damage is caused by the build up of charges on a resist surface during a water rinsing step. This charging is inducing a mirror charge on the interconnect circuitry and results in a discharge through the inter metal dielectric layer (IMD) towards a grounded structure. This CID can lead to direct severe yield loss. In milder cases the damage is difficult to detect but is proven to result in reliability issues. The charging has been detected, measured and evaluated with the help of a non contact surface potential measurement. The phenomena has been characterized and quantified. This paper is describing the occurrence of the failures, the design of the test structures, the measurement results. This work is concluding on how a design can be made safe from ESDFOS during processing by applying the popper layout rules.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127756916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：