Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510286
D. Wendel, R. Kalla, J. Friedrich, J. Kahle, J. Leenstra, C. Lichtenau, B. Sinharoy, William J. Starke, V. Zyuban
Introducing POWER7TM the latest member of the IBM POWERTM processor family. A 567mm² chip implemented in 45nm SOI technology, holding eight quad threaded cores, a 32MB shared eDRAM L3, two memory controllers and high bandwidth SMP interfaces. The new out of order, shallow pipeline core with 12 execution units, multiport L1 caches and a private 256kB L2 offers the efficiency to support 4x the number of cores within the same power envelope as its predecessor. Supporting over 4GHz, the L1 data cache loop is kept to 2 cycles. Data from the L2 can be returned to the core at a rate of 32B per cycle.
{"title":"The power7TM processor SoC","authors":"D. Wendel, R. Kalla, J. Friedrich, J. Kahle, J. Leenstra, C. Lichtenau, B. Sinharoy, William J. Starke, V. Zyuban","doi":"10.1109/ICICDT.2010.5510286","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510286","url":null,"abstract":"Introducing POWER7TM the latest member of the IBM POWERTM processor family. A 567mm² chip implemented in 45nm SOI technology, holding eight quad threaded cores, a 32MB shared eDRAM L3, two memory controllers and high bandwidth SMP interfaces. The new out of order, shallow pipeline core with 12 execution units, multiport L1 caches and a private 256kB L2 offers the efficiency to support 4x the number of cores within the same power envelope as its predecessor. Supporting over 4GHz, the L1 data cache loop is kept to 2 cycles. Data from the L2 can be returned to the core at a rate of 32B per cycle.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129012604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510287
X. Garros, M. Cassé, G. Reimbold, F. Martin, L. Brunet, F. Andrieu, F. Boulanger
The paper presents an overview of the Bias Temperature Instabilities (BTI) reliability in High-k/Metal gate technologies. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.
{"title":"Reliability concerns in High-K/Metal gate technologies","authors":"X. Garros, M. Cassé, G. Reimbold, F. Martin, L. Brunet, F. Andrieu, F. Boulanger","doi":"10.1109/ICICDT.2010.5510287","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510287","url":null,"abstract":"The paper presents an overview of the Bias Temperature Instabilities (BTI) reliability in High-k/Metal gate technologies. We show that mobility performance and NBTI reliability are strongly correlated and that they are affected by the diffusion of nitrogen species N at the Si interface. PBTI, more sensitive to bulk oxide traps, is strongly reduced in very thin dielectric films. Reducing the metal gate thickness favors the reduction of mobility degradations and NBTI, but, also strongly enhances PBTI, due to a complex set of reactions in the gate oxide. Trade off must be found to obtain a great trade off between device performance and reliability requirements.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116704056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510282
Motoyuki Sato, Jun Chen, T. Sekiguchi, T. Chikyow, J. Yugami, K. Ikeda, Y. Ohji
Microscopical investigation of leakage behaviors of Hf-based high-k gate stacks was achieved by means of electron-beam-induced current (EBIC) method. With this method, we could observe the pre-existing and stress induced defect in high-k. This pre-existing defect affect on MOSFET characteristics. We investigated in detail the relationship between the defect (in bulk high-k and interface) and 1/f noise on (110) and (100) substrates. The 1/f noise is strongly related to the degradation in the hole mobility due to the pre-existing defect or process integration damage. On the other hand, the 1/f noise of nMOSFETs is rerated to interface defects rather than electron mobility degradation.
{"title":"Pre-existing and process induced defects in high-k gate dielectrics ∼direct observation with EBIC and impact on 1/f noise∼","authors":"Motoyuki Sato, Jun Chen, T. Sekiguchi, T. Chikyow, J. Yugami, K. Ikeda, Y. Ohji","doi":"10.1109/ICICDT.2010.5510282","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510282","url":null,"abstract":"Microscopical investigation of leakage behaviors of Hf-based high-k gate stacks was achieved by means of electron-beam-induced current (EBIC) method. With this method, we could observe the pre-existing and stress induced defect in high-k. This pre-existing defect affect on MOSFET characteristics. We investigated in detail the relationship between the defect (in bulk high-k and interface) and 1/f noise on (110) and (100) substrates. The 1/f noise is strongly related to the degradation in the hole mobility due to the pre-existing defect or process integration damage. On the other hand, the 1/f noise of nMOSFETs is rerated to interface defects rather than electron mobility degradation.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125981854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510266
M. Nongaillard, B. Allard, S. Jacqueline
The use of integrated passive components in circuit design and the reliability of this type of circuits are scarcely covered in literature. The fabrication of high-density passive components generates stress in the silicon wafer and the manufacturing reliability of the passive chips is an important issue. The reliability is assessed using various accelerating tests including humidity and thermal stress. Solving the reliability issue calls for process-based actions and desgin-based actions, namely Design-for-Manufacturing. The paper introduces a Design-for-Manufacturing method called stress-relief method. The objective is to increase the design robustness against thermal cycling test. The stress-relief uses sacrificial structures. Various options are detailed in the paper and their respective efficiency is compared with experimental passive thermal cycling. The method does not need any process modification and the required silicon area is small.
{"title":"Design approach to improve thermo-mechanical reliability for high-integrated passive circuits","authors":"M. Nongaillard, B. Allard, S. Jacqueline","doi":"10.1109/ICICDT.2010.5510266","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510266","url":null,"abstract":"The use of integrated passive components in circuit design and the reliability of this type of circuits are scarcely covered in literature. The fabrication of high-density passive components generates stress in the silicon wafer and the manufacturing reliability of the passive chips is an important issue. The reliability is assessed using various accelerating tests including humidity and thermal stress. Solving the reliability issue calls for process-based actions and desgin-based actions, namely Design-for-Manufacturing. The paper introduces a Design-for-Manufacturing method called stress-relief method. The objective is to increase the design robustness against thermal cycling test. The stress-relief uses sacrificial structures. Various options are detailed in the paper and their respective efficiency is compared with experimental passive thermal cycling. The method does not need any process modification and the required silicon area is small.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127194743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510248
F. Vecchi, S. Bozzola, M. Pozzoni, D. Guermandi, E. Temporiti, M. Repossi, U. Decanis, A. Mazzanti, F. Svelto
This paper presents a wide-band fully integrated receiver for Gbit/s connectivity at mm-waves comprising LNA, RF mixer, quadrature IF mixers, local oscillator (LO), in 65 nm CMOS. The architecture choice is key to meet LO requirements at low power dissipation. We have selected a sliding IF architecture, where the IF frequency, set to 1/3 the RF frequency, slides according to the received frequency. The VCO at 2/3 the RF frequency provides the reference for the first down-conversion and drives two injection locked dividers delivering LO signals for quadrature IF mixing. A Phase Noise of -115 dBc/Hz @ 10 MHz offset from an equivalent 60GHz carrier is achieved with 12.6% frequency tuning range. Coupled interstage resonators are introduced in the low-noise amplifier to extend considerably the gain bandwidth product, leading to more than 13GHz bandwidth with 26dB LNA gain. Selection of the architecture and design of building blocks are discussed in details. Realized prototypes of the receiver show a conversion gain of 35dB, 13GHz RF input bandwidth and noise figure below 6dB with a power dissipation, including LO generation, of 75mW only.
{"title":"A 60GHz receiver with 13GHz bandwidth for Gbit/s wireless links in 65nm CMOS","authors":"F. Vecchi, S. Bozzola, M. Pozzoni, D. Guermandi, E. Temporiti, M. Repossi, U. Decanis, A. Mazzanti, F. Svelto","doi":"10.1109/ICICDT.2010.5510248","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510248","url":null,"abstract":"This paper presents a wide-band fully integrated receiver for Gbit/s connectivity at mm-waves comprising LNA, RF mixer, quadrature IF mixers, local oscillator (LO), in 65 nm CMOS. The architecture choice is key to meet LO requirements at low power dissipation. We have selected a sliding IF architecture, where the IF frequency, set to 1/3 the RF frequency, slides according to the received frequency. The VCO at 2/3 the RF frequency provides the reference for the first down-conversion and drives two injection locked dividers delivering LO signals for quadrature IF mixing. A Phase Noise of -115 dBc/Hz @ 10 MHz offset from an equivalent 60GHz carrier is achieved with 12.6% frequency tuning range. Coupled interstage resonators are introduced in the low-noise amplifier to extend considerably the gain bandwidth product, leading to more than 13GHz bandwidth with 26dB LNA gain. Selection of the architecture and design of building blocks are discussed in details. Realized prototypes of the receiver show a conversion gain of 35dB, 13GHz RF input bandwidth and noise figure below 6dB with a power dissipation, including LO generation, of 75mW only.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new transient detection circuit against electrical fast transient (EFT) disturbance is proposed for display panel protection. The circuit function to detect positive or negative electrical transients under EFT tests has been investigated in HSPICE simulation and verified in silicon chip. The output of the proposed transient detection circuit can be used as a firmware index to execute system automatic recovery operation. With hardware/firmware co-design, the immunity of display panel against transient disturbance under EFT tests can be significantly improved.
{"title":"New transient detection circuit for electrical fast transient (EFT) protection design in display panels","authors":"M. Ker, Wan-Yen Lin, Cheng-Cheng Yen, Che-Ming Yang, Tung-Yang Chen, Shih-Fan Chen","doi":"10.1109/ICICDT.2010.5510297","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510297","url":null,"abstract":"A new transient detection circuit against electrical fast transient (EFT) disturbance is proposed for display panel protection. The circuit function to detect positive or negative electrical transients under EFT tests has been investigated in HSPICE simulation and verified in silicon chip. The output of the proposed transient detection circuit can be used as a firmware index to execute system automatic recovery operation. With hardware/firmware co-design, the immunity of display panel against transient disturbance under EFT tests can be significantly improved.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129651487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510249
Xiaowei He, Jinwen Li, Minxuan Zhang, Shubo Qi
In this paper, a 2mm-long linear on-chip dipole antenna pair on Si substrate is analyzed and simulated to investigate the transmission characteristics using Ansoft's HFSS. By inserting a 0.35mm thick diamond layer between substrate and heat sink, the obtained transmission gain of antenna pair with 1mm separation on 10 Ohm-cm Si substrate increases by 9dB at 20GHz. The effect of the dielectric materials, diamond thickness, substrate resistivity and the separation of an antenna pair on the transmission gain has been investigated. The results indicate that thinner diamond layer along with high resistivity substrate is preferred. A modified propagation model involving a diamond layer is also evaluated to make antenna performance predictable in real wireless interconnection systems.
{"title":"Improvement of integrated dipole antenna performance using diamond for intra-chip wireless interconnection","authors":"Xiaowei He, Jinwen Li, Minxuan Zhang, Shubo Qi","doi":"10.1109/ICICDT.2010.5510249","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510249","url":null,"abstract":"In this paper, a 2mm-long linear on-chip dipole antenna pair on Si substrate is analyzed and simulated to investigate the transmission characteristics using Ansoft's HFSS. By inserting a 0.35mm thick diamond layer between substrate and heat sink, the obtained transmission gain of antenna pair with 1mm separation on 10 Ohm-cm Si substrate increases by 9dB at 20GHz. The effect of the dielectric materials, diamond thickness, substrate resistivity and the separation of an antenna pair on the transmission gain has been investigated. The results indicate that thinner diamond layer along with high resistivity substrate is preferred. A modified propagation model involving a diamond layer is also evaluated to make antenna performance predictable in real wireless interconnection systems.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"29 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114086269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510254
Iman Madadi, H. Aghababa, B. Forouzandeh
In future technologies, people will confront with traditional Cu interconnect problems and there is a widespread demand for single-walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). One of the most important parts in carbon nanotube interconnects is their impedance. Thus we investigate impedance, especially dc resistance, in multi walled carbon nano tube interconnect in low and high bias voltages for different geometries. The total dc resistance of an MWCNT is then calculated and an equation was obtained. We have also investigated the behavior of MWCNTs, in both low and high damping modes, in high bias regime. The results for delay and power showed better performance for MWCNT's interconnect compared to those for Cu's
{"title":"Multi-walled carbon nanotube impedance","authors":"Iman Madadi, H. Aghababa, B. Forouzandeh","doi":"10.1109/ICICDT.2010.5510254","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510254","url":null,"abstract":"In future technologies, people will confront with traditional Cu interconnect problems and there is a widespread demand for single-walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). One of the most important parts in carbon nanotube interconnects is their impedance. Thus we investigate impedance, especially dc resistance, in multi walled carbon nano tube interconnect in low and high bias voltages for different geometries. The total dc resistance of an MWCNT is then calculated and an equation was obtained. We have also investigated the behavior of MWCNTs, in both low and high damping modes, in high bias regime. The results for delay and power showed better performance for MWCNT's interconnect compared to those for Cu's","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125067987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510265
A. Sathanur, M. Ashouei, J. Huisken
Power gating (PG) has emerged as an effective technique to reduce standby leakage power in portable devices where battery life time is vital. However, it comes at the cost of timing overhead which is a problem for most of the applications where real-time constraints exist. Designing efficient power gated circuits is very challenging problem due to contrasting requirements in active mode (low timing overhead implying larger power switch size) and standby mode (low standby leakage power implying smaller power switch size). In this work, we show that applying Forward Body Biasing (FBB) to the logic gates in conjunction with power gating (PG + FBB) will provide us with an additional degree of freedom which can be utilized to improve the efficiency of the power gated circuit. We propose an optimization algorithm to find the optimum power switch size and FBB value such that total leakage energy of the design (active + standby) in minimized. Results show that our PG + FBB technique on an average improves the leakage energy savings by 2X-5X as compared to using only power gating. With PG + FBB technique, one can also design a zero delay penalty power gated circuit which is not possible if only power gating is used.
{"title":"Improving efficiency of power gated circuits through concurrent optimization of power switch size and forward body biasing","authors":"A. Sathanur, M. Ashouei, J. Huisken","doi":"10.1109/ICICDT.2010.5510265","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510265","url":null,"abstract":"Power gating (PG) has emerged as an effective technique to reduce standby leakage power in portable devices where battery life time is vital. However, it comes at the cost of timing overhead which is a problem for most of the applications where real-time constraints exist. Designing efficient power gated circuits is very challenging problem due to contrasting requirements in active mode (low timing overhead implying larger power switch size) and standby mode (low standby leakage power implying smaller power switch size). In this work, we show that applying Forward Body Biasing (FBB) to the logic gates in conjunction with power gating (PG + FBB) will provide us with an additional degree of freedom which can be utilized to improve the efficiency of the power gated circuit. We propose an optimization algorithm to find the optimum power switch size and FBB value such that total leakage energy of the design (active + standby) in minimized. Results show that our PG + FBB technique on an average improves the leakage energy savings by 2X-5X as compared to using only power gating. With PG + FBB technique, one can also design a zero delay penalty power gated circuit which is not possible if only power gating is used.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130082926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-02DOI: 10.1109/ICICDT.2010.5510292
P. Galy, J. Bourgeat, J. Jimenez, C. Entringer, A. Dray, B. Jacquier
The Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to the technology scaling down. The main purpose of this paper is to present and compare silicon results in C45nm CMOS technology of a single pitch ESD protection using isolated Silicon Controlled Rectifier (SCR) and dual isolated SCR. These two protection structures with dynamic trigger circuit will be compared. Also, the power pad clamps in 1 pitch IO are qualified through 100ns TLP. Silicon result show that ESD robustness reaches 4kV HBM, 200V MM and 500V CDM for a 64 BGA package. IO power pads are also immune to Latch Up and power sequence.
{"title":"Comparison between isolated SCR & embedded dual isolated SCR power devices for ESD power clamp in C45nm CMOS technology","authors":"P. Galy, J. Bourgeat, J. Jimenez, C. Entringer, A. Dray, B. Jacquier","doi":"10.1109/ICICDT.2010.5510292","DOIUrl":"https://doi.org/10.1109/ICICDT.2010.5510292","url":null,"abstract":"The Electrostatic Discharge (ESD) protection for advanced CMOS technologies is a challenge due to the technology scaling down. The main purpose of this paper is to present and compare silicon results in C45nm CMOS technology of a single pitch ESD protection using isolated Silicon Controlled Rectifier (SCR) and dual isolated SCR. These two protection structures with dynamic trigger circuit will be compared. Also, the power pad clamps in 1 pitch IO are qualified through 100ns TLP. Silicon result show that ESD robustness reaches 4kV HBM, 200V MM and 500V CDM for a 64 BGA package. IO power pads are also immune to Latch Up and power sequence.","PeriodicalId":187361,"journal":{"name":"2010 IEEE International Conference on Integrated Circuit Design and Technology","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122649238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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