Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116290
Andres F. Gomez, L. Poehls, F. Vargas, V. Champac
This paper proposes an early resilience methodology to identify circuit output nodes where aging sensors should be inserted for an error prediction framework. The methodology is based in a pre-layout statistical estimation of the signal paths likely to become critical due to NBTI and/or Process Variations. To handle the fact that spatial correlation information is not available at early steps of the design flow, a statistical approach maximizing critical paths coverage is proposed. The results obtained with the early prediction methodology are compared with those obtained with spatial correlation information. The proposed methodology provides a good prediction of the set of critical paths to be monitored. Furthermore, location and number of aging sensors required to be inserted at critical paths output nodes are closely predicted.
{"title":"An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging","authors":"Andres F. Gomez, L. Poehls, F. Vargas, V. Champac","doi":"10.1109/VTS.2015.7116290","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116290","url":null,"abstract":"This paper proposes an early resilience methodology to identify circuit output nodes where aging sensors should be inserted for an error prediction framework. The methodology is based in a pre-layout statistical estimation of the signal paths likely to become critical due to NBTI and/or Process Variations. To handle the fact that spatial correlation information is not available at early steps of the design flow, a statistical approach maximizing critical paths coverage is proposed. The results obtained with the early prediction methodology are compared with those obtained with spatial correlation information. The proposed methodology provides a good prediction of the set of critical paths to be monitored. Furthermore, location and number of aging sensors required to be inserted at critical paths output nodes are closely predicted.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115138369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116272
M. E. Amyeen
This talk focuses on test and debug challenges that are unique to large die products. A technical review of problems being faced today specific to test quality, test time, test cost, electrical and speed content, and debug will be outlined along with some current solutions being pursued to drive large die products to production quality. The talk concludes with a discussion about new solutions and areas of innovation that will be necessary to keep future generations of these products manufacturable, and on a cadence that meets the stringent time to market requirements.
{"title":"Innovative practices session 5C: Advancements in test -keeping moore moving!","authors":"M. E. Amyeen","doi":"10.1109/VTS.2015.7116272","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116272","url":null,"abstract":"This talk focuses on test and debug challenges that are unique to large die products. A technical review of problems being faced today specific to test quality, test time, test cost, electrical and speed content, and debug will be outlined along with some current solutions being pursued to drive large die products to production quality. The talk concludes with a discussion about new solutions and areas of innovation that will be necessary to keep future generations of these products manufacturable, and on a cadence that meets the stringent time to market requirements.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129708513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116296
D. Erb, Karsten Scheibler, M. Sauer, S. Reddy, B. Becker
Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Generating tests to detect such defects is challenging due to the need to accurately determine the coupling capacitances between the open net and its aggressors and fix the state of these aggressors during test. Process variations cause deviations from assumed values of circuit parameters thus potentially invalidating tests generated with assumed circuit parameters. Additionally, recent investigation using test chips showed that the steady state voltage on open nets may drift slowly with the application of circuit inputs and can be different at different nets.
{"title":"Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects","authors":"D. Erb, Karsten Scheibler, M. Sauer, S. Reddy, B. Becker","doi":"10.1109/VTS.2015.7116296","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116296","url":null,"abstract":"Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Generating tests to detect such defects is challenging due to the need to accurately determine the coupling capacitances between the open net and its aggressors and fix the state of these aggressors during test. Process variations cause deviations from assumed values of circuit parameters thus potentially invalidating tests generated with assumed circuit parameters. Additionally, recent investigation using test chips showed that the steady state voltage on open nets may drift slowly with the application of circuit inputs and can be different at different nets.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129039600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116299
R. Aitken
There has been a lot of interest recently in design-for-security, while at the same time research opportunities in conventional DFT are waning. Is DFS the new DFT, since many similar techniques can be applied, or is DFS something new, requiring new approaches to be successful, or is DFS merely a distraction? The panel will discuss the issues and give the audience the opportunity to decide.
{"title":"Panel: Is design-for-security the new DFT?","authors":"R. Aitken","doi":"10.1109/VTS.2015.7116299","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116299","url":null,"abstract":"There has been a lot of interest recently in design-for-security, while at the same time research opportunities in conventional DFT are waning. Is DFS the new DFT, since many similar techniques can be applied, or is DFS something new, requiring new approaches to be successful, or is DFS merely a distraction? The panel will discuss the issues and give the audience the opportunity to decide.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116449693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116304
S. Kodakara, S. Natarajan
The era of Internet-Of-Things, or IOT - ubiquitous connected components, shared across an intelligent communication medium, and analyzed by massive storage and analysis “clouds” - has begun. With development of deep integration and sensor technologies, very high speed network connectivity, and huge server farms that can provide 24×7 service, the ability to monitor, process and optimize our work and personal life is at our door step.
{"title":"Special session 12B: Panel: IOT - Reliable? Secure? Or death by a billion cuts?","authors":"S. Kodakara, S. Natarajan","doi":"10.1109/VTS.2015.7116304","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116304","url":null,"abstract":"The era of Internet-Of-Things, or IOT - ubiquitous connected components, shared across an intelligent communication medium, and analyzed by massive storage and analysis “clouds” - has begun. With development of deep integration and sensor technologies, very high speed network connectivity, and huge server farms that can provide 24×7 service, the ability to monitor, process and optimize our work and personal life is at our door step.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133345665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116275
Anthony Coyette, B. Esen, Ronny Vanhooren, Wim Dobbelaere, G. Gielen
A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem such that the fault coverage is maximized and the silicon overhead is minimized. The new method was applied to a real-case industrial circuit, demonstrating a nearly 100 percent coverage at the expense of an area increase of about 5 percent.
{"title":"Automated testing of mixed-signal integrated circuits by topology modification","authors":"Anthony Coyette, B. Esen, Ronny Vanhooren, Wim Dobbelaere, G. Gielen","doi":"10.1109/VTS.2015.7116275","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116275","url":null,"abstract":"A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem such that the fault coverage is maximized and the silicon overhead is minimized. The new method was applied to a real-case industrial circuit, demonstrating a nearly 100 percent coverage at the expense of an area increase of about 5 percent.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"347 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131528748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116292
Mehdi Sadi, L. Winemberg, M. Tehranipoor
Because of process variations, the post-silicon critical or near-critical paths differ from those identified in the pre-silicon stage. Thus, it has become necessary to extract timing slack information from circuit paths in the post-silicon phase. In this paper, we present a robust digital sensor IP for in-situ timing slack monitoring on actual circuit paths from SoCs. The timing slack data is converted into a digital format and stored in a dedicated scan register chain for easy extraction at any point in time during test and functional modes. A novel layout-aware and netlist-level sensor insertion flow is proposed. The sensor IP has been designed with 32/28nm standard cell library and its performance is demonstrated in the physical design of several benchmark circuits.
{"title":"A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs","authors":"Mehdi Sadi, L. Winemberg, M. Tehranipoor","doi":"10.1109/VTS.2015.7116292","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116292","url":null,"abstract":"Because of process variations, the post-silicon critical or near-critical paths differ from those identified in the pre-silicon stage. Thus, it has become necessary to extract timing slack information from circuit paths in the post-silicon phase. In this paper, we present a robust digital sensor IP for in-situ timing slack monitoring on actual circuit paths from SoCs. The timing slack data is converted into a digital format and stored in a dedicated scan register chain for easy extraction at any point in time during test and functional modes. A novel layout-aware and netlist-level sensor insertion flow is proposed. The sensor IP has been designed with 32/28nm standard cell library and its performance is demonstrated in the physical design of several benchmark circuits.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125787045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116263
M. Ricchetti
Debug and diagnosis using the IEEE 1149.1 TAP has been a useful tool for engineers for some twenty years. The TAP however is limited as it only can provide a single full duplex data stream of 50 to 100mb/s. IEEE 1500 provides higher bandwidth via parallel access to multiple scan-channels however providing physical access to hundreds of pins has become more challenging. This parallel access has little benefit in debug when the SoC is in the system. This presentation focuses on the solution proposed by IEEE P1149.10 which uses a packet protocol over SERDES to access on-chip DFT (instruments) like the TAP but with multi-gigabit SERDES. With the standardization of the IEEE 1149.1-2013 PDL language (Procedural Description Language) which abstracts the TAP, PDL can be used with a higher speed interface as proposed by P1149.10. Use cases of how the proposed standard are shown with benefits for silicon debug.
{"title":"Innovative practices session 3C: Advances in silicon debug & diagnosis","authors":"M. Ricchetti","doi":"10.1109/VTS.2015.7116263","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116263","url":null,"abstract":"Debug and diagnosis using the IEEE 1149.1 TAP has been a useful tool for engineers for some twenty years. The TAP however is limited as it only can provide a single full duplex data stream of 50 to 100mb/s. IEEE 1500 provides higher bandwidth via parallel access to multiple scan-channels however providing physical access to hundreds of pins has become more challenging. This parallel access has little benefit in debug when the SoC is in the system. This presentation focuses on the solution proposed by IEEE P1149.10 which uses a packet protocol over SERDES to access on-chip DFT (instruments) like the TAP but with multi-gigabit SERDES. With the standardization of the IEEE 1149.1-2013 PDL language (Procedural Description Language) which abstracts the TAP, PDL can be used with a higher speed interface as proposed by P1149.10. Use cases of how the proposed standard are shown with benefits for silicon debug.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127004829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116283
S. Ozev, L. Milor
BIST for analog and RF circuits has been proposed many years ago and we are still chasing it. One school of thought is to have generic BIST components for input stimulus generation and output analysis and to use them in a plug-and-play fashion. Another school of thought is to develop dedicated circuits for each functionality and re-use the same blocks for the same functionality. A third approach is designing completely circuit-specific BIST for each primary circuit. The truth is ad-hoc examples of BIST have been around for years. However, there is no standardized way of implementing or inserting BIST for analog and RF circuits. The panelists, all experts in this domain, will share their view of the best way of implementing BIST for analog and RF circuits, if there is such a thing…
{"title":"Panel: Analog/RF BIST: Are we there yet?","authors":"S. Ozev, L. Milor","doi":"10.1109/VTS.2015.7116283","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116283","url":null,"abstract":"BIST for analog and RF circuits has been proposed many years ago and we are still chasing it. One school of thought is to have generic BIST components for input stimulus generation and output analysis and to use them in a plug-and-play fashion. Another school of thought is to develop dedicated circuits for each functionality and re-use the same blocks for the same functionality. A third approach is designing completely circuit-specific BIST for each primary circuit. The truth is ad-hoc examples of BIST have been around for years. However, there is no standardized way of implementing or inserting BIST for analog and RF circuits. The panelists, all experts in this domain, will share their view of the best way of implementing BIST for analog and RF circuits, if there is such a thing…","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130809399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116253
Da Cheng, S. Gupta
Hardware redundancy, such as spare processors and cores, has been added to chip multi-processors (CMPs) to improve yield while sustaining all functionalities of CMPs. During post-silicon testing, spares processors and cores are used for repair. Even after repair, some CMPs may have processors with insufficient number of cores; in such CMPs some processors are disabled and such chips are sold at lower prices to improve yield per area. Despite binning on the number of processors, substantial functional resources are wasted in disabled components. In this work, we propose a new utility function and a new repair algorithm which enable utilization of every working core on a CMP. We demonstrate the benefits of the proposed approach for benchmarks from ISPASS and Nvidia CUDA SDK using GPGPU-sim to compute the instructions per cycle (IPC). Results show that our design and repair approaches provide above 50% IPC per wafer area even with 10x the current defect density.
硬件冗余，如备用处理器和核心，已经添加到芯片多处理器(cmp)中，以提高产量，同时保持cmp的所有功能。在硅后测试期间，备用处理器和核心用于修复。即使在修复之后，一些cmp的处理器可能内核数量不足;在这种cmp中，一些处理器被禁用，这样的芯片以较低的价格出售，以提高单位面积的产量。尽管减少了处理器的数量，但是大量的功能资源被浪费在被禁用的组件上。在这项工作中，我们提出了一种新的效用函数和一种新的修复算法，使CMP上的每个工作核心都能被利用。我们展示了使用GPGPU-sim卡计算每周期指令(IPC)的ISPASS和Nvidia CUDA SDK基准测试方法的好处。结果表明，我们的设计和修复方法即使在当前缺陷密度为10倍的情况下，每个晶圆面积也能提供50%以上的IPC。
{"title":"PPB: Partially-working processors binning for maximizing wafer utilization","authors":"Da Cheng, S. Gupta","doi":"10.1109/VTS.2015.7116253","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116253","url":null,"abstract":"Hardware redundancy, such as spare processors and cores, has been added to chip multi-processors (CMPs) to improve yield while sustaining all functionalities of CMPs. During post-silicon testing, spares processors and cores are used for repair. Even after repair, some CMPs may have processors with insufficient number of cores; in such CMPs some processors are disabled and such chips are sold at lower prices to improve yield per area. Despite binning on the number of processors, substantial functional resources are wasted in disabled components. In this work, we propose a new utility function and a new repair algorithm which enable utilization of every working core on a CMP. We demonstrate the benefits of the proposed approach for benchmarks from ISPASS and Nvidia CUDA SDK using GPGPU-sim to compute the instructions per cycle (IPC). Results show that our design and repair approaches provide above 50% IPC per wafer area even with 10x the current defect density.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130861639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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