Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116290
Andres F. Gomez, L. Poehls, F. Vargas, V. Champac
This paper proposes an early resilience methodology to identify circuit output nodes where aging sensors should be inserted for an error prediction framework. The methodology is based in a pre-layout statistical estimation of the signal paths likely to become critical due to NBTI and/or Process Variations. To handle the fact that spatial correlation information is not available at early steps of the design flow, a statistical approach maximizing critical paths coverage is proposed. The results obtained with the early prediction methodology are compared with those obtained with spatial correlation information. The proposed methodology provides a good prediction of the set of critical paths to be monitored. Furthermore, location and number of aging sensors required to be inserted at critical paths output nodes are closely predicted.
{"title":"An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging","authors":"Andres F. Gomez, L. Poehls, F. Vargas, V. Champac","doi":"10.1109/VTS.2015.7116290","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116290","url":null,"abstract":"This paper proposes an early resilience methodology to identify circuit output nodes where aging sensors should be inserted for an error prediction framework. The methodology is based in a pre-layout statistical estimation of the signal paths likely to become critical due to NBTI and/or Process Variations. To handle the fact that spatial correlation information is not available at early steps of the design flow, a statistical approach maximizing critical paths coverage is proposed. The results obtained with the early prediction methodology are compared with those obtained with spatial correlation information. The proposed methodology provides a good prediction of the set of critical paths to be monitored. Furthermore, location and number of aging sensors required to be inserted at critical paths output nodes are closely predicted.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115138369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116272
M. E. Amyeen
This talk focuses on test and debug challenges that are unique to large die products. A technical review of problems being faced today specific to test quality, test time, test cost, electrical and speed content, and debug will be outlined along with some current solutions being pursued to drive large die products to production quality. The talk concludes with a discussion about new solutions and areas of innovation that will be necessary to keep future generations of these products manufacturable, and on a cadence that meets the stringent time to market requirements.
{"title":"Innovative practices session 5C: Advancements in test -keeping moore moving!","authors":"M. E. Amyeen","doi":"10.1109/VTS.2015.7116272","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116272","url":null,"abstract":"This talk focuses on test and debug challenges that are unique to large die products. A technical review of problems being faced today specific to test quality, test time, test cost, electrical and speed content, and debug will be outlined along with some current solutions being pursued to drive large die products to production quality. The talk concludes with a discussion about new solutions and areas of innovation that will be necessary to keep future generations of these products manufacturable, and on a cadence that meets the stringent time to market requirements.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129708513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116296
D. Erb, Karsten Scheibler, M. Sauer, S. Reddy, B. Becker
Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Generating tests to detect such defects is challenging due to the need to accurately determine the coupling capacitances between the open net and its aggressors and fix the state of these aggressors during test. Process variations cause deviations from assumed values of circuit parameters thus potentially invalidating tests generated with assumed circuit parameters. Additionally, recent investigation using test chips showed that the steady state voltage on open nets may drift slowly with the application of circuit inputs and can be different at different nets.
{"title":"Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects","authors":"D. Erb, Karsten Scheibler, M. Sauer, S. Reddy, B. Becker","doi":"10.1109/VTS.2015.7116296","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116296","url":null,"abstract":"Interconnect opens are known to be one of the predominant defects in nanoscale technologies. Generating tests to detect such defects is challenging due to the need to accurately determine the coupling capacitances between the open net and its aggressors and fix the state of these aggressors during test. Process variations cause deviations from assumed values of circuit parameters thus potentially invalidating tests generated with assumed circuit parameters. Additionally, recent investigation using test chips showed that the steady state voltage on open nets may drift slowly with the application of circuit inputs and can be different at different nets.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129039600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116299
R. Aitken
There has been a lot of interest recently in design-for-security, while at the same time research opportunities in conventional DFT are waning. Is DFS the new DFT, since many similar techniques can be applied, or is DFS something new, requiring new approaches to be successful, or is DFS merely a distraction? The panel will discuss the issues and give the audience the opportunity to decide.
{"title":"Panel: Is design-for-security the new DFT?","authors":"R. Aitken","doi":"10.1109/VTS.2015.7116299","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116299","url":null,"abstract":"There has been a lot of interest recently in design-for-security, while at the same time research opportunities in conventional DFT are waning. Is DFS the new DFT, since many similar techniques can be applied, or is DFS something new, requiring new approaches to be successful, or is DFS merely a distraction? The panel will discuss the issues and give the audience the opportunity to decide.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116449693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116304
S. Kodakara, S. Natarajan
The era of Internet-Of-Things, or IOT - ubiquitous connected components, shared across an intelligent communication medium, and analyzed by massive storage and analysis “clouds” - has begun. With development of deep integration and sensor technologies, very high speed network connectivity, and huge server farms that can provide 24×7 service, the ability to monitor, process and optimize our work and personal life is at our door step.
{"title":"Special session 12B: Panel: IOT - Reliable? Secure? Or death by a billion cuts?","authors":"S. Kodakara, S. Natarajan","doi":"10.1109/VTS.2015.7116304","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116304","url":null,"abstract":"The era of Internet-Of-Things, or IOT - ubiquitous connected components, shared across an intelligent communication medium, and analyzed by massive storage and analysis “clouds” - has begun. With development of deep integration and sensor technologies, very high speed network connectivity, and huge server farms that can provide 24×7 service, the ability to monitor, process and optimize our work and personal life is at our door step.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133345665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116275
Anthony Coyette, B. Esen, Ronny Vanhooren, Wim Dobbelaere, G. Gielen
A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem such that the fault coverage is maximized and the silicon overhead is minimized. The new method was applied to a real-case industrial circuit, demonstrating a nearly 100 percent coverage at the expense of an area increase of about 5 percent.
{"title":"Automated testing of mixed-signal integrated circuits by topology modification","authors":"Anthony Coyette, B. Esen, Ronny Vanhooren, Wim Dobbelaere, G. Gielen","doi":"10.1109/VTS.2015.7116275","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116275","url":null,"abstract":"A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem such that the fault coverage is maximized and the silicon overhead is minimized. The new method was applied to a real-case industrial circuit, demonstrating a nearly 100 percent coverage at the expense of an area increase of about 5 percent.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"347 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131528748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116267
Chang Hao, Huaguo Liang
Defects in TSV not only lead to variation in the propagation delay but also in the transition delay of the net connected to the TSV. A non-invasive approach for pre-bond TSV test based on pulse shrinkage is proposed to detect resistive open and leakage fault. TSVs are used as capacitive loads of their driving gates, then the pulse visiting the cyclic shrinkage cells will be shrunk until it vanishes completely. The shrinkage amount is digitized into a digital code to compare with an expected value of fault free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of resistive open defects 0.2kΩ above and equivalent leakage resistance less than 40MΩ. The estimated design for testability area cost of our method is negligible for realistic dies.
{"title":"Pulse shrinkage based pre-bond through silicon vias test in 3D IC","authors":"Chang Hao, Huaguo Liang","doi":"10.1109/VTS.2015.7116267","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116267","url":null,"abstract":"Defects in TSV not only lead to variation in the propagation delay but also in the transition delay of the net connected to the TSV. A non-invasive approach for pre-bond TSV test based on pulse shrinkage is proposed to detect resistive open and leakage fault. TSVs are used as capacitive loads of their driving gates, then the pulse visiting the cyclic shrinkage cells will be shrunk until it vanishes completely. The shrinkage amount is digitized into a digital code to compare with an expected value of fault free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of resistive open defects 0.2kΩ above and equivalent leakage resistance less than 40MΩ. The estimated design for testability area cost of our method is negligible for realistic dies.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129238325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116249
Tao Chen, Degang Chen
Linearity test of an analog-to-digital converter (ADC) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. For high performance ADCs, the overall manufacturing cost could be dominated by the long test time and the high-precision test instruments. This paper introduces the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) method for high resolution ADC linearity test, allowing the stimulus signal's linearity requirement to be significantly relaxed and the test time to be reduced by orders of magnitude compared to the state-of-art histogram method. The USER-SMILE algorithm uses two nonlinear but functionally related input signals as ADC excitations and uses a stimulus error removal technique to recover test accuracy. The USER-SMILE algorithm also uses the ultrafast segmented model identification of linearity errors (uSMILE) approach to dramatically reduce test time while achieving test accuracy and coverage superior to the histogram method. The USER-SMILE algorithm is validated by extensive simulation with different types of ADCs, different resolution levels, and different types of input signals including nonlinear ramps, nonlinear sine waves and even random input signals. Statistical simulation results show that for a 16-bit SAR ADC, with two 1 hit/code nonlinear ramp signals, the INL test error is within +/- 0.4LSB.
{"title":"Ultrafast stimulus error removal algorithm for ADC linearity test","authors":"Tao Chen, Degang Chen","doi":"10.1109/VTS.2015.7116249","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116249","url":null,"abstract":"Linearity test of an analog-to-digital converter (ADC) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. For high performance ADCs, the overall manufacturing cost could be dominated by the long test time and the high-precision test instruments. This paper introduces the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) method for high resolution ADC linearity test, allowing the stimulus signal's linearity requirement to be significantly relaxed and the test time to be reduced by orders of magnitude compared to the state-of-art histogram method. The USER-SMILE algorithm uses two nonlinear but functionally related input signals as ADC excitations and uses a stimulus error removal technique to recover test accuracy. The USER-SMILE algorithm also uses the ultrafast segmented model identification of linearity errors (uSMILE) approach to dramatically reduce test time while achieving test accuracy and coverage superior to the histogram method. The USER-SMILE algorithm is validated by extensive simulation with different types of ADCs, different resolution levels, and different types of input signals including nonlinear ramps, nonlinear sine waves and even random input signals. Statistical simulation results show that for a 16-bit SAR ADC, with two 1 hit/code nonlinear ramp signals, the INL test error is within +/- 0.4LSB.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122610318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116258
S. Sindia
As the economics of traditional devices scaling changes, alternative solutions to increase transistor counts in semiconductor packages are being explored, including various multi-die integration techniques. These solutions include 3D die stacking, 2.5D with dies sitting side-by-side on substrate, Package-on-Package (PoP), System in Package (SiP), etc. In particular, 2.5D and 3D device integration may create new challenges and old challenges seen in multi-chip module (MCM) manufacturing also re-appear to affect new users.
{"title":"Innovative practices session 2C: New technologies, new challenges - 2","authors":"S. Sindia","doi":"10.1109/VTS.2015.7116258","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116258","url":null,"abstract":"As the economics of traditional devices scaling changes, alternative solutions to increase transistor counts in semiconductor packages are being explored, including various multi-die integration techniques. These solutions include 3D die stacking, 2.5D with dies sitting side-by-side on substrate, Package-on-Package (PoP), System in Package (SiP), etc. In particular, 2.5D and 3D device integration may create new challenges and old challenges seen in multi-chip module (MCM) manufacturing also re-appear to affect new users.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123034199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116279
Ashkan Eghbal, Pooria M. Yaghini, N. Bagherzadeh
TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a TSV using circuit-level model is presented in this article. Two coding approaches are proposed to mitigate capacitive parasitic effects by adjusting the current flow pattern for any given n × n mesh of TSV arrangement to reduce the number of 8C/7C parasitic capacitance. The experimental results proves the efficacy of the proposed coding methods.
{"title":"Capacitive Coupling Mitigation for TSV-based 3D ICs","authors":"Ashkan Eghbal, Pooria M. Yaghini, N. Bagherzadeh","doi":"10.1109/VTS.2015.7116279","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116279","url":null,"abstract":"TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a TSV using circuit-level model is presented in this article. Two coding approaches are proposed to mitigate capacitive parasitic effects by adjusting the current flow pattern for any given n × n mesh of TSV arrangement to reduce the number of 8C/7C parasitic capacitance. The experimental results proves the efficacy of the proposed coding methods.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"55 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120922296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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