Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116269
Andreas Riefert, M. Sauer, S. Reddy, B. Becker
Manufactured VLSI circuits using a new technology typically suffer from systematic defects that are process-dependent and at sub-nanometer feature sizes such defects may be even design-dependent. The root causes for systematic defects must be determined to ramp up yields. Volume diagnosis is becoming popular to identify root causes for systematic defects. Volume diagnosis uses logic diagnosis based on failing circuit responses to production tests of a large number of failing devices, followed by statistical analysis methods to determine the root cause(s) for yield limiters. Typically production tests use fault detection tests and hence may have limited diagnosis resolution. To improve diagnosis resolution diagnostic ATPGs can be used to generate test sets to distinguish all pairs of distinguishable faults in one or more fault models. The sizes of such tests tend to be considerably higher than fault detection test sets used as production tests. For this reason, generation of test sets that detect faults and also possess a high diagnosis resolution is important. In this work we present a method to improve the diagnosis resolution of a compact fault detection test set without increasing pattern count or decreasing fault coverage. The basic idea of the approach is to generate a SAT formula which enforces diagnosis and is solved by a MAX-SAT solver which is a SAT-based maximization tool. We believe this is the first time a method to improve diagnosis resolution of a test set of given size has been reported. Experimental results on ISCAS 89 circuits demonstrate the effectiveness of the proposed method.
{"title":"Improving diagnosis resolution of a fault detection test set","authors":"Andreas Riefert, M. Sauer, S. Reddy, B. Becker","doi":"10.1109/VTS.2015.7116269","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116269","url":null,"abstract":"Manufactured VLSI circuits using a new technology typically suffer from systematic defects that are process-dependent and at sub-nanometer feature sizes such defects may be even design-dependent. The root causes for systematic defects must be determined to ramp up yields. Volume diagnosis is becoming popular to identify root causes for systematic defects. Volume diagnosis uses logic diagnosis based on failing circuit responses to production tests of a large number of failing devices, followed by statistical analysis methods to determine the root cause(s) for yield limiters. Typically production tests use fault detection tests and hence may have limited diagnosis resolution. To improve diagnosis resolution diagnostic ATPGs can be used to generate test sets to distinguish all pairs of distinguishable faults in one or more fault models. The sizes of such tests tend to be considerably higher than fault detection test sets used as production tests. For this reason, generation of test sets that detect faults and also possess a high diagnosis resolution is important. In this work we present a method to improve the diagnosis resolution of a compact fault detection test set without increasing pattern count or decreasing fault coverage. The basic idea of the approach is to generate a SAT formula which enforces diagnosis and is solved by a MAX-SAT solver which is a SAT-based maximization tool. We believe this is the first time a method to improve diagnosis resolution of a test set of given size has been reported. Experimental results on ISCAS 89 circuits demonstrate the effectiveness of the proposed method.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123085367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116274
Xian Wang, D. Banerjee, A. Chatterjee
The quality of a communication link is commonly indicated by signal to noise/interference ratio and affected by noise and interference variance. To ensure a power efficient adaptive OFDM system's performance, the system needs to be tested against various channel conditions. Conventional algorithms and experiments assume that the noise and interference density stays constant over the OFDM frequency band but in reality the communication link often populated with both white noise and interference that results an uneven impact on OFDM spectrum. To create such channel condition, an up-conversion is commonly used. However, due to the non-linearity of the mixer, the up-converted interference is always distorted. The proposed method uses a modified higher-than-Nyquist-rate RF signal generation algorithm to minimize the distortion of generated interference within a pre-defined output bandwidth. Both concept validation and experimental measurement have been conducted to prove the effect of proposed method.
{"title":"Low cost high frequency signal synthesis: Application to RF channel interference testing","authors":"Xian Wang, D. Banerjee, A. Chatterjee","doi":"10.1109/VTS.2015.7116274","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116274","url":null,"abstract":"The quality of a communication link is commonly indicated by signal to noise/interference ratio and affected by noise and interference variance. To ensure a power efficient adaptive OFDM system's performance, the system needs to be tested against various channel conditions. Conventional algorithms and experiments assume that the noise and interference density stays constant over the OFDM frequency band but in reality the communication link often populated with both white noise and interference that results an uneven impact on OFDM spectrum. To create such channel condition, an up-conversion is commonly used. However, due to the non-linearity of the mixer, the up-converted interference is always distorted. The proposed method uses a modified higher-than-Nyquist-rate RF signal generation algorithm to minimize the distortion of generated interference within a pre-defined output bandwidth. Both concept validation and experimental measurement have been conducted to prove the effect of proposed method.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123514567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116262
D. Drouin, Mohamed Amine-Bounouar, G. Droulers, M. Labalette, M. Pioro-Ladrière, A. Souifi, S. Ecoffey
This presentation will address the potential of nanoelectronic devices 3D monolithic integration in the CMOS back-end-of-line (BEOL) to add functionality and enhance integrated circuits (ICs) performances.
{"title":"3D microelectronic with BEOL compatible devices","authors":"D. Drouin, Mohamed Amine-Bounouar, G. Droulers, M. Labalette, M. Pioro-Ladrière, A. Souifi, S. Ecoffey","doi":"10.1109/VTS.2015.7116262","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116262","url":null,"abstract":"This presentation will address the potential of nanoelectronic devices 3D monolithic integration in the CMOS back-end-of-line (BEOL) to add functionality and enhance integrated circuits (ICs) performances.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121110681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116289
Woongrae Kim, Chang-Chih Chen, Soonyoung Cha, L. Milor
In this paper we present Memory Built-In Self-Test (MBIST) diagnosis methodologies for failure analysis of time-dependent breakdown due to gate oxide breakdown (GOBD) and backend time-dependent dielectric breakdown (BTDDB) in an SRAM array. First, a Built-In Self-Test (BIST) system and algorithm detect the breakdown mechanisms and identify the locations of the faulty sites in SRAM cells. Then, probabilities of failure are estimated for BTDDB and GOBD by matching the observed failure rate from BIST and the expected failure distribution functions from system simulations under realistic use scenarios, with different simulated failure rates for BTDDB and GOBD.
{"title":"MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array","authors":"Woongrae Kim, Chang-Chih Chen, Soonyoung Cha, L. Milor","doi":"10.1109/VTS.2015.7116289","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116289","url":null,"abstract":"In this paper we present Memory Built-In Self-Test (MBIST) diagnosis methodologies for failure analysis of time-dependent breakdown due to gate oxide breakdown (GOBD) and backend time-dependent dielectric breakdown (BTDDB) in an SRAM array. First, a Built-In Self-Test (BIST) system and algorithm detect the breakdown mechanisms and identify the locations of the faulty sites in SRAM cells. Then, probabilities of failure are estimated for BTDDB and GOBD by matching the observed failure rate from BIST and the expected failure distribution functions from system simulations under realistic use scenarios, with different simulated failure rates for BTDDB and GOBD.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126236896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116293
S. K. Rao, B. Shivashankar, R. Robucci, Nilanjan Banerjee, C. Patel
Variations in the power-distribution network are exacerbated because of scaled supply voltages and smaller noise margins in sub-nanometer designs, which adversely affect performance and yield. Power-Supply noise incurred by excessive simultaneous switching of multiple paths negatively impacts the timing of a circuit. Supply noise is a major issue especially during transition and delay test where test vectors cause increased switching as compared to functional operation resulting in increase in path delays. Test rejects due to excessive noise-induced failures during delay and transition testing negatively impacts yield. Hence there is a need to accurately characterize the resistive and inductive voltage drop caused by excessive switching. To our knowledge, inductive drop has been excluded to simplify noise analysis. In our previous work, we have presented a convolution-based dynamic method (herein referred to as PSANDE) to estimate both IR and Ldi/dt drop on small combinational and sequential circuits. In this paper we show that the effectiveness of the design partitioning technique makes the framework feasible for a larger design. Our dynamic approach involves selectively simulating only extracted switching logic which makes the run-time tractable as compared to prohibitive full-chip SPICE simulations. We also present data to show that PSANDE can accurately predict the power-supply noise due to clock tree switching. Data presented in this paper for power supply noise is based on a large ITC'99 sequential benchmark b17 circuit. with a maximum error of 8.2% in comparison to full-chip SPICE results.
{"title":"Scalability study of PSANDE: Power supply analysis for noise and delay estimation","authors":"S. K. Rao, B. Shivashankar, R. Robucci, Nilanjan Banerjee, C. Patel","doi":"10.1109/VTS.2015.7116293","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116293","url":null,"abstract":"Variations in the power-distribution network are exacerbated because of scaled supply voltages and smaller noise margins in sub-nanometer designs, which adversely affect performance and yield. Power-Supply noise incurred by excessive simultaneous switching of multiple paths negatively impacts the timing of a circuit. Supply noise is a major issue especially during transition and delay test where test vectors cause increased switching as compared to functional operation resulting in increase in path delays. Test rejects due to excessive noise-induced failures during delay and transition testing negatively impacts yield. Hence there is a need to accurately characterize the resistive and inductive voltage drop caused by excessive switching. To our knowledge, inductive drop has been excluded to simplify noise analysis. In our previous work, we have presented a convolution-based dynamic method (herein referred to as PSANDE) to estimate both IR and Ldi/dt drop on small combinational and sequential circuits. In this paper we show that the effectiveness of the design partitioning technique makes the framework feasible for a larger design. Our dynamic approach involves selectively simulating only extracted switching logic which makes the run-time tractable as compared to prohibitive full-chip SPICE simulations. We also present data to show that PSANDE can accurately predict the power-supply noise due to clock tree switching. Data presented in this paper for power supply noise is based on a large ITC'99 sequential benchmark b17 circuit. with a maximum error of 8.2% in comparison to full-chip SPICE results.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125949431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116246
C. Jaress, P. Brisk, D. Grissom
Microfluidic technologies offer benefits to the biological sciences by miniaturizing and automating chemical reactions. Software-controlled laboratories-on-a-chip (LoCs) execute biological protocols (assays) specified using high-level languages. Integrated sensors and video monitoring provide a closed feedback loop between the LoC and its control software, which provide timely information about the progress of an ongoing assay and the overall health of the LoC. This paper introduces a cyber-physical control algorithm that rectifies hard and soft faults that are detected dynamically while executing an assay on a digital microfluidic biochip (DMFB), one specific LoC technology. The approach is scalable (i.e., there is no fixed limit on the number of faults that may occur), and runs efficiently in practice, thereby limiting the performance overhead incurred when a hard or soft fault occurs during assay execution.
{"title":"Rapid online fault recovery for cyber-physical digital microfluidic biochips","authors":"C. Jaress, P. Brisk, D. Grissom","doi":"10.1109/VTS.2015.7116246","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116246","url":null,"abstract":"Microfluidic technologies offer benefits to the biological sciences by miniaturizing and automating chemical reactions. Software-controlled laboratories-on-a-chip (LoCs) execute biological protocols (assays) specified using high-level languages. Integrated sensors and video monitoring provide a closed feedback loop between the LoC and its control software, which provide timely information about the progress of an ongoing assay and the overall health of the LoC. This paper introduces a cyber-physical control algorithm that rectifies hard and soft faults that are detected dynamically while executing an assay on a digital microfluidic biochip (DMFB), one specific LoC technology. The approach is scalable (i.e., there is no fixed limit on the number of faults that may occur), and runs efficiently in practice, thereby limiting the performance overhead incurred when a hard or soft fault occurs during assay execution.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126907780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-01DOI: 10.1109/VTS.2015.7116247
Yong-Xiao Chen, Jin-Fu Li
Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.
{"title":"Fault modeling and testing of 1T1R memristor memories","authors":"Yong-Xiao Chen, Jin-Fu Li","doi":"10.1109/VTS.2015.7116247","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116247","url":null,"abstract":"Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121576974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/VTS.2015.7116285
M. Portolan, K. Huang
Named after Prof. E.J. McCluskey, a key contributor to the field of test technology, the 2015 TTTC's Doctoral Thesis Award serves the purpose to i) promote the most impactful doctoral student work, ii) provide the students with the exposure to the community and the prospective employers, and iii) support interaction between academia and industry in the field of test technology. TTTC's E.J. McCluskey Best Doctoral Thesis Award will be given to the winning student of the doctoral student contest and his or her advisor. The award consists of a certificate, an honorarium and an invitation to submit a paper on the presented work to the IEEE Design & Test magazine.
{"title":"Special session 8C: E.J. McCluskey doctoral thesis award semi-final","authors":"M. Portolan, K. Huang","doi":"10.1109/VTS.2015.7116285","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116285","url":null,"abstract":"Named after Prof. E.J. McCluskey, a key contributor to the field of test technology, the 2015 TTTC's Doctoral Thesis Award serves the purpose to i) promote the most impactful doctoral student work, ii) provide the students with the exposure to the community and the prospective employers, and iii) support interaction between academia and industry in the field of test technology. TTTC's E.J. McCluskey Best Doctoral Thesis Award will be given to the winning student of the doctoral student contest and his or her advisor. The award consists of a certificate, an honorarium and an invitation to submit a paper on the presented work to the IEEE Design & Test magazine.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124756769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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