Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116261
A. Ahmadi, K. Huang, A. Nahar, Bob Orr, M. Pas, J. Carulli, Y. Makris
We investigate the utility of correlations between e-test and probe test measurements in predicting yield. Specifically, we first examine whether statistical methods can accurately predict parametric probe test yield as a function of e-test measurements within the same fab. Then, we investigate whether the e-test profile of a destination fab, in conjunction with the e-test and probe test profiles of a source fab, suffice for accurate yield prognosis during fab-to-fab product migration. Results using an industrial dataset of ~3.5M devices from a 65nm Texas Instruments RF transceiver design fabricated in two different fabs reveal that (i) within-fab yield prediction error is in the range of a few tenths of a percentile point, and (ii) fab-to-fab yield prediction error is in the range of half a percentile point.
{"title":"Yield prognosis for fab-to-fab product migration","authors":"A. Ahmadi, K. Huang, A. Nahar, Bob Orr, M. Pas, J. Carulli, Y. Makris","doi":"10.1109/VTS.2015.7116261","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116261","url":null,"abstract":"We investigate the utility of correlations between e-test and probe test measurements in predicting yield. Specifically, we first examine whether statistical methods can accurately predict parametric probe test yield as a function of e-test measurements within the same fab. Then, we investigate whether the e-test profile of a destination fab, in conjunction with the e-test and probe test profiles of a source fab, suffice for accurate yield prognosis during fab-to-fab product migration. Results using an industrial dataset of ~3.5M devices from a 65nm Texas Instruments RF transceiver design fabricated in two different fabs reveal that (i) within-fab yield prediction error is in the range of a few tenths of a percentile point, and (ii) fab-to-fab yield prediction error is in the range of half a percentile point.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"409 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122787584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116282
S. Natarajan
The traditional focus of work in test has been innovation and efficiency for high volume manufacturing test. However, in reality, a significant amount of effort is expended on design validation and debug prior to deeming analog and high speed serial IO test stimuli content production worthy. In this presentation we emphasize the importance of widening the post-silicon envelope to include early design validation and debug in addition to manufacturing test. The impact on DFX architecture is considered in which in order to be efficient the architecture has to be scalable across a wider set of post-silicon stages. We also discuss the need for establishing quick correlation between design validation and manufacturing test measurements and the time-to-market savings it brings for analog and IO content designed essentially on a digital process technology.
{"title":"Innovative practices session 7C: Mixed signal test and debug","authors":"S. Natarajan","doi":"10.1109/VTS.2015.7116282","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116282","url":null,"abstract":"The traditional focus of work in test has been innovation and efficiency for high volume manufacturing test. However, in reality, a significant amount of effort is expended on design validation and debug prior to deeming analog and high speed serial IO test stimuli content production worthy. In this presentation we emphasize the importance of widening the post-silicon envelope to include early design validation and debug in addition to manufacturing test. The impact on DFX architecture is considered in which in order to be efficient the architecture has to be scalable across a wider set of post-silicon stages. We also discuss the need for establishing quick correlation between design validation and manufacturing test measurements and the time-to-market savings it brings for analog and IO content designed essentially on a digital process technology.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114970488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116302
I. Pomeranz
Test quality metrics that use the numbers of detections of target faults are based on the premise that increasing the number of tests for a fault increases the likelihood of detecting defects around the site of the fault. This paper describes a new definition of the number of detections for faults that have only one test in a given test set. Such faults are prevalent in compact test sets. For a fault with a single test, metrics based on the number of detections yield the same value, one, for any test. The new definition associates different numbers of detections with different tests for the fault by considering the number of distinct test cubes that a test contains. It thus provides a target for the generation of a single test with a higher quality for the fault. The effectiveness of the definition is demonstrated by modifying a compact test set to increase the numbers of detections of single stuck-at faults with single tests, and comparing a bridging fault coverage of the test set before and after the modification.
{"title":"A definition of the number of detections for faults with single tests in a compact scan-based test set","authors":"I. Pomeranz","doi":"10.1109/VTS.2015.7116302","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116302","url":null,"abstract":"Test quality metrics that use the numbers of detections of target faults are based on the premise that increasing the number of tests for a fault increases the likelihood of detecting defects around the site of the fault. This paper describes a new definition of the number of detections for faults that have only one test in a given test set. Such faults are prevalent in compact test sets. For a fault with a single test, metrics based on the number of detections yield the same value, one, for any test. The new definition associates different numbers of detections with different tests for the fault by considering the number of distinct test cubes that a test contains. It thus provides a target for the generation of a single test with a higher quality for the fault. The effectiveness of the definition is demonstrated by modifying a compact test set to increase the numbers of detections of single stuck-at faults with single tests, and comparing a bridging fault coverage of the test set before and after the modification.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128087586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116266
Ran Wang, Guoliang Li, Rui Li, J. Qian, K. Chakrabarty
Interposer-based 2.5D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents an efficient ExTest scheduling strategy that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number of output test pins. We present scheduling and optimization results for a “monster” die with 50 million flip-flops in a 2.5D IC, which is currently in production, to highlight the effectiveness of the proposed test strategy.
{"title":"ExTest scheduling for 2.5D system-on-chip integrated circuits","authors":"Ran Wang, Guoliang Li, Rui Li, J. Qian, K. Chakrabarty","doi":"10.1109/VTS.2015.7116266","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116266","url":null,"abstract":"Interposer-based 2.5D integrated circuits (ICs) enable high-density interconnects, but introduce new challenges for the testing of a system-on-chip (SoC) die on an interposer. This paper presents an efficient ExTest scheduling strategy that implements interconnect testing between tiles inside an SoC die while satisfying the practical constraint that the number of required test pins cannot exceed the number of available pins at the chip level. The tiles in the SoC are divided into groups based on the manner in which they are interconnected. In order to minimize the test time, two optimization solutions are introduced. The first solution minimizes the number of input test pins, and the second solution minimizes the number of output test pins. We present scheduling and optimization results for a “monster” die with 50 million flip-flops in a 2.5D IC, which is currently in production, to highlight the effectiveness of the proposed test strategy.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133248942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116259
S. Kodakara, M. V. Sagar, J. Yuen
We describe a tool and methodology for extracting short and effective functional tests from long running commercial programs and manufacturing system tests for testing microprocessors and SOCs. The tool combines fast Instruction Set Architecture (ISA) simulator and Design for Test (DFT) capabilities of the microprocessor to enable tracing of long running workloads. The trace is then converted into short functional test programs that can be replayed back in silicon. The tool can extract test programs from BIOS, operating systems, application programs and long running manufacturing system test programs. Using data from silicon experiments on recent microprocessor products, we show that the short tests extracted with our tool was able to screen the defective units as effectively as the original long running application with 6X to 15X reduction in test time.
{"title":"Extracting effective functional tests from commercial programs","authors":"S. Kodakara, M. V. Sagar, J. Yuen","doi":"10.1109/VTS.2015.7116259","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116259","url":null,"abstract":"We describe a tool and methodology for extracting short and effective functional tests from long running commercial programs and manufacturing system tests for testing microprocessors and SOCs. The tool combines fast Instruction Set Architecture (ISA) simulator and Design for Test (DFT) capabilities of the microprocessor to enable tracing of long running workloads. The trace is then converted into short functional test programs that can be replayed back in silicon. The tool can extract test programs from BIOS, operating systems, application programs and long running manufacturing system test programs. Using data from silicon experiments on recent microprocessor products, we show that the short tests extracted with our tool was able to screen the defective units as effectively as the original long running application with 6X to 15X reduction in test time.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123445065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116287
Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Christopher Lin, M. Chao
Due to the demand of pursuing a main memory with larger data bandwidth, higher data density, and lower power, the specification of DRAM has been constantly evolved in the past decade. The new DRAM specifications support multiple operating modes with multiple timing settings. It then becomes computationally infeasible to exhaustively validate all the combinations of different operating modes, timing settings and address/data with pure simulation before silicon. In this paper, we propose a framework to generate proper random patterns for validating a newly designed DDR3 SDRAM based on its first silicon chips. The proposed framework needs to not only guarantee the correctness of the generated patterns according to the state diagram and timing constraints defined in the specification but also provide the flexibility of exploring various design corners for the targeted DDR3 SDRAM. We will also show some successful silicon-validation cases of applying the proposed framework to identify the design errors based on real DDR3 SDRAM products.
{"title":"Random pattern generation for post-silicon validation of DDR3 SDRAM","authors":"Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Christopher Lin, M. Chao","doi":"10.1109/VTS.2015.7116287","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116287","url":null,"abstract":"Due to the demand of pursuing a main memory with larger data bandwidth, higher data density, and lower power, the specification of DRAM has been constantly evolved in the past decade. The new DRAM specifications support multiple operating modes with multiple timing settings. It then becomes computationally infeasible to exhaustively validate all the combinations of different operating modes, timing settings and address/data with pure simulation before silicon. In this paper, we propose a framework to generate proper random patterns for validating a newly designed DDR3 SDRAM based on its first silicon chips. The proposed framework needs to not only guarantee the correctness of the generated patterns according to the state diagram and timing constraints defined in the specification but also provide the flexibility of exploring various design corners for the targeted DDR3 SDRAM. We will also show some successful silicon-validation cases of applying the proposed framework to identify the design errors based on real DDR3 SDRAM products.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"385 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124778418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116265
M. Barragán, G. Léger, F. Azaïs, R. D. Blanton, A. Singh, S. Sunter
The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.
{"title":"Special session: Hot topics: Statistical test methods","authors":"M. Barragán, G. Léger, F. Azaïs, R. D. Blanton, A. Singh, S. Sunter","doi":"10.1109/VTS.2015.7116265","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116265","url":null,"abstract":"The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124461132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116254
S. Mirkhani, Balavinayagam Samynathan, J. Abraham
Statistical fault injection is widely used for analyzing hardware in the presence of soft errors. Although this method can give accurate results for averaged erroneous outcomes with a fairly small sample size, it will not be accurate for vulnerability analysis of each sequential element in the design with small sample sizes. This paper describes a novel and highly efficient technique which is suitable for detailed vulnerability analysis of a processor. The technique involves specific sets of assembly language routines, and is shown to be much more efficient and comprehensive compared with traditional statistical error injection on a predetermined set of benchmarks. We have shown the effectiveness of the method using error injection in an ARM Amber25 processor model. Our analysis is based on more than 330,000 simulation runs with single bit-flips on the sequential elements of this processor running our synthetic benchmarks and 40,000 FPGA-based error injections for 4 conventional benchmarks.
{"title":"In-depth soft error vulnerability analysis using synthetic benchmarks","authors":"S. Mirkhani, Balavinayagam Samynathan, J. Abraham","doi":"10.1109/VTS.2015.7116254","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116254","url":null,"abstract":"Statistical fault injection is widely used for analyzing hardware in the presence of soft errors. Although this method can give accurate results for averaged erroneous outcomes with a fairly small sample size, it will not be accurate for vulnerability analysis of each sequential element in the design with small sample sizes. This paper describes a novel and highly efficient technique which is suitable for detailed vulnerability analysis of a processor. The technique involves specific sets of assembly language routines, and is shown to be much more efficient and comprehensive compared with traditional statistical error injection on a predetermined set of benchmarks. We have shown the effectiveness of the method using error injection in an ARM Amber25 processor model. Our analysis is based on more than 330,000 simulation runs with single bit-flips on the sequential elements of this processor running our synthetic benchmarks and 40,000 FPGA-based error injections for 4 conventional benchmarks.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123903535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116273
Kohki Taniguchi, N. Miura, Taisuke Hayashi, M. Nagata
This paper presents an adaptive supply-resonance (SR) suppression scheme at a product testing stage. Dedicated to each product in different assembly forms, an on-chip power-delivery-network analyzer identifies SR frequency and autotunes notch filter for SR noise suppression. The feasibility has been silicon-proven by a prototype demonstration in 0.18μm CMOS successfully.
{"title":"At-Product-Test Dedicated Adaptive supply-resonance suppression","authors":"Kohki Taniguchi, N. Miura, Taisuke Hayashi, M. Nagata","doi":"10.1109/VTS.2015.7116273","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116273","url":null,"abstract":"This paper presents an adaptive supply-resonance (SR) suppression scheme at a product testing stage. Dedicated to each product in different assembly forms, an on-chip power-delivery-network analyzer identifies SR frequency and autotunes notch filter for SR noise suppression. The feasibility has been silicon-proven by a prototype demonstration in 0.18μm CMOS successfully.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"93 Pt A 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115786935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116277
M. Nicolaidis, P. Papavramidou
We illustrate that memory repair for high defect densities allows improving yield, extending circuit life, reducing power, and improving reliability, and can be used to push aggressively the limits of technology scaling. Then we present several developments enabling low-cost memory repair for high defect densities, which alllow realising this promise.
{"title":"Memory repair for high defect densities","authors":"M. Nicolaidis, P. Papavramidou","doi":"10.1109/VTS.2015.7116277","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116277","url":null,"abstract":"We illustrate that memory repair for high defect densities allows improving yield, extending circuit life, reducing power, and improving reliability, and can be used to push aggressively the limits of technology scaling. Then we present several developments enabling low-cost memory repair for high defect densities, which alllow realising this promise.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"47 23","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132062676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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