Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116249
Tao Chen, Degang Chen
Linearity test of an analog-to-digital converter (ADC) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. For high performance ADCs, the overall manufacturing cost could be dominated by the long test time and the high-precision test instruments. This paper introduces the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) method for high resolution ADC linearity test, allowing the stimulus signal's linearity requirement to be significantly relaxed and the test time to be reduced by orders of magnitude compared to the state-of-art histogram method. The USER-SMILE algorithm uses two nonlinear but functionally related input signals as ADC excitations and uses a stimulus error removal technique to recover test accuracy. The USER-SMILE algorithm also uses the ultrafast segmented model identification of linearity errors (uSMILE) approach to dramatically reduce test time while achieving test accuracy and coverage superior to the histogram method. The USER-SMILE algorithm is validated by extensive simulation with different types of ADCs, different resolution levels, and different types of input signals including nonlinear ramps, nonlinear sine waves and even random input signals. Statistical simulation results show that for a 16-bit SAR ADC, with two 1 hit/code nonlinear ramp signals, the INL test error is within +/- 0.4LSB.
{"title":"Ultrafast stimulus error removal algorithm for ADC linearity test","authors":"Tao Chen, Degang Chen","doi":"10.1109/VTS.2015.7116249","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116249","url":null,"abstract":"Linearity test of an analog-to-digital converter (ADC) can be very challenging because it requires a signal generator substantially more linear than the ADC under test. For high performance ADCs, the overall manufacturing cost could be dominated by the long test time and the high-precision test instruments. This paper introduces the ultrafast stimulus error removal and segmented model identification of linearity errors (USER-SMILE) method for high resolution ADC linearity test, allowing the stimulus signal's linearity requirement to be significantly relaxed and the test time to be reduced by orders of magnitude compared to the state-of-art histogram method. The USER-SMILE algorithm uses two nonlinear but functionally related input signals as ADC excitations and uses a stimulus error removal technique to recover test accuracy. The USER-SMILE algorithm also uses the ultrafast segmented model identification of linearity errors (uSMILE) approach to dramatically reduce test time while achieving test accuracy and coverage superior to the histogram method. The USER-SMILE algorithm is validated by extensive simulation with different types of ADCs, different resolution levels, and different types of input signals including nonlinear ramps, nonlinear sine waves and even random input signals. Statistical simulation results show that for a 16-bit SAR ADC, with two 1 hit/code nonlinear ramp signals, the INL test error is within +/- 0.4LSB.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122610318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116258
S. Sindia
As the economics of traditional devices scaling changes, alternative solutions to increase transistor counts in semiconductor packages are being explored, including various multi-die integration techniques. These solutions include 3D die stacking, 2.5D with dies sitting side-by-side on substrate, Package-on-Package (PoP), System in Package (SiP), etc. In particular, 2.5D and 3D device integration may create new challenges and old challenges seen in multi-chip module (MCM) manufacturing also re-appear to affect new users.
{"title":"Innovative practices session 2C: New technologies, new challenges - 2","authors":"S. Sindia","doi":"10.1109/VTS.2015.7116258","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116258","url":null,"abstract":"As the economics of traditional devices scaling changes, alternative solutions to increase transistor counts in semiconductor packages are being explored, including various multi-die integration techniques. These solutions include 3D die stacking, 2.5D with dies sitting side-by-side on substrate, Package-on-Package (PoP), System in Package (SiP), etc. In particular, 2.5D and 3D device integration may create new challenges and old challenges seen in multi-chip module (MCM) manufacturing also re-appear to affect new users.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123034199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116279
Ashkan Eghbal, Pooria M. Yaghini, N. Bagherzadeh
TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a TSV using circuit-level model is presented in this article. Two coding approaches are proposed to mitigate capacitive parasitic effects by adjusting the current flow pattern for any given n × n mesh of TSV arrangement to reduce the number of 8C/7C parasitic capacitance. The experimental results proves the efficacy of the proposed coding methods.
{"title":"Capacitive Coupling Mitigation for TSV-based 3D ICs","authors":"Ashkan Eghbal, Pooria M. Yaghini, N. Bagherzadeh","doi":"10.1109/VTS.2015.7116279","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116279","url":null,"abstract":"TSV-to-TSV capacitive coupling has large disruptive effects on timing requirements of the circuit. The latency effect of TSV-to-TSV capacitive coupling for different characteristics of a TSV using circuit-level model is presented in this article. Two coding approaches are proposed to mitigate capacitive parasitic effects by adjusting the current flow pattern for any given n × n mesh of TSV arrangement to reduce the number of 8C/7C parasitic capacitance. The experimental results proves the efficacy of the proposed coding methods.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"55 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120922296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116255
Subidh Ali, O. Sinanoglu
We present a new class of scan attack on hardware implementation of ciphers. The existing scan attacks on ciphers exploit the Design for Testability (DfT) infrastructure of the implementation, where an attacker applies cipher inputs in the functional mode and then by switching to the test mode retrieves the secret key in the form of test responses. These attacks can be thwarted by applying a reset operation when there is a switch of mode. However, the mode-reset countermeasure can be thwarted by using only the test mode of a secure chip. In this work we show how a Test-Mode-Only (TMO) attack can overcome the constraints imposed by a mode-reset countermeasure and demonstrate TMO attacks on private key as well as public key ciphers.
{"title":"TMO: A new class of attack on cipher misusing test infrastructure","authors":"Subidh Ali, O. Sinanoglu","doi":"10.1109/VTS.2015.7116255","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116255","url":null,"abstract":"We present a new class of scan attack on hardware implementation of ciphers. The existing scan attacks on ciphers exploit the Design for Testability (DfT) infrastructure of the implementation, where an attacker applies cipher inputs in the functional mode and then by switching to the test mode retrieves the secret key in the form of test responses. These attacks can be thwarted by applying a reset operation when there is a switch of mode. However, the mode-reset countermeasure can be thwarted by using only the test mode of a secure chip. In this work we show how a Test-Mode-Only (TMO) attack can overcome the constraints imposed by a mode-reset countermeasure and demonstrate TMO attacks on private key as well as public key ciphers.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132706145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116267
Chang Hao, Huaguo Liang
Defects in TSV not only lead to variation in the propagation delay but also in the transition delay of the net connected to the TSV. A non-invasive approach for pre-bond TSV test based on pulse shrinkage is proposed to detect resistive open and leakage fault. TSVs are used as capacitive loads of their driving gates, then the pulse visiting the cyclic shrinkage cells will be shrunk until it vanishes completely. The shrinkage amount is digitized into a digital code to compare with an expected value of fault free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of resistive open defects 0.2kΩ above and equivalent leakage resistance less than 40MΩ. The estimated design for testability area cost of our method is negligible for realistic dies.
{"title":"Pulse shrinkage based pre-bond through silicon vias test in 3D IC","authors":"Chang Hao, Huaguo Liang","doi":"10.1109/VTS.2015.7116267","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116267","url":null,"abstract":"Defects in TSV not only lead to variation in the propagation delay but also in the transition delay of the net connected to the TSV. A non-invasive approach for pre-bond TSV test based on pulse shrinkage is proposed to detect resistive open and leakage fault. TSVs are used as capacitive loads of their driving gates, then the pulse visiting the cyclic shrinkage cells will be shrunk until it vanishes completely. The shrinkage amount is digitized into a digital code to compare with an expected value of fault free. Experiments on fault detection are presented through HSPICE simulations using realistic models for a 45 nm CMOS technology. The results show the effectiveness in the detection of resistive open defects 0.2kΩ above and equivalent leakage resistance less than 40MΩ. The estimated design for testability area cost of our method is negligible for realistic dies.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129238325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116256
Jennifer Dworak, A. Crouch
Today's chips often contain a wealth of embedded instruments, including sensors, hardware monitors, built-in self-test (BIST) engines, etc. They may process sensitive data that requires encryption or obfuscation and may contain encryption keys and ChipIDs. Unfortunately, unauthorized access to internal registers or instruments through test and debug circuitry can turn design for testability (DFT) logic into a backdoor for data theft, reverse engineering, counterfeiting, and denial-of-service attacks. A compromised chip also poses a security threat to any board or system that includes that chip, and boards have their own security issues. We will provide an overview of some chip and board security concerns as they relate to DFT hardware and will briefly review several ways in which the new IEEE 1687 standard can be made more secure. We will then discuss the need for an IEEE Security Standard that can provide solutions and metrics for providing appropriate security matched to the needs of a real world environment.
{"title":"A call to action: Securing IEEE 1687 and the need for an IEEE test Security Standard","authors":"Jennifer Dworak, A. Crouch","doi":"10.1109/VTS.2015.7116256","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116256","url":null,"abstract":"Today's chips often contain a wealth of embedded instruments, including sensors, hardware monitors, built-in self-test (BIST) engines, etc. They may process sensitive data that requires encryption or obfuscation and may contain encryption keys and ChipIDs. Unfortunately, unauthorized access to internal registers or instruments through test and debug circuitry can turn design for testability (DFT) logic into a backdoor for data theft, reverse engineering, counterfeiting, and denial-of-service attacks. A compromised chip also poses a security threat to any board or system that includes that chip, and boards have their own security issues. We will provide an overview of some chip and board security concerns as they relate to DFT hardware and will briefly review several ways in which the new IEEE 1687 standard can be made more secure. We will then discuss the need for an IEEE Security Standard that can provide solutions and metrics for providing appropriate security matched to the needs of a real world environment.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115107651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116250
Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, P. Adell, B. Vermeire, B. Bakkaloglu, S. Ozev
Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are also subject to higher process variations jeopardizing stable operation of the power supply. This paper presents a technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal energy being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the-shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.
{"title":"Disturbance-free BIST for loop characterization of DC-DC buck converters","authors":"Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, P. Adell, B. Vermeire, B. Bakkaloglu, S. Ozev","doi":"10.1109/VTS.2015.7116250","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116250","url":null,"abstract":"Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are also subject to higher process variations jeopardizing stable operation of the power supply. This paper presents a technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal energy being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the-shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converter's natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126331290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116281
R. Aitken, E. Cannon, M. Pant, M. Tahoori
Improvements in chip manufacturing technology, driven by high degree of integration due to small device sizes and additional complex functionalities enabled by heterogeneous integration, have propelled an astonishing growth of computing systems. While the pervasiveness of these systems enables emerging application domains, however, this trend is facing serious challenges, both at device and system levels. As the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and resiliency of embedded and critical systems. Some of these factors are caused by the stochastic nature of the nanoscale manufacturing process, while other factors appear because of high frequencies and nanoscale features. This paper overviews the vision by some of the key industrial players regarding the emerging resiliency challenges faced at the extreme nanoscale technologies.
{"title":"Resiliency challenges in sub-10nm technologies","authors":"R. Aitken, E. Cannon, M. Pant, M. Tahoori","doi":"10.1109/VTS.2015.7116281","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116281","url":null,"abstract":"Improvements in chip manufacturing technology, driven by high degree of integration due to small device sizes and additional complex functionalities enabled by heterogeneous integration, have propelled an astonishing growth of computing systems. While the pervasiveness of these systems enables emerging application domains, however, this trend is facing serious challenges, both at device and system levels. As the minimum feature size continues to shrink, a host of vulnerabilities influence the robustness, reliability, and resiliency of embedded and critical systems. Some of these factors are caused by the stochastic nature of the nanoscale manufacturing process, while other factors appear because of high frequencies and nanoscale features. This paper overviews the vision by some of the key industrial players regarding the emerging resiliency challenges faced at the extreme nanoscale technologies.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125997482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116301
Chao Han, A. Singh
Recent test studies on volume production data suggest that a significant number of CMOS open defects remain undetected by commonly applied TDF timing tests, potentially leading to high defectivity in the shipped parts. This has focused attention on developing tests that explicitly target open faults, in particular transistor stuck open faults (TSOFs). However, while TSOFs cover all open faults in circuits implemented from primitive logic gates, they do not model a type of open fault found only in complex CMOS gates. We refer to these as cross wire open (CWO) faults. In this paper, we develop the first tests that target CWOs. Although we observe that the fault list of potential CWOs can be significantly reduced if the layouts of complex gate cells used in the design are available, we present test generation methodologies both with and without this layout information. CWO fault coverage results for scan based tests are presented for ISCAS89 and ITC99 benchmark circuits that have been resynthesized using an open source cell library containing complex gates.
{"title":"Testing cross wire opens within complex gates","authors":"Chao Han, A. Singh","doi":"10.1109/VTS.2015.7116301","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116301","url":null,"abstract":"Recent test studies on volume production data suggest that a significant number of CMOS open defects remain undetected by commonly applied TDF timing tests, potentially leading to high defectivity in the shipped parts. This has focused attention on developing tests that explicitly target open faults, in particular transistor stuck open faults (TSOFs). However, while TSOFs cover all open faults in circuits implemented from primitive logic gates, they do not model a type of open fault found only in complex CMOS gates. We refer to these as cross wire open (CWO) faults. In this paper, we develop the first tests that target CWOs. Although we observe that the fault list of potential CWOs can be significantly reduced if the layouts of complex gate cells used in the design are available, we present test generation methodologies both with and without this layout information. CWO fault coverage results for scan based tests are presented for ISCAS89 and ITC99 benchmark circuits that have been resynthesized using an open source cell library containing complex gates.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131036237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-27DOI: 10.1109/VTS.2015.7116295
Nathan Debardeleben, S. Blanchard, D. Kaeli, P. Rech
Reliability is an issue for today's large scale computing systems designers, producers, and users. As we approach exascale, the resilience challenge will become critical due to increase in system-scale. It is then fundamental to understand the nature of errors, evaluate their probability of occurrence, and improve the design to reduce their impact on the overall system. In the paper we will present experimental, field, and analytical data to characterize and quantify errors on accelerators, providing a thorough understanding of errors impact on today and future large-scale systems.
{"title":"Field, experimental, and analytical data on large-scale HPC systems and evaluation of the implications for exascale system design","authors":"Nathan Debardeleben, S. Blanchard, D. Kaeli, P. Rech","doi":"10.1109/VTS.2015.7116295","DOIUrl":"https://doi.org/10.1109/VTS.2015.7116295","url":null,"abstract":"Reliability is an issue for today's large scale computing systems designers, producers, and users. As we approach exascale, the resilience challenge will become critical due to increase in system-scale. It is then fundamental to understand the nature of errors, evaluate their probability of occurrence, and improve the design to reduce their impact on the overall system. In the paper we will present experimental, field, and analytical data to characterize and quantify errors on accelerators, providing a thorough understanding of errors impact on today and future large-scale systems.","PeriodicalId":187545,"journal":{"name":"2015 IEEE 33rd VLSI Test Symposium (VTS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116461713","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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