Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585803
G. Milne
Integrated circuit verification is required to establish the correctness of a circuit design before fabrication. This paper proposes CIRCAL as a model in which to describe the behaviour of devices in a natural, concise and accurate manner. CIRCAL supports a number of verification techniques which allow for the formal analysis of circuit behaviour. Properties of the model are outlined while simulation and proof techniques using CIRCAL are presented.
{"title":"A Model for Hardware Description and Verification","authors":"G. Milne","doi":"10.1109/DAC.1984.1585803","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585803","url":null,"abstract":"Integrated circuit verification is required to establish the correctness of a circuit design before fabrication. This paper proposes CIRCAL as a model in which to describe the behaviour of devices in a natural, concise and accurate manner. CIRCAL supports a number of verification techniques which allow for the formal analysis of circuit behaviour. Properties of the model are outlined while simulation and proof techniques using CIRCAL are presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"38 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132375357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585800
M. Kawamura, H. Takagi, K. Hirabayashi
The timing simulator MACTIS was successfully applied to functional verification of MOS memory circuits from mask artwork data. The circuit description is extracted automatically from artwork data by the mask analysis program. Combining the macromodel technique and the code generation scheme, the timing simulation can be performed cost-effectively. MACTIS can handle circuits with analog features also, including bootstrapping effects, which cannot be done by logic and switch level simulators.
{"title":"Functional Verification of Memory Circuits from Mask Artwork Data","authors":"M. Kawamura, H. Takagi, K. Hirabayashi","doi":"10.1109/DAC.1984.1585800","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585800","url":null,"abstract":"The timing simulator MACTIS was successfully applied to functional verification of MOS memory circuits from mask artwork data. The circuit description is extracted automatically from artwork data by the mask analysis program. Combining the macromodel technique and the code generation scheme, the timing simulation can be performed cost-effectively. MACTIS can handle circuits with analog features also, including bootstrapping effects, which cannot be done by logic and switch level simulators.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132116721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585821
Herbert Y. Chang, R. N. Talmadge
EDS, a subsystem within AT&T Bell Laboratories Unified CAD system, is an integrated front-end computer-aided engineering system that is designed to facilitate the early detection and correction of design errors for system designers. This paper provides an overview of its system attributes and functional capabilities. EDS has been in wide use at AT&T Bell Laboratories and AT&T Information Systems Laboratory in support of the various hardware design activities associated with electronic switching systems, processors, transmission systems, and many other applications.
{"title":"Engineering Design Aspects","authors":"Herbert Y. Chang, R. N. Talmadge","doi":"10.1109/DAC.1984.1585821","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585821","url":null,"abstract":"EDS, a subsystem within AT&T Bell Laboratories Unified CAD system, is an integrated front-end computer-aided engineering system that is designed to facilitate the early detection and correction of design errors for system designers. This paper provides an overview of its system attributes and functional capabilities. EDS has been in wide use at AT&T Bell Laboratories and AT&T Information Systems Laboratory in support of the various hardware design activities associated with electronic switching systems, processors, transmission systems, and many other applications.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132336056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585771
Gary Clow
An algorithm is presented which accomplishes the global routing for a building block or general cell routing problem. A line search technique is employed and therefore no grid is assumed either for the module placements or the pin locations. Instead of breaking the routing surface up into channels, a maze search finds acceptable global routes while avoiding the blocks. Both multi-pin terminals and multi-terminal nets are accomodated. It is shown that the Lee-Moore grid-based approach is actually a special case of the general search algorithm presented. This algorithm is borrowed from the field of artificial intelligence where it has been applied to many state-space search problems.
{"title":"A Global Routing Algorithm for General Cells","authors":"Gary Clow","doi":"10.1109/DAC.1984.1585771","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585771","url":null,"abstract":"An algorithm is presented which accomplishes the global routing for a building block or general cell routing problem. A line search technique is employed and therefore no grid is assumed either for the module placements or the pin locations. Instead of breaking the routing surface up into channels, a maze search finds acceptable global routes while avoiding the blocks. Both multi-pin terminals and multi-terminal nets are accomodated. It is shown that the Lee-Moore grid-based approach is actually a special case of the general search algorithm presented. This algorithm is borrowed from the field of artificial intelligence where it has been applied to many state-space search problems.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115906445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585877
J. Blanks
It is known [1] that the optimal placement of devices on a carrier is NP-complete. So algorithms are forced to rely on heuristics in order to generate placements which are of high quality even if not globally optimal. This paper proposes the use of a metric which is the sum of the squares of the lengths of connections, for which a globally optimal assignment can be derived when overlapping components are ignored. A second placement phase maps this into a non-overlapping placement on the carrier while perturbing the derived placement as little as possible. This is essentially the metric used in [4] although not explicitly stated. However, [4] does not deal with the problems of fixed devices, IO's and other constraints which are important to VLSI design. The current paper seeks to incorporate these constraints into the model from the beginning.
{"title":"Initial Placement of Gate Arrays Using Least-Squares Methods","authors":"J. Blanks","doi":"10.1109/DAC.1984.1585877","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585877","url":null,"abstract":"It is known [1] that the optimal placement of devices on a carrier is NP-complete. So algorithms are forced to rely on heuristics in order to generate placements which are of high quality even if not globally optimal.\u0000 This paper proposes the use of a metric which is the sum of the squares of the lengths of connections, for which a globally optimal assignment can be derived when overlapping components are ignored. A second placement phase maps this into a non-overlapping placement on the carrier while perturbing the derived placement as little as possible.\u0000 This is essentially the metric used in [4] although not explicitly stated. However, [4] does not deal with the problems of fixed devices, IO's and other constraints which are important to VLSI design. The current paper seeks to incorporate these constraints into the model from the beginning.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115177210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585829
John Alan Roach
Constraint-based symbolic layout of VLSI designs has received growing attention during the past few years. Several systems have been developed which can offer graphical or textual media for the expression of designs and can provide automatic compaction to technology specific design rules. The ability of these systems to allow for the expression of more generalized relationships is a topic open for further research. RPL is a constraint-based symbolic layout language intended to address the problem of providing a more flexible set of constraints and restraints to the designer for expressing the relationships and dependencies of the design. This paper describes some of the ideas behind this work and details some of the progress that has been made.
{"title":"The Rectangle Placement Language","authors":"John Alan Roach","doi":"10.1109/DAC.1984.1585829","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585829","url":null,"abstract":"Constraint-based symbolic layout of VLSI designs has received growing attention during the past few years. Several systems have been developed which can offer graphical or textual media for the expression of designs and can provide automatic compaction to technology specific design rules. The ability of these systems to allow for the expression of more generalized relationships is a topic open for further research. RPL is a constraint-based symbolic layout language intended to address the problem of providing a more flexible set of constraints and restraints to the designer for expressing the relationships and dependencies of the design. This paper describes some of the ideas behind this work and details some of the progress that has been made.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115873057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Block Description Language (BDL), a language for capturing the structure of an electronic system, is described. The structure of a system may be specified hierarchically in this language. Additional information may be associated with the structural description with general properties. A facility for declaring and using arrays and records of the structure elements is provided.
{"title":"Block Description Language (BDL): A Structural Description Language","authors":"E. Slutz, Glen K. Okita, Jeanne Wiseman","doi":"10.5555/800033.800777","DOIUrl":"https://doi.org/10.5555/800033.800777","url":null,"abstract":"The Block Description Language (BDL), a language for capturing the structure of an electronic system, is described. The structure of a system may be specified hierarchically in this language. Additional information may be associated with the structural description with general properties. A facility for declaring and using arrays and records of the structure elements is provided.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125407052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585815
A. C. Parker, F. Kurdahi, M. Mlinar
The general relationship between register-transfer synthesis and verification is discussed, and common mechanisms are shown to underlie both tasks. The paper proposes a framework for combined synthesis and verification of hardware that supports any combination of user-selectable synthesis techniques. The synthesis process can begin with any degree of completion of a partial design, and verification of the partial design can be achieved by completing its synthesis while subjecting it to constraints that can be generated from a "template" and user constraints. The driving force was the work done by Hafer [3] on a synthesis model. The model was augmented by adding variables and constraints in order to verify interconnections. A multilevel, multidimensional design representation [6] is introduced which is shown to to be equivalent to Hafer's model. This equivalence relationship is exploited in deriving constraints off the design representation. These constraints can be manipulated in a variety of ways before being input to a linear program which completes the synthesis/verification process. An example is presented in which verification and synthesis occur simultaneously and the contribution of each automatically varies, depending on the number of previous design decisions.
{"title":"A General Methodology for Synthesis and Verification of Register-Transfer Designs","authors":"A. C. Parker, F. Kurdahi, M. Mlinar","doi":"10.1109/DAC.1984.1585815","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585815","url":null,"abstract":"The general relationship between register-transfer synthesis and verification is discussed, and common mechanisms are shown to underlie both tasks. The paper proposes a framework for combined synthesis and verification of hardware that supports any combination of user-selectable synthesis techniques. The synthesis process can begin with any degree of completion of a partial design, and verification of the partial design can be achieved by completing its synthesis while subjecting it to constraints that can be generated from a \"template\" and user constraints. The driving force was the work done by Hafer [3] on a synthesis model. The model was augmented by adding variables and constraints in order to verify interconnections. A multilevel, multidimensional design representation [6] is introduced which is shown to to be equivalent to Hafer's model. This equivalence relationship is exploited in deriving constraints off the design representation. These constraints can be manipulated in a variety of ways before being input to a linear program which completes the synthesis/verification process. An example is presented in which verification and synthesis occur simultaneously and the contribution of each automatically varies, depending on the number of previous design decisions.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126659684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585796
E. Trischler
A general overview on an Integrated Design for Testability and Automatic Test Pattern Generation System (IDAS) is given. The major components of IDAS include: heuristic controllability/observability (C/O) analysis, prediction of testing costs, tools for evaluation, display and improvement of testability, and C/O guided automatic test pattern generator. The IDAS system includes also the logic and concurrent fault simulator CADAT. A brief description of major components with a scenario how to use IDAS is given. Future research activities are discussed.
{"title":"An Integrated Design for Testability and Automatic Test Pattern Generation System: An Overview","authors":"E. Trischler","doi":"10.1109/DAC.1984.1585796","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585796","url":null,"abstract":"A general overview on an Integrated Design for Testability and Automatic Test Pattern Generation System (IDAS) is given. The major components of IDAS include: heuristic controllability/observability (C/O) analysis, prediction of testing costs, tools for evaluation, display and improvement of testability, and C/O guided automatic test pattern generator. The IDAS system includes also the logic and concurrent fault simulator CADAT. A brief description of major components with a scenario how to use IDAS is given. Future research activities are discussed.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127059303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, interest has grown in the possibility of developing a formal design verification approach as an alternative to standard simulation techniques for verification. Several researchers have used, or suggested the use of, artificial intelligence techniques in such a formal system. The purpose of this paper is to briefly describe the ongoing work on the development of a viable formal design verification system based on an automated reasoning system. This system, called LMA (Logic Machine Architecture), has been developed at Argonne National Laboratory. This paper describes the basic ideas underlying this formal system for verification and discusses several of the current research projects.
{"title":"A Formal Design Verification System Based on an Automated Reasoning System","authors":"A. S. Wojcik, J. Kljaich, N. Srinivas","doi":"10.5555/800033.800867","DOIUrl":"https://doi.org/10.5555/800033.800867","url":null,"abstract":"In recent years, interest has grown in the possibility of developing a formal design verification approach as an alternative to standard simulation techniques for verification. Several researchers have used, or suggested the use of, artificial intelligence techniques in such a formal system. The purpose of this paper is to briefly describe the ongoing work on the development of a viable formal design verification system based on an automated reasoning system. This system, called LMA (Logic Machine Architecture), has been developed at Argonne National Laboratory. This paper describes the basic ideas underlying this formal system for verification and discusses several of the current research projects.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126086810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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