Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585840
Kit Tham, Robert Willoner, David Wimp
This paper introduces Intel's functional CAD design environment and methodology. The generation of an accurate behavioral model for use in systems design validation and for comparisons with lower-level components is described. The need for both an RTL and a schematics simulator in Intel's hierarchical design methodology is explained. Finally, the paper shows how these two simulators have been linked together in two ways for two different purposes: for RTL-schematics verification, and for very large logic simulation runs.
{"title":"Functional Design Verification by Multi-Level Simulation","authors":"Kit Tham, Robert Willoner, David Wimp","doi":"10.1109/DAC.1984.1585840","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585840","url":null,"abstract":"This paper introduces Intel's functional CAD design environment and methodology. The generation of an accurate behavioral model for use in systems design validation and for comparisons with lower-level components is described. The need for both an RTL and a schematics simulator in Intel's hierarchical design methodology is explained. Finally, the paper shows how these two simulators have been linked together in two ways for two different purposes: for RTL-schematics verification, and for very large logic simulation runs.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114801612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585775
G. Odawara, Jun Sato, M. Tomita
This paper describes a new diagrammatic hardware description language SFDL (Symbolic Functional Description Language) and a hierarchical logic design supporting system LDSS (Logic Design Supporting System). SFDL has three features that help designers design logic circuits easily and speedily; easy to describe with its simple rule, comprehensible to grasp the behavior of the circuit and suitable for computer processing. Besides, the LDSS allows designers to draw diagrams without the attention to complicated drawing rule and translate the SFDL diagrams into a text-styled hardware description language. Through experiments, the effectiveness of the SFDL for hierarchical logic design has been confirmed.
{"title":"A Symbolic Functional Description Language","authors":"G. Odawara, Jun Sato, M. Tomita","doi":"10.1109/DAC.1984.1585775","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585775","url":null,"abstract":"This paper describes a new diagrammatic hardware description language SFDL (Symbolic Functional Description Language) and a hierarchical logic design supporting system LDSS (Logic Design Supporting System). SFDL has three features that help designers design logic circuits easily and speedily; easy to describe with its simple rule, comprehensible to grasp the behavior of the circuit and suitable for computer processing. Besides, the LDSS allows designers to draw diagrams without the attention to complicated drawing rule and translate the SFDL diagrams into a text-styled hardware description language. Through experiments, the effectiveness of the SFDL for hierarchical logic design has been confirmed.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115490538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585770
T. Yoshimura
In the LSI chip layout design, channel routing is one of the key problems. The problem is to route a spcified net list between two rows of terminals across a two layer channel. This paper presents a new routing algorithm, which is an improved version of the classical "left edge algorithm". The new algorithm uses a row by row approach, calculating an optimum net assignment to each row. The algorithm was implemented for examples in previously published papers. Experimental results show that the new algorithm produces optimum solutions in most cases.
{"title":"An Efficient Channel Router","authors":"T. Yoshimura","doi":"10.1109/DAC.1984.1585770","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585770","url":null,"abstract":"In the LSI chip layout design, channel routing is one of the key problems. The problem is to route a spcified net list between two rows of terminals across a two layer channel. This paper presents a new routing algorithm, which is an improved version of the classical \"left edge algorithm\". The new algorithm uses a row by row approach, calculating an optimum net assignment to each row. The algorithm was implemented for examples in previously published papers. Experimental results show that the new algorithm produces optimum solutions in most cases.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116606518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585804
R. Alali, C. Durante, J. Mercier
This paper presents a model for non interpreted structures of logical systems, i.e., structures in which neither the type of transformations nor the contents of informations are specified. Systems structures are modelled by a set of Primitive Functional Entities (PFE), while informations are represented by dynamic entities called Information Flow Entity (IFE). To compensate the role of information contents, two subjectivity attributes are associated with each IFE. An application example is given to show how the above concepts are used.
{"title":"A Model for Non Interpreted Structures of Logical Systems","authors":"R. Alali, C. Durante, J. Mercier","doi":"10.1109/DAC.1984.1585804","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585804","url":null,"abstract":"This paper presents a model for non interpreted structures of logical systems, i.e., structures in which neither the type of transformations nor the contents of informations are specified. Systems structures are modelled by a set of Primitive Functional Entities (PFE), while informations are represented by dynamic entities called Information Flow Entity (IFE). To compensate the role of information contents, two subjectivity attributes are associated with each IFE. An application example is given to show how the above concepts are used.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126456342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585890
Ola A. Marvik
A method for MOS integrated circuit layout verification based on net list extraction and logic simulation is presented. The net list elements are on the gate level or higher, defined by the user. A self developed net list extractor, NETEX, is described. NETEX is interfaced to a commercially available layout system and logic simulator. Results show that this is a fast and reliable way of connectivity checking. Limitations and further improvements are discussed.
{"title":"A Method for IC Layout Verification","authors":"Ola A. Marvik","doi":"10.1109/DAC.1984.1585890","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585890","url":null,"abstract":"A method for MOS integrated circuit layout verification based on net list extraction and logic simulation is presented. The net list elements are on the gate level or higher, defined by the user. A self developed net list extractor, NETEX, is described. NETEX is interfaced to a commercially available layout system and logic simulator. Results show that this is a fast and reliable way of connectivity checking. Limitations and further improvements are discussed.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126872987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1080/01449298408901765
G. Heiden, E. Grandjean
Although there is a large amount of research publications available on the ergonomics of Visual Display Terminals, only few authors applied human factors' thoughts in a CAD-environment. This paper describes the results of an ergonomic survey on interactive graphics workstations. Starting from an analysis of specific characteristics of CAD-operation, areas of improvement in workstation design can be deduced.
{"title":"Ergonomic Studies in Computer Aided Design","authors":"G. Heiden, E. Grandjean","doi":"10.1080/01449298408901765","DOIUrl":"https://doi.org/10.1080/01449298408901765","url":null,"abstract":"Although there is a large amount of research publications available on the ergonomics of Visual Display Terminals, only few authors applied human factors' thoughts in a CAD-environment. This paper describes the results of an ergonomic survey on interactive graphics workstations. Starting from an analysis of specific characteristics of CAD-operation, areas of improvement in workstation design can be deduced.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132636321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585780
P. A. D. Powell, M. Elmasry
A symbolic circuit design language for describing the topology and topography of a VLSI design in a simple and hierarchical manner is described. The language was intended to provide a simple manner of structuring a VLSI design, based on the Mead and Conway design methodology. Cells may be constructed from other cells and technology specific devices. Terminals for interconnecting cells are explicitly named, and may be accessed in a symbolic fashion from the language. The restriction of methods of interconnecting cells to simple abutment and specific wiring provides a simple and clear method of maintaining the connectivity of the design. The methodology proposed obviates the need for overly complex geometrical design rules. Other tools will provide design compaction, mask generation, and circuit extraction using a technology specific database and the design description.
{"title":"The Icewater Language and Interpreter","authors":"P. A. D. Powell, M. Elmasry","doi":"10.1109/DAC.1984.1585780","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585780","url":null,"abstract":"A symbolic circuit design language for describing the topology and topography of a VLSI design in a simple and hierarchical manner is described. The language was intended to provide a simple manner of structuring a VLSI design, based on the Mead and Conway design methodology. Cells may be constructed from other cells and technology specific devices. Terminals for interconnecting cells are explicitly named, and may be accessed in a symbolic fashion from the language. The restriction of methods of interconnecting cells to simple abutment and specific wiring provides a simple and clear method of maintaining the connectivity of the design. The methodology proposed obviates the need for overly complex geometrical design rules. Other tools will provide design compaction, mask generation, and circuit extraction using a technology specific database and the design description.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133220245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585870
D. Gajski
{"title":"Workshop: Silicon Compilers and Expert Systems for VLSI","authors":"D. Gajski","doi":"10.1109/DAC.1984.1585870","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585870","url":null,"abstract":"","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134427941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585782
George D. M. Ross
{"title":"Efficient Implementation of Experimental Design Systems","authors":"George D. M. Ross","doi":"10.1109/DAC.1984.1585782","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585782","url":null,"abstract":"","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121366124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585862
F. Luellau, T. Hoepken, E. Barke
Functional block extraction is a useful tool for layout verification of integrated circuits. In particular, it facilitates the network comparison problem by transfering it to a higher level of hierarchy. This paper describes a computer program called BLEX (Block Extractor), which is able to extract any given circuit block, e.g., gates, flip-flops, memory cells, differential amplifiers, darlington circuits etc., from a SPICE-like network description. The algorithm is fully technology independent. The size of the blocks is not subject to any restrictions. Descriptions of the functional blocks having the same format as the network description are supplied by the user. The circuit to be examined results usually from a preceding circuit extraction. The extractor and BLEX are part of the layout verification system ALAS (A Layout Analysis System).
功能块提取是集成电路版图验证的有效工具。特别是，它通过将网络比较问题转移到更高的层次结构来简化网络比较问题。本文描述了一个名为BLEX (Block Extractor)的计算机程序，它能够从类似spice的网络描述中提取任何给定的电路块，例如门、触发器、存储单元、差分放大器、达林顿电路等。该算法完全独立于技术。块的大小不受任何限制。与网络描述格式相同的功能块描述由用户提供。要检查的电路通常是由先前的电路提取得到的结果。提取器和BLEX是布局验证系统ALAS (A layout Analysis system)的组成部分。
{"title":"A Technology Independent Block Extraction Algorithm","authors":"F. Luellau, T. Hoepken, E. Barke","doi":"10.1109/DAC.1984.1585862","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585862","url":null,"abstract":"Functional block extraction is a useful tool for layout verification of integrated circuits. In particular, it facilitates the network comparison problem by transfering it to a higher level of hierarchy. This paper describes a computer program called BLEX (Block Extractor), which is able to extract any given circuit block, e.g., gates, flip-flops, memory cells, differential amplifiers, darlington circuits etc., from a SPICE-like network description. The algorithm is fully technology independent. The size of the blocks is not subject to any restrictions. Descriptions of the functional blocks having the same format as the network description are supplied by the user. The circuit to be examined results usually from a preceding circuit extraction. The extractor and BLEX are part of the layout verification system ALAS (A Layout Analysis System).","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124312695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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