Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585858
C. Wardle, C. R. Watson, C. A. Wilson, J. Mudge, B. Nelson
This paper describes Sprint, an IC design system. Sprint is an integrated, hierarchical approach to VLSI design. All nodes (cells) in the hierarchy are abstracted in terms of their structural, electrical, and functional properties. Cells may be of arbitrary size and aspect ratio. The relative placement of cells is specified by the designer, and signal and power routing is automatically generated. Sprint has been successfully used by a six-person team to design a 100,000 transistor chip. The chip has been fabricated in a 2.5 micron, double layer metal, HMOS process.
{"title":"A Declarative Design Approach for Combining Macrocells by Directed Placement and Constructive Routing","authors":"C. Wardle, C. R. Watson, C. A. Wilson, J. Mudge, B. Nelson","doi":"10.1109/DAC.1984.1585858","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585858","url":null,"abstract":"This paper describes Sprint, an IC design system. Sprint is an integrated, hierarchical approach to VLSI design. All nodes (cells) in the hierarchy are abstracted in terms of their structural, electrical, and functional properties. Cells may be of arbitrary size and aspect ratio. The relative placement of cells is specified by the designer, and signal and power routing is automatically generated. Sprint has been successfully used by a six-person team to design a 100,000 transistor chip. The chip has been fabricated in a 2.5 micron, double layer metal, HMOS process.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116601181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585827
B. Richard
A standard cell initial placement strategy has been developed that incorporates characteristics of both the class of algorithms that is constructive in nature (i.e., bottom-up) and the class that utilizes a top-down partitioning scheme. This approach has been pursued recognizing the fact that while both of these types of algorithms exhibit some rather adverse traits both also possess advantageous properties. Specifically, the placement strategy described in this paper incorporates both the simplicity of constructive placement methods and the global connectivity information characteristic of placement schemes involving partitioning. The specified algorithm has been implemented within the microelectronics computer-aided design facility at Sandia National Laboratories.
{"title":"A Standard Cell Initial Placement Strategy","authors":"B. Richard","doi":"10.1109/DAC.1984.1585827","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585827","url":null,"abstract":"A standard cell initial placement strategy has been developed that incorporates characteristics of both the class of algorithms that is constructive in nature (i.e., bottom-up) and the class that utilizes a top-down partitioning scheme. This approach has been pursued recognizing the fact that while both of these types of algorithms exhibit some rather adverse traits both also possess advantageous properties. Specifically, the placement strategy described in this paper incorporates both the simplicity of constructive placement methods and the global connectivity information characteristic of placement schemes involving partitioning. The specified algorithm has been implemented within the microelectronics computer-aided design facility at Sandia National Laboratories.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115054508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585880
G. Persky, L. Tran
In LSI and VLSI layout, certain categories of signal nets, e.g. critical nets, power buses and data buses, require special attention during routing. In data bus routing the goal is to maximize the commonality of the routing paths comprising the bus, without unnecessarily lengthening individual routing paths. A topological data bus router has been implemented in the Hughes Automated Layout system and is the subject of this paper.
{"title":"Topological Routing of Multi-Bit Data Buses","authors":"G. Persky, L. Tran","doi":"10.1109/DAC.1984.1585880","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585880","url":null,"abstract":"In LSI and VLSI layout, certain categories of signal nets, e.g. critical nets, power buses and data buses, require special attention during routing. In data bus routing the goal is to maximize the commonality of the routing paths comprising the bus, without unnecessarily lengthening individual routing paths. A topological data bus router has been implemented in the Hughes Automated Layout system and is the subject of this paper.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123349004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585833
M. Meyer, P. Agrawal, R. Pfister
This paper describes a fully automated finite-state machine (FSM) synthesis system. The FSM is realized as a PLA. This synthesizer accepts a high-level description of the FSM and generates a mask level layout. Several simulation models are produced at different levels of abstraction; these models can be integrated with other modules on the chip to aid in the debugging of the overall VLSI chip design. Valuable information on speed, area, and testability of the PLA can be obtained through a collection of audit programs. This system has been used to design complex controllers for many VLSI chips at AT&T Bell Laboratories. Although a PLA implementation is assumed, the system can be extended to synthesize a random logic implementation of the FSM.
{"title":"A VLSI FSM Design System","authors":"M. Meyer, P. Agrawal, R. Pfister","doi":"10.1109/DAC.1984.1585833","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585833","url":null,"abstract":"This paper describes a fully automated finite-state machine (FSM) synthesis system. The FSM is realized as a PLA. This synthesizer accepts a high-level description of the FSM and generates a mask level layout. Several simulation models are produced at different levels of abstraction; these models can be integrated with other modules on the chip to aid in the debugging of the overall VLSI chip design. Valuable information on speed, area, and testability of the PLA can be obtained through a collection of audit programs. This system has been used to design complex controllers for many VLSI chips at AT&T Bell Laboratories. Although a PLA implementation is assumed, the system can be extended to synthesize a random logic implementation of the FSM.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129615238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585878
J. Hudson, J. Wisniewski, R. Peters
A completely hierarchical approach to integrated circuit design begins by partitioning a design problem into subproblems which are based on functional boundaries. It is desirable to produce a final layout which is compact, yet preserves the functional decomposition. Allowing the physical macrocells to have arbitrary rectilinear shapes permits this goal to be achieved but introduces many levels of complexity into the modeling of the assembly. To support macrocells with rectilinear shapes, a directed graph, referred to as an adjacency graph is used to model the positional relationship of the components in the assembly. Algorithms are presented for constructing the adjacency graphs, identifying the cycles present in the adjacency graph, converting the graph to an acyclic graph, and for establishing the component and channel positions based on a critical path analysis. These algorithms are implemented in Pascal on a DECSYSTEM-20.
{"title":"Module Positioning Algorithms for Rectilinear Macrocell Assemblies","authors":"J. Hudson, J. Wisniewski, R. Peters","doi":"10.1109/DAC.1984.1585878","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585878","url":null,"abstract":"A completely hierarchical approach to integrated circuit design begins by partitioning a design problem into subproblems which are based on functional boundaries. It is desirable to produce a final layout which is compact, yet preserves the functional decomposition. Allowing the physical macrocells to have arbitrary rectilinear shapes permits this goal to be achieved but introduces many levels of complexity into the modeling of the assembly. To support macrocells with rectilinear shapes, a directed graph, referred to as an adjacency graph is used to model the positional relationship of the components in the assembly. Algorithms are presented for constructing the adjacency graphs, identifying the cycles present in the adjacency graph, converting the graph to an acyclic graph, and for establishing the component and channel positions based on a critical path analysis. These algorithms are implemented in Pascal on a DECSYSTEM-20.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130015042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585792
Gordon T. Hamachi, J. Ousterhout
Detour is the channel router used by the Magic layout system. Based on Rivest and Fiduccia's "greedy" channel router, Detour is capable of routing switchboxes and channels containing obstacles such as preexisting wiring. It jogs nets around multi-layer obstacles such as contacts, and routes over single-layer obstacles. If there are no obstacles, results are comparable to other good channel routers. Detour thus combines the effectiveness of traditional channel routers with the flexibility of net-at-a-time routers.
{"title":"A Switchbox Router with Obstacle Avoidance","authors":"Gordon T. Hamachi, J. Ousterhout","doi":"10.1109/DAC.1984.1585792","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585792","url":null,"abstract":"Detour is the channel router used by the Magic layout system. Based on Rivest and Fiduccia's \"greedy\" channel router, Detour is capable of routing switchboxes and channels containing obstacles such as preexisting wiring. It jogs nets around multi-layer obstacles such as contacts, and routes over single-layer obstacles. If there are no obstacles, results are comparable to other good channel routers. Detour thus combines the effectiveness of traditional channel routers with the flexibility of net-at-a-time routers.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128209486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585873
B. Tien, B. Ting, J. Cheam, K. Chow, Scott C. Evans
This paper describes the automatic layout software system - GALA (Gate Array Layout Automation) - developed at Hughes Aircraft Company for a high density CMOS gate array family with 3u design rules. The system layout and hierarchical decomposition schemes used in GALA are presented. The particular design environment and style are discussed. The system has been used in production for the various sizes of the Hughes HCMOS gate array family for over 2 years. Routing results for some designs produced during that period are presented.
{"title":"GALA - An Automatic Layout System for High Density CMOS Gate Arrays","authors":"B. Tien, B. Ting, J. Cheam, K. Chow, Scott C. Evans","doi":"10.1109/DAC.1984.1585873","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585873","url":null,"abstract":"This paper describes the automatic layout software system - GALA (Gate Array Layout Automation) - developed at Hughes Aircraft Company for a high density CMOS gate array family with 3u design rules. The system layout and hierarchical decomposition schemes used in GALA are presented. The particular design environment and style are discussed. The system has been used in production for the various sizes of the Hughes HCMOS gate array family for over 2 years. Routing results for some designs produced during that period are presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131892520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents fast, simple, and relatively accurate delay models for large digital MOS circuits. Delay modeling is organized around chains of switches and nodes called stages, instead of logic gates. The use of stages permits both logic gates and pass transistor arrays to be handled in a uniform fashion. Three delay models are presented, ranging from an RC model that typically errs by 25% to a slope-based model whose delay estimates are typically within 10% of SPICE's estimates. The slope model is parameterized in terms of the ratio between the slopes of a stage's input and output waveforms. All the models have been implemented in the Crystal timing analyzer. They are evaluated by comparing their delay estimates to SPICE, using a dozen critical paths from two VLSI designs.
{"title":"Switch-Level Delay Models for Digital MOS VLSI","authors":"J. Ousterhout","doi":"10.1145/62882.62941","DOIUrl":"https://doi.org/10.1145/62882.62941","url":null,"abstract":"This paper presents fast, simple, and relatively accurate delay models for large digital MOS circuits. Delay modeling is organized around chains of switches and nodes called stages, instead of logic gates. The use of stages permits both logic gates and pass transistor arrays to be handled in a uniform fashion. Three delay models are presented, ranging from an RC model that typically errs by 25% to a slope-based model whose delay estimates are typically within 10% of SPICE's estimates. The slope model is parameterized in terms of the ratio between the slopes of a stage's input and output waveforms. All the models have been implemented in the Crystal timing analyzer. They are evaluated by comparing their delay estimates to SPICE, using a dozen critical paths from two VLSI designs.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134066716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585853
Ann R. Lanfri
Caesar is an interactive graphic editor that is used to generate layouts for VLSI circuits. It runs on a VAX-11/780 under the UNIX operating system with Berkeley extensions. Caesar has a unique and simple user interface. Phled is an enhanced version of Caesar that runs on a M68000-based engineering work station. Phled45 is based on Phled; its distinctive feature is the ability to enter layout containing 45° angles. The design considerations for implementing the capability to edit 45° shapes are discussed. The details of the implementation are presented.
{"title":"PHLED45: An Enhanced Version of Caesar Supporting 45 ° Geometries","authors":"Ann R. Lanfri","doi":"10.1109/DAC.1984.1585853","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585853","url":null,"abstract":"Caesar is an interactive graphic editor that is used to generate layouts for VLSI circuits. It runs on a VAX-11/780 under the UNIX operating system with Berkeley extensions. Caesar has a unique and simple user interface. Phled is an enhanced version of Caesar that runs on a M68000-based engineering work station. Phled45 is based on Phled; its distinctive feature is the ability to enter layout containing 45° angles. The design considerations for implementing the capability to edit 45° shapes are discussed. The details of the implementation are presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131145419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585801
P. Chapman, K. Clark
Advances in integrated circuit technology in the last several years have led to designs with ever-increasing complexity and density. Consequently, designers have been faced with performing design-rule-checking on designs with shape outlines that have been doubling in number every year or two. In response, we have recently incorporated efficient algorithms into our design checking strategy. This paper reports on the computational results of these efforts.
{"title":"The Scan Line Approach to Design Rules Checking: Computational Experiences","authors":"P. Chapman, K. Clark","doi":"10.1109/DAC.1984.1585801","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585801","url":null,"abstract":"Advances in integrated circuit technology in the last several years have led to designs with ever-increasing complexity and density. Consequently, designers have been faced with performing design-rule-checking on designs with shape outlines that have been doubling in number every year or two. In response, we have recently incorporated efficient algorithms into our design checking strategy. This paper reports on the computational results of these efforts.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"338 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124310417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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