Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585778
F. Hinchliffe, R. Alessi, J. Bunik, P. Catapano, M. Kubota, R. H. Dean, E. Dorsey, M. Leddell
{"title":"Workshop - Introduction to Gate Array Placement and Routing Packages","authors":"F. Hinchliffe, R. Alessi, J. Bunik, P. Catapano, M. Kubota, R. H. Dean, E. Dorsey, M. Leddell","doi":"10.1109/DAC.1984.1585778","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585778","url":null,"abstract":"","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"45 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133228245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585872
K. Kozminski, E. Kinnen
An O(n /sup 2/) algorithm for finding a rectangular dual of a planar triangulated graph is presented. In practice, almost linear running times have been observed. The algorithm is useful for solving area planning problems in VLSI IC design.
{"title":"An Algorithm for Finding a Rectangular Dual of a Planar Graph for Use in Area Planning for VLSI Integrated Circuits","authors":"K. Kozminski, E. Kinnen","doi":"10.1109/DAC.1984.1585872","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585872","url":null,"abstract":"An O(n /sup 2/) algorithm for finding a rectangular dual of a planar triangulated graph is presented. In practice, almost linear running times have been observed. The algorithm is useful for solving area planning problems in VLSI IC design.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121950486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585854
W. Birmingham, D. Siewiorek
For some time there has been interest in automatically implementing designs described in a high level representation. This paper presents a workbench that allows a designer to describe a single board computer at the hardware requirements level and have a design produced automatically. The designs produced by the system, MICON, compare favorably to commercial designs. In comparison to manual techniques, the design time has been drastically reduced; a series of three commercial designs was reproduced in a few hours. MICON uses knowledge based engineering approaches in its implementation and is written in the OPS-5 production system language.
{"title":"MICON: A Knowledge Based Single Board Computer Designer","authors":"W. Birmingham, D. Siewiorek","doi":"10.1109/DAC.1984.1585854","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585854","url":null,"abstract":"For some time there has been interest in automatically implementing designs described in a high level representation. This paper presents a workbench that allows a designer to describe a single board computer at the hardware requirements level and have a design produced automatically. The designs produced by the system, MICON, compare favorably to commercial designs. In comparison to manual techniques, the design time has been drastically reduced; a series of three commercial designs was reproduced in a few hours. MICON uses knowledge based engineering approaches in its implementation and is written in the OPS-5 production system language.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125840337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585881
J. Crawford
The large variety of CAD/CAE tools/systems and foundry services now available to the electronic engineer have brought to a head the long-standing need for a standard format for the exchange of design information. Existing formats have not served this need for a variety of reasons. This paper describes an Electronic Design Interchange Format (EDIF) that has arisen from collaboration of the principals involved in four preceding efforts.
{"title":"An Electronic Design Interchange Format","authors":"J. Crawford","doi":"10.1109/DAC.1984.1585881","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585881","url":null,"abstract":"The large variety of CAD/CAE tools/systems and foundry services now available to the electronic engineer have brought to a head the long-standing need for a standard format for the exchange of design information. Existing formats have not served this need for a variety of reasons. This paper describes an Electronic Design Interchange Format (EDIF) that has arisen from collaboration of the principals involved in four preceding efforts.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128805797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585874
Sany M. Leinwand, Y. Lai
Previous reports [1] [3] have shown how to build an optimal floor-plan assembly starting with a planar structure graph in terms of components and their connections. The existing methods are based on exhaustively inspecting all possible rectangular duals until an optimal one is found. However, expensive computational resources are wasted when no rectangular dual exists. This paper presents a graph-theoretical formulation for the existence of rectangular floor-plans. It is shown that any triangulated graph (planar graph with all regions triangular) admits a rectangular dual if and only if it does not contain complex triangular faces. This result is the basis of a fast algorithm for checking admissibility of solutions.
{"title":"An Algorithm for Building Rectangular Floor-Plans","authors":"Sany M. Leinwand, Y. Lai","doi":"10.1109/DAC.1984.1585874","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585874","url":null,"abstract":"Previous reports [1] [3] have shown how to build an optimal floor-plan assembly starting with a planar structure graph in terms of components and their connections. The existing methods are based on exhaustively inspecting all possible rectangular duals until an optimal one is found. However, expensive computational resources are wasted when no rectangular dual exists. This paper presents a graph-theoretical formulation for the existence of rectangular floor-plans. It is shown that any triangulated graph (planar graph with all regions triangular) admits a rectangular dual if and only if it does not contain complex triangular faces. This result is the basis of a fast algorithm for checking admissibility of solutions.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127690403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585810
M. Lotvin, B. Juran, Reeni Goldin
Amoeba is an auto-interactive system which provides the chip designer with a powerful tool for cell layout. The system contains both interactive graphics tools, which give the user a great deal of control over the layout process, and highly automatic commands, which eliminate many of the tedious and error prone tasks. The designer works with a symbolic rather than physical data representation which allows for easier construction of complex designs.
{"title":"AMOEBA: A Symbolic VLSI Layout System","authors":"M. Lotvin, B. Juran, Reeni Goldin","doi":"10.1109/DAC.1984.1585810","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585810","url":null,"abstract":"Amoeba is an auto-interactive system which provides the chip designer with a powerful tool for cell layout. The system contains both interactive graphics tools, which give the user a great deal of control over the layout process, and highly automatic commands, which eliminate many of the tedious and error prone tasks. The designer works with a symbolic rather than physical data representation which allows for easier construction of complex designs.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117323719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585864
J. Kors, M. Israel
Simulation, interconnection verification, design Rules Checking, need a data base corresponding to the electrical graph of the circuit layout to be verified. We present an interactive electrical graph extractor, based on EMILIE2 CAD system working during the layout design and avoiding the use of an off line extractor.
{"title":"An Interactive Electrical Graph Extractor","authors":"J. Kors, M. Israel","doi":"10.1109/DAC.1984.1585864","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585864","url":null,"abstract":"Simulation, interconnection verification, design Rules Checking, need a data base corresponding to the electrical graph of the circuit layout to be verified. We present an interactive electrical graph extractor, based on EMILIE2 CAD system working during the layout design and avoiding the use of an off line extractor.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124483141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585781
C. Lursinsap, D. Gajski
This paper describes a cell compiler that translates cell descriptions given in form of Boolean equations including pass transistors into layout descriptions in Caltech Intermediate Form (CIF). The translation process is constrained by given height and width of the cell and the position of each I/O signal on the boundary of the cell. Furthermore, the size of each transistor as well as power consumption can be arbitrarily chosen. This cell compiler allows routing through the cell in any direction. The cell architecture is based on PLA structures.
{"title":"Cell Compilation with Constraints","authors":"C. Lursinsap, D. Gajski","doi":"10.1109/DAC.1984.1585781","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585781","url":null,"abstract":"This paper describes a cell compiler that translates cell descriptions given in form of Boolean equations including pass transistors into layout descriptions in Caltech Intermediate Form (CIF). The translation process is constrained by given height and width of the cell and the position of each I/O signal on the boundary of the cell. Furthermore, the size of each transistor as well as power consumption can be arbitrarily chosen. This cell compiler allows routing through the cell in any direction. The cell architecture is based on PLA structures.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"412 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124401011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
STAtistical Fault ANalysis (STAFAN) is proposed as an alternative to fault simulation of digital circuits. In this analysis, controllabilities and observabilities of circuit nodes are defined as probabilities which are estimated from signal statistics obtained from fault-free simulation. Special procedures are developed for dealing with these quantities at fanout nodes and at feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Fault coverage and the undetected fault data obtained from STAFAN for actual circuits are shown to agree favorably with the fault simulator results. The computational complexity added to a fault-free simulator by STAFAN grows only linearly with the number of circuit nodes.
{"title":"STAFAN: An Alternative to Fault Simulation","authors":"Sunil K. Jain, V. Agrawal","doi":"10.1145/62882.62939","DOIUrl":"https://doi.org/10.1145/62882.62939","url":null,"abstract":"STAtistical Fault ANalysis (STAFAN) is proposed as an alternative to fault simulation of digital circuits. In this analysis, controllabilities and observabilities of circuit nodes are defined as probabilities which are estimated from signal statistics obtained from fault-free simulation. Special procedures are developed for dealing with these quantities at fanout nodes and at feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Fault coverage and the undetected fault data obtained from STAFAN for actual circuits are shown to agree favorably with the fault simulator results. The computational complexity added to a fault-free simulator by STAFAN grows only linearly with the number of circuit nodes.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121624007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585863
S. McCormick
This paper describes EXCL, an automated circuit extraction program that transforms an IC layout into a circuit representation suitable for detailed circuit simulation. The program has built-in, general extraction algorithms capable of accurate computations of interconnection resistance, internodal capacitance, ground capacitance, and transistor sizes. However, where possible, the general algorithms are replaced with simple techniques, thereby improving execution speed. A basic component of the extractor is a procedure that decomposes regions into domains appropriate for specialized or simple algorithms. The paper describes the decomposition algorithm, the extraction algorithms and discusses how they connect with the rest of EXCL.
{"title":"EXCL: A Circuit Extractor for IC Designs","authors":"S. McCormick","doi":"10.1109/DAC.1984.1585863","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585863","url":null,"abstract":"This paper describes EXCL, an automated circuit extraction program that transforms an IC layout into a circuit representation suitable for detailed circuit simulation. The program has built-in, general extraction algorithms capable of accurate computations of interconnection resistance, internodal capacitance, ground capacitance, and transistor sizes. However, where possible, the general algorithms are replaced with simple techniques, thereby improving execution speed. A basic component of the extractor is a procedure that decomposes regions into domains appropriate for specialized or simple algorithms. The paper describes the decomposition algorithm, the extraction algorithms and discusses how they connect with the rest of EXCL.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122176085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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