M. Ozaki, Miho Watanabe, M. Kakinuma, M. Ikeda, Koji Sato
A symbolic layout system for double-metal silicon-gate MOS technology in the style of Gate Matrix is presented. This system provides an integrated layout environment which consists of stick-figure-based graphic editor, a mask artwork generator, a connectivity checker, a circuit parameter extracter and simulator interfaces. All the modules are designed to deal with symbol data, rather than mask artwork, so that fast execution is realized. A method to associate symbol data with actual mask geometry is described along with the data structure employed. Also described is network partitioning by signal names taking into account logical equivalence of transistor circuits.
{"title":"MGX: An Integrated Symbolic Layout System for VLSI","authors":"M. Ozaki, Miho Watanabe, M. Kakinuma, M. Ikeda, Koji Sato","doi":"10.5555/800033.800855","DOIUrl":"https://doi.org/10.5555/800033.800855","url":null,"abstract":"A symbolic layout system for double-metal silicon-gate MOS technology in the style of Gate Matrix is presented. This system provides an integrated layout environment which consists of stick-figure-based graphic editor, a mask artwork generator, a connectivity checker, a circuit parameter extracter and simulator interfaces. All the modules are designed to deal with symbol data, rather than mask artwork, so that fast execution is realized. A method to associate symbol data with actual mask geometry is described along with the data structure employed. Also described is network partitioning by signal names taking into account logical equivalence of transistor circuits.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129665529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585807
B. Jackson
This paper reports on the development of a computer program, SYSBLD2, which generates passive solar designs for multi-family housing from a database of apartment plans, their components, and their associated economic and energy analysis. Although the program has been designed to be generic, the plans are associated with a precast concrete modular housing system. The program development acts as a framework for re-evaluation and modification of an industrialized housing system to include passive or low energy technology. Design criteria are established as objective functions which are linked to analytical programs and files in the database. The program utilizes the record structure of PASCAL to provide its data structure. Data input is interactive using a keyboard or digitizer; output is graphic or numeric.
{"title":"A Designing System for Multi-Family Housing","authors":"B. Jackson","doi":"10.1109/DAC.1984.1585807","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585807","url":null,"abstract":"This paper reports on the development of a computer program, SYSBLD2, which generates passive solar designs for multi-family housing from a database of apartment plans, their components, and their associated economic and energy analysis. Although the program has been designed to be generic, the plans are associated with a precast concrete modular housing system. The program development acts as a framework for re-evaluation and modification of an industrialized housing system to include passive or low energy technology. Design criteria are established as objective functions which are linked to analytical programs and files in the database. The program utilizes the record structure of PASCAL to provide its data structure. Data input is interactive using a keyboard or digitizer; output is graphic or numeric.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130145823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585886
S. Trimberger
VTIcompose is a graphical chip assembly tool. It is designed to ease the assembly of large-scale custom chips in a hierarchical manner, leaving the detailed cell design to other tools in the system. VTIcompose supports both manual and automatic placement and interconnection, with commands and data structures applicable to both exact placement and symbolic style layout. The wide range of commands allows VTIcompose to support a wide range of chip design styles.
{"title":"VTIcompose - A Powerful Graphical Chip Assembly Tool","authors":"S. Trimberger","doi":"10.1109/DAC.1984.1585886","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585886","url":null,"abstract":"VTIcompose is a graphical chip assembly tool. It is designed to ease the assembly of large-scale custom chips in a hierarchical manner, leaving the detailed cell design to other tools in the system. VTIcompose supports both manual and automatic placement and interconnection, with commands and data structures applicable to both exact placement and symbolic style layout. The wide range of commands allows VTIcompose to support a wide range of chip design styles.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120927204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585817
M. d'Abreu, K. L. Cheong, C. T. Flanagan
This paper describes a logic simulation system that supports both Bipolar as well as MOS IC design. Some of the underlying concepts implemented in this system, which also supports mixed-level simulation, are described. A brief discussion of the basic Current Mode Logic (CML) primitives, simulation algorithms and basic data structures will also be presented.
{"title":"ORACLE - A Simulator for Bipolar and MOS IC Design","authors":"M. d'Abreu, K. L. Cheong, C. T. Flanagan","doi":"10.1109/DAC.1984.1585817","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585817","url":null,"abstract":"This paper describes a logic simulation system that supports both Bipolar as well as MOS IC design. Some of the underlying concepts implemented in this system, which also supports mixed-level simulation, are described. A brief discussion of the basic Current Mode Logic (CML) primitives, simulation algorithms and basic data structures will also be presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121134889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585837
H. D. Schnurmann, L. J. Vidunas, R. M. Peters
This paper describes a software system for testing LSI memory chips. This system achieves complete automation by customizing test data for a given part number design and by creating an overall test program to be used by a computer-controlled tester in a manufacturing environment. This system encompasses DC testing of the memory product and test sites, AC testing under a variety of timing conditions, and generating a complete set of AC functional test patterns.
{"title":"An Automated System for Testing LSI Memory Chips","authors":"H. D. Schnurmann, L. J. Vidunas, R. M. Peters","doi":"10.1109/DAC.1984.1585837","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585837","url":null,"abstract":"This paper describes a software system for testing LSI memory chips. This system achieves complete automation by customizing test data for a given part number design and by creating an overall test program to be used by a computer-controlled tester in a manufacturing environment. This system encompasses DC testing of the memory product and test sites, AC testing under a variety of timing conditions, and generating a complete set of AC functional test patterns.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116479413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585805
K. Lieberherr
General requirements for hardware description languages are defined. The hardware description language Zeus is claimed to satisfy most of these requirements. Zeus is summarized and briefly compared to other hardware description languages. The expressiveness of Zeus is demonstrated on designs for music generation, comparison and unary-to-binary conversion.
{"title":"Towards a Standard Hardware Description Language","authors":"K. Lieberherr","doi":"10.1109/DAC.1984.1585805","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585805","url":null,"abstract":"General requirements for hardware description languages are defined. The hardware description language Zeus is claimed to satisfy most of these requirements. Zeus is summarized and briefly compared to other hardware description languages. The expressiveness of Zeus is demonstrated on designs for music generation, comparison and unary-to-binary conversion.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125705759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585768
Mahesh H. Doshi, R. B. Sullivan, Donald M. Schuler
A new logic simulator called THEMIS (TM) Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level. To allow the simulation of an entire system or check the correctness of a single circuit, the different modeling techniques can be easily intermixed. THEMIS is a highly interactive simulator that minimizes a hardware engineer's time and effort to debug logic. This paper gives an overview of THEMIS and its use by design engineers.
{"title":"THEMIS Logic Simulator - A Mix Mode, Multi-Level, Hierarchical, Interactive Digital Circuit Simulator","authors":"Mahesh H. Doshi, R. B. Sullivan, Donald M. Schuler","doi":"10.1109/DAC.1984.1585768","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585768","url":null,"abstract":"A new logic simulator called THEMIS (TM) Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level. To allow the simulation of an entire system or check the correctness of a single circuit, the different modeling techniques can be easily intermixed. THEMIS is a highly interactive simulator that minimizes a hardware engineer's time and effort to debug logic. This paper gives an overview of THEMIS and its use by design engineers.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126415841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585869
A. Zingale
The semicustom IC market, has exploded during the past few years (figure 1). Comprised of both gate arrays and standard cells, the market spans the range of IC technologies including bipolar, CMOS and linear. To meet the needs of the system engineers who implement semicustom designs, CAE tools have become increasingly important and more focused with respect to rapid, right-the-first-time product development. Panelists will discuss their company's semi-custom design automation solution in relation to the semicustom silicon vendor and the users of various semicustom designs and technologies. The session will close with a discussion on the future of CAE tools and the evolution of the semicustom market into standard cells and fullcustom design.
{"title":"The Semi-Custom Revolution: How To Thrive or Survive","authors":"A. Zingale","doi":"10.1109/DAC.1984.1585869","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585869","url":null,"abstract":"The semicustom IC market, has exploded during the past few years (figure 1). Comprised of both gate arrays and standard cells, the market spans the range of IC technologies including bipolar, CMOS and linear. To meet the needs of the system engineers who implement semicustom designs, CAE tools have become increasingly important and more focused with respect to rapid, right-the-first-time product development. Panelists will discuss their company's semi-custom design automation solution in relation to the semicustom silicon vendor and the users of various semicustom designs and technologies. The session will close with a discussion on the future of CAE tools and the evolution of the semicustom market into standard cells and fullcustom design.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127517035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585784
L. Hollaar, B. Nelson, Tony M. Carter, R. Lorie
An important use for a database management system is in the storage and handling of information for engineering design, particularly integrated circuit design. However, most discussions on this topic have concentrated on the layout of shapes necessary to form the various circuit elements, or connections between user-defined cells. Equally important, but often disregarded, is the necessity to support other design tools in addition to graphics for circuit layout. These include simulators and automatic layout programs that take a description of a circuit at one level and convert it to a lower level. In addition, if cells are part of a library defined and maintained by others, operations must be included to handle the maintenance of generations or versions of a cell design. These aspects of a database management system for engineering design are discussed in light of the tools being developed at the University of Utah and an extended version of System R, developed at the IBM San Jose Research Laboratory. The Utah approach emphasizes the use of previously designed and tested cells, with interconnects at fixed locations, placed on a grid. Because it is unlikely that the designers of circuits designed all (or any) of the cells used in their circuits, special database management operations are necessary to assure that a consistent, working circuit results.
{"title":"The Structure and Operation of a Relational Database System in a Cell-Oriented Integrated Circuit Design System","authors":"L. Hollaar, B. Nelson, Tony M. Carter, R. Lorie","doi":"10.1109/DAC.1984.1585784","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585784","url":null,"abstract":"An important use for a database management system is in the storage and handling of information for engineering design, particularly integrated circuit design. However, most discussions on this topic have concentrated on the layout of shapes necessary to form the various circuit elements, or connections between user-defined cells. Equally important, but often disregarded, is the necessity to support other design tools in addition to graphics for circuit layout. These include simulators and automatic layout programs that take a description of a circuit at one level and convert it to a lower level. In addition, if cells are part of a library defined and maintained by others, operations must be included to handle the maintenance of generations or versions of a cell design. These aspects of a database management system for engineering design are discussed in light of the tools being developed at the University of Utah and an extended version of System R, developed at the IBM San Jose Research Laboratory. The Utah approach emphasizes the use of previously designed and tested cells, with interconnects at fixed locations, placed on a grid. Because it is unlikely that the designers of circuits designed all (or any) of the cells used in their circuits, special database management operations are necessary to assure that a consistent, working circuit results.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"439 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127603223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we describe functional testing techniques for detecting single stuck-at faults in a microprocessor. These techniques appear to be practical in that a relatively small number of machine language instructions is needed in the programs which implement them, the number of reference outputs which must be stored is small, and hardware redundancy for testing purposes is not needed. The efficacy of use of these functional testing techniques has been demonstrated by applying them to the testing of a simulated 4-bit microprocessor with simulated single stuck-at faults.
{"title":"An Approach to the Testing of Microprocessors","authors":"M. Karpovsky, R. V. Meter","doi":"10.5555/800033.800795","DOIUrl":"https://doi.org/10.5555/800033.800795","url":null,"abstract":"In this paper, we describe functional testing techniques for detecting single stuck-at faults in a microprocessor. These techniques appear to be practical in that a relatively small number of machine language instructions is needed in the programs which implement them, the number of reference outputs which must be stored is small, and hardware redundancy for testing purposes is not needed. The efficacy of use of these functional testing techniques has been demonstrated by applying them to the testing of a simulated 4-bit microprocessor with simulated single stuck-at faults.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"03 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129165740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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