Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585803
G. Milne
Integrated circuit verification is required to establish the correctness of a circuit design before fabrication. This paper proposes CIRCAL as a model in which to describe the behaviour of devices in a natural, concise and accurate manner. CIRCAL supports a number of verification techniques which allow for the formal analysis of circuit behaviour. Properties of the model are outlined while simulation and proof techniques using CIRCAL are presented.
{"title":"A Model for Hardware Description and Verification","authors":"G. Milne","doi":"10.1109/DAC.1984.1585803","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585803","url":null,"abstract":"Integrated circuit verification is required to establish the correctness of a circuit design before fabrication. This paper proposes CIRCAL as a model in which to describe the behaviour of devices in a natural, concise and accurate manner. CIRCAL supports a number of verification techniques which allow for the formal analysis of circuit behaviour. Properties of the model are outlined while simulation and proof techniques using CIRCAL are presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"38 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132375357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we describe functional testing techniques for detecting single stuck-at faults in a microprocessor. These techniques appear to be practical in that a relatively small number of machine language instructions is needed in the programs which implement them, the number of reference outputs which must be stored is small, and hardware redundancy for testing purposes is not needed. The efficacy of use of these functional testing techniques has been demonstrated by applying them to the testing of a simulated 4-bit microprocessor with simulated single stuck-at faults.
{"title":"An Approach to the Testing of Microprocessors","authors":"M. Karpovsky, R. V. Meter","doi":"10.5555/800033.800795","DOIUrl":"https://doi.org/10.5555/800033.800795","url":null,"abstract":"In this paper, we describe functional testing techniques for detecting single stuck-at faults in a microprocessor. These techniques appear to be practical in that a relatively small number of machine language instructions is needed in the programs which implement them, the number of reference outputs which must be stored is small, and hardware redundancy for testing purposes is not needed. The efficacy of use of these functional testing techniques has been demonstrated by applying them to the testing of a simulated 4-bit microprocessor with simulated single stuck-at faults.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"03 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129165740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585821
Herbert Y. Chang, R. N. Talmadge
EDS, a subsystem within AT&T Bell Laboratories Unified CAD system, is an integrated front-end computer-aided engineering system that is designed to facilitate the early detection and correction of design errors for system designers. This paper provides an overview of its system attributes and functional capabilities. EDS has been in wide use at AT&T Bell Laboratories and AT&T Information Systems Laboratory in support of the various hardware design activities associated with electronic switching systems, processors, transmission systems, and many other applications.
{"title":"Engineering Design Aspects","authors":"Herbert Y. Chang, R. N. Talmadge","doi":"10.1109/DAC.1984.1585821","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585821","url":null,"abstract":"EDS, a subsystem within AT&T Bell Laboratories Unified CAD system, is an integrated front-end computer-aided engineering system that is designed to facilitate the early detection and correction of design errors for system designers. This paper provides an overview of its system attributes and functional capabilities. EDS has been in wide use at AT&T Bell Laboratories and AT&T Information Systems Laboratory in support of the various hardware design activities associated with electronic switching systems, processors, transmission systems, and many other applications.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132336056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585817
M. d'Abreu, K. L. Cheong, C. T. Flanagan
This paper describes a logic simulation system that supports both Bipolar as well as MOS IC design. Some of the underlying concepts implemented in this system, which also supports mixed-level simulation, are described. A brief discussion of the basic Current Mode Logic (CML) primitives, simulation algorithms and basic data structures will also be presented.
{"title":"ORACLE - A Simulator for Bipolar and MOS IC Design","authors":"M. d'Abreu, K. L. Cheong, C. T. Flanagan","doi":"10.1109/DAC.1984.1585817","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585817","url":null,"abstract":"This paper describes a logic simulation system that supports both Bipolar as well as MOS IC design. Some of the underlying concepts implemented in this system, which also supports mixed-level simulation, are described. A brief discussion of the basic Current Mode Logic (CML) primitives, simulation algorithms and basic data structures will also be presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121134889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585837
H. D. Schnurmann, L. J. Vidunas, R. M. Peters
This paper describes a software system for testing LSI memory chips. This system achieves complete automation by customizing test data for a given part number design and by creating an overall test program to be used by a computer-controlled tester in a manufacturing environment. This system encompasses DC testing of the memory product and test sites, AC testing under a variety of timing conditions, and generating a complete set of AC functional test patterns.
{"title":"An Automated System for Testing LSI Memory Chips","authors":"H. D. Schnurmann, L. J. Vidunas, R. M. Peters","doi":"10.1109/DAC.1984.1585837","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585837","url":null,"abstract":"This paper describes a software system for testing LSI memory chips. This system achieves complete automation by customizing test data for a given part number design and by creating an overall test program to be used by a computer-controlled tester in a manufacturing environment. This system encompasses DC testing of the memory product and test sites, AC testing under a variety of timing conditions, and generating a complete set of AC functional test patterns.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116479413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585772
Charles H. Ng
The router described in this paper is part of a complete CAD system which aims at hierarchical designs of customized VLSI MOS circuits. It routes global signals as symbolic interconnect and is guaranteed to complete all routing in one pass. The router is fully automatic as well as highly interactive. It employs the novel idea of bouyancy and produces wires with a natural bus structure. The router is fully operational, and has been used in routing a number of real-world integrated circuits.
{"title":"A Symbolic-Interconnect Router for Custom IC Design","authors":"Charles H. Ng","doi":"10.1109/DAC.1984.1585772","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585772","url":null,"abstract":"The router described in this paper is part of a complete CAD system which aims at hierarchical designs of customized VLSI MOS circuits. It routes global signals as symbolic interconnect and is guaranteed to complete all routing in one pass. The router is fully automatic as well as highly interactive. It employs the novel idea of bouyancy and produces wires with a natural bus structure. The router is fully operational, and has been used in routing a number of real-world integrated circuits.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114991804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585847
S. Su, Tonysheng Lin
Functional testing is becomilng more important due to the increasing complexity in digital LSI/VLSI devices. Various functional testing approaches have been proposed to meet this urgent need in LSI/VLSI testing. This paper presents the basic ideas behind deterministic functional testing and concisely overviews eight major functional testing techniques. Comparisons among these techniques and suggestions for future development are made to meet the challenges in this fast growing testing field.
{"title":"Functional Testing Techniques for Digital LSI/VLSI Systems","authors":"S. Su, Tonysheng Lin","doi":"10.1109/DAC.1984.1585847","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585847","url":null,"abstract":"Functional testing is becomilng more important due to the increasing complexity in digital LSI/VLSI devices. Various functional testing approaches have been proposed to meet this urgent need in LSI/VLSI testing. This paper presents the basic ideas behind deterministic functional testing and concisely overviews eight major functional testing techniques. Comparisons among these techniques and suggestions for future development are made to meet the challenges in this fast growing testing field.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114524028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585768
Mahesh H. Doshi, R. B. Sullivan, Donald M. Schuler
A new logic simulator called THEMIS (TM) Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level. To allow the simulation of an entire system or check the correctness of a single circuit, the different modeling techniques can be easily intermixed. THEMIS is a highly interactive simulator that minimizes a hardware engineer's time and effort to debug logic. This paper gives an overview of THEMIS and its use by design engineers.
{"title":"THEMIS Logic Simulator - A Mix Mode, Multi-Level, Hierarchical, Interactive Digital Circuit Simulator","authors":"Mahesh H. Doshi, R. B. Sullivan, Donald M. Schuler","doi":"10.1109/DAC.1984.1585768","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585768","url":null,"abstract":"A new logic simulator called THEMIS (TM) Logic Simulator for the design of LSI, VLSI and PCBs is described. THEMIS supports design verification and test development from initial specification in behavioral and RTL languages to analysis of the final layout at the gate and switch level. To allow the simulation of an entire system or check the correctness of a single circuit, the different modeling techniques can be easily intermixed. THEMIS is a highly interactive simulator that minimizes a hardware engineer's time and effort to debug logic. This paper gives an overview of THEMIS and its use by design engineers.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126415841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585869
A. Zingale
The semicustom IC market, has exploded during the past few years (figure 1). Comprised of both gate arrays and standard cells, the market spans the range of IC technologies including bipolar, CMOS and linear. To meet the needs of the system engineers who implement semicustom designs, CAE tools have become increasingly important and more focused with respect to rapid, right-the-first-time product development. Panelists will discuss their company's semi-custom design automation solution in relation to the semicustom silicon vendor and the users of various semicustom designs and technologies. The session will close with a discussion on the future of CAE tools and the evolution of the semicustom market into standard cells and fullcustom design.
{"title":"The Semi-Custom Revolution: How To Thrive or Survive","authors":"A. Zingale","doi":"10.1109/DAC.1984.1585869","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585869","url":null,"abstract":"The semicustom IC market, has exploded during the past few years (figure 1). Comprised of both gate arrays and standard cells, the market spans the range of IC technologies including bipolar, CMOS and linear. To meet the needs of the system engineers who implement semicustom designs, CAE tools have become increasingly important and more focused with respect to rapid, right-the-first-time product development. Panelists will discuss their company's semi-custom design automation solution in relation to the semicustom silicon vendor and the users of various semicustom designs and technologies. The session will close with a discussion on the future of CAE tools and the evolution of the semicustom market into standard cells and fullcustom design.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127517035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585886
S. Trimberger
VTIcompose is a graphical chip assembly tool. It is designed to ease the assembly of large-scale custom chips in a hierarchical manner, leaving the detailed cell design to other tools in the system. VTIcompose supports both manual and automatic placement and interconnection, with commands and data structures applicable to both exact placement and symbolic style layout. The wide range of commands allows VTIcompose to support a wide range of chip design styles.
{"title":"VTIcompose - A Powerful Graphical Chip Assembly Tool","authors":"S. Trimberger","doi":"10.1109/DAC.1984.1585886","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585886","url":null,"abstract":"VTIcompose is a graphical chip assembly tool. It is designed to ease the assembly of large-scale custom chips in a hierarchical manner, leaving the detailed cell design to other tools in the system. VTIcompose supports both manual and automatic placement and interconnection, with commands and data structures applicable to both exact placement and symbolic style layout. The wide range of commands allows VTIcompose to support a wide range of chip design styles.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120927204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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