Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585848
L. Glasser, L. Hoyte
The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macro-models are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.
{"title":"Delay and Power Optimization in VLSI Circuits","authors":"L. Glasser, L. Hoyte","doi":"10.1109/DAC.1984.1585848","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585848","url":null,"abstract":"The problem of optimally sizing the transistors in a digital MOS VLSI circuit is examined. Macro-models are developed and new theorems on the optimal sizing of the transistors in a critical path are presented. The results of a design automation procedure to perform the optimization is discussed.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125812852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585828
M. Palczewski
This paper analyzes the performance of a commonly used class of methods for initial placement and describes several new classes. The classification in this paper is based on common methods of problem-solving used in artificial intelligence (AI) approaches. The paper does not describe the details of algorithms; instead it focuses on the qualitative performance.
{"title":"Performance of Algorithms for Initial Placement","authors":"M. Palczewski","doi":"10.1109/DAC.1984.1585828","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585828","url":null,"abstract":"This paper analyzes the performance of a commonly used class of methods for initial placement and describes several new classes. The classification in this paper is based on common methods of problem-solving used in artificial intelligence (AI) approaches. The paper does not describe the details of algorithms; instead it focuses on the qualitative performance.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127276304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585774
W. H. Evans, J. Ballegeer, Nguyen H. Duyet
The Algorithmic Design Language (ADL), provides a means to procedurally describe the functional, circuit, schematic and mask aspects of integrated circuits. The constructs of this language have been coded in the C language and are intended for application to IC design. C programs that incorporate ADL routines are executed to build a data base from which CIF files, input files to circuit simulation programs or a textual representation of ADL's own highly structured data base can be generated.
{"title":"ADL: An Algorithmic Design Language for Integrated Circuit Synthesis","authors":"W. H. Evans, J. Ballegeer, Nguyen H. Duyet","doi":"10.1109/DAC.1984.1585774","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585774","url":null,"abstract":"The Algorithmic Design Language (ADL), provides a means to procedurally describe the functional, circuit, schematic and mask aspects of integrated circuits. The constructs of this language have been coded in the C language and are intended for application to IC design. C programs that incorporate ADL routines are executed to build a data base from which CIF files, input files to circuit simulation programs or a textual representation of ADL's own highly structured data base can be generated.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123698758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585838
Stephen Nachtsheim
The Intel Design Automation (DA) System is overviewed within the framework of Intel's business and technological goals. The philosophies and goals that direct development, acquisition, and deployment of DA capabilities throughout Intel are provided as a foundation for a more detailed discussion of specific areas within the total DA system. The "computing hierarchy" used within Intel world-wide for design and verification of its products is presented, as well as a high-level picture of the entire DA system for Intel's components products mix. With this overview as a basis, detailed explanations of the Engineering Design Environment (EDeN), Functional Design Verification, Hierarchical Layout Verification, and Circuit Performance Verification are presented.
{"title":"The Intel Design Automation System","authors":"Stephen Nachtsheim","doi":"10.1109/DAC.1984.1585838","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585838","url":null,"abstract":"The Intel Design Automation (DA) System is overviewed within the framework of Intel's business and technological goals. The philosophies and goals that direct development, acquisition, and deployment of DA capabilities throughout Intel are provided as a foundation for a more detailed discussion of specific areas within the total DA system. The \"computing hierarchy\" used within Intel world-wide for design and verification of its products is presented, as well as a high-level picture of the entire DA system for Intel's components products mix. With this overview as a basis, detailed explanations of the Engineering Design Environment (EDeN), Functional Design Verification, Hierarchical Layout Verification, and Circuit Performance Verification are presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131564218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585889
C. Jhon, R. Keller
One means of making VLSI design tractable is to proceed from a high-level specification of a circuit in terms of functionality, to the circuit level. A notable error which may occur in a topdown design starting with a data-flow graph representation of a circuit is a design inconsistency due to deadlock. This paper attempts to further develop the theoretical basis for algorithms which analyze the deadlock property of circuits on the basis of their data-flow graph representations. A systematic scheme to verify the absence of deadlock in data-flow graphs is also presented.
{"title":"Deadlock Analysis in the Design of Data-Flow Circuits","authors":"C. Jhon, R. Keller","doi":"10.1109/DAC.1984.1585889","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585889","url":null,"abstract":"One means of making VLSI design tractable is to proceed from a high-level specification of a circuit in terms of functionality, to the circuit level. A notable error which may occur in a topdown design starting with a data-flow graph representation of a circuit is a design inconsistency due to deadlock. This paper attempts to further develop the theoretical basis for algorithms which analyze the deadlock property of circuits on the basis of their data-flow graph representations. A systematic scheme to verify the absence of deadlock in data-flow graphs is also presented.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"29 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125694669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585788
Paul W. Horstmann, E. Stabler
This paper gives an overview of expert systems and logic programming as applied to Computer-Aided Design (CAD) systems. Our objective is to show the relevance of these two approaches developed from research in artificial intelligence for the solution of problems in VLSI design. We will provide some examples of the use of logic programming for familiar CAD tasks. The expert systems discussed function as experts in a very narrowly defined area of expertise, and can be called designer's assistants. We will also compare the use of logic programming (PROLOG) to current algorithmic solutions to VLSI design problems and discuss some future research in this area.
{"title":"Computer Aided Design (CAD) Using Logic Programming","authors":"Paul W. Horstmann, E. Stabler","doi":"10.1109/DAC.1984.1585788","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585788","url":null,"abstract":"This paper gives an overview of expert systems and logic programming as applied to Computer-Aided Design (CAD) systems. Our objective is to show the relevance of these two approaches developed from research in artificial intelligence for the solution of problems in VLSI design. We will provide some examples of the use of logic programming for familiar CAD tasks. The expert systems discussed function as experts in a very narrowly defined area of expertise, and can be called designer's assistants. We will also compare the use of logic programming (PROLOG) to current algorithmic solutions to VLSI design problems and discuss some future research in this area.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128241963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A channel model for routing double-layer cell arrays is presented. A switch-box is defined as an overlapping area of a horizontal channel and a vertical channel. Along the sides of switch-boxes, dynamic terminals are generated by the loose router and moved by the final router. A channel router, that is an extension of the "Dogleg Channel Router" introduced by D.N. Deutsch in 1976, is described.
{"title":"A Wire Routing Scheme for Double-Layer Cell Arrays","authors":"G. Dupenloup","doi":"10.5555/800033.800770","DOIUrl":"https://doi.org/10.5555/800033.800770","url":null,"abstract":"A channel model for routing double-layer cell arrays is presented. A switch-box is defined as an overlapping area of a horizontal channel and a vertical channel. Along the sides of switch-boxes, dynamic terminals are generated by the loose router and moved by the final router. A channel router, that is an extension of the \"Dogleg Channel Router\" introduced by D.N. Deutsch in 1976, is described.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130427827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585846
K. Lieberherr
Random testing uses random inputs to test digital circuits. A major problem in random testing is the cost to compute the test length which is required for achieving an acceptable fault coverage. Different input distributions on the random inputs produce different fault detection probabilities. Therefore parameterized input distributions are analyzed and analytical methods are given for computing the fault coverage as a function of the parameters. The parameters are chosen so that the fault detection probability is maximized and the test pattern length is minimized. This analytical method of analyzing random test patterns tends to be faster than fault simulation.
{"title":"Parameterized Random Testing","authors":"K. Lieberherr","doi":"10.1109/DAC.1984.1585846","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585846","url":null,"abstract":"Random testing uses random inputs to test digital circuits. A major problem in random testing is the cost to compute the test length which is required for achieving an acceptable fault coverage. Different input distributions on the random inputs produce different fault detection probabilities. Therefore parameterized input distributions are analyzed and analytical methods are given for computing the fault coverage as a function of the parameters. The parameters are chosen so that the fault detection probability is maximized and the test pattern length is minimized. This analytical method of analyzing random test patterns tends to be faster than fault simulation.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134026401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585843
C. Bellon, R. Velazco
The proposed functional test method for complex circuits presents the following features: the test problem is studied in the aggregate; a test method, a test environment and automated test program generation are proposed; the circuit behavior is considered as a whole, including the response to instructions (or commands), and to signals at the same level. Emphasis is put on the signal test; an hardware which allows the test of signals and is compatible with functional testing is defined; a description language for signal timing diagrams is proposed.
{"title":"Taking into Account Asynchronous Signals in Functional Test of Complex Circuits","authors":"C. Bellon, R. Velazco","doi":"10.1109/DAC.1984.1585843","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585843","url":null,"abstract":"The proposed functional test method for complex circuits presents the following features: the test problem is studied in the aggregate; a test method, a test environment and automated test program generation are proposed; the circuit behavior is considered as a whole, including the response to instructions (or commands), and to signals at the same level. Emphasis is put on the signal test; an hardware which allows the test of signals and is compatible with functional testing is defined; a description language for signal timing diagrams is proposed.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"64 8-9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585841
J. Mar, You-Pang Wei
This paper describes a multi-level simulation strategy for verifying and optimizing VLSI circuit performance. Circuit simulation alone is insufficient for ensuring that VLSI designs meet performance targets. To meet VLSI needs, a tri-level family of simulation tools consisting of critical path analyzers, parasitic timing simulators, and circuit simulators is proposed. The relationship and interface between these tools, including how they combine "tops-down" and "bottoms-up" design methodologies, and some results from the initial implementation of this strategy in actual VLSI product designs are also discussed.
{"title":"Performance Verification of Circuits","authors":"J. Mar, You-Pang Wei","doi":"10.1109/DAC.1984.1585841","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585841","url":null,"abstract":"This paper describes a multi-level simulation strategy for verifying and optimizing VLSI circuit performance. Circuit simulation alone is insufficient for ensuring that VLSI designs meet performance targets. To meet VLSI needs, a tri-level family of simulation tools consisting of critical path analyzers, parasitic timing simulators, and circuit simulators is proposed. The relationship and interface between these tools, including how they combine \"tops-down\" and \"bottoms-up\" design methodologies, and some results from the initial implementation of this strategy in actual VLSI product designs are also discussed.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133436689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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