Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585832
J. Lewandowski, C. Liu
In this paper we present a branch and bound algorithm which exhaustively searches for an optimal column and/or row folding of PLAs. For PLAs with up to 50-60 input/output lines we can obtain an optimal solution in no more than a few minutes.
{"title":"A Branch and Bound Algorithm for Optimal PLA Folding","authors":"J. Lewandowski, C. Liu","doi":"10.1109/DAC.1984.1585832","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585832","url":null,"abstract":"In this paper we present a branch and bound algorithm which exhaustively searches for an optimal column and/or row folding of PLAs. For PLAs with up to 50-60 input/output lines we can obtain an optimal solution in no more than a few minutes.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123740711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585773
P. Veiga, M. Lança
In this paper, a new hardware description language -HARPA- is presented which was specially designed to permit the description of hierarchically structured digital systems at different levels of abstraction. The system building modules can be represented in terms of their structure, their behavior or a combination of both, as appropriate. A set of data types is provided which is adequate to characterize the data handling entities utilized at the various levels. Conversion mechanisms exist that facilitate the interfacing of blocks. The language is used as input medium for a multi-level simulator for verification of hierarchical designs.
{"title":"HARPA: A Hierarchical Multi-Level Hardware Description Language","authors":"P. Veiga, M. Lança","doi":"10.1109/DAC.1984.1585773","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585773","url":null,"abstract":"In this paper, a new hardware description language -HARPA- is presented which was specially designed to permit the description of hierarchically structured digital systems at different levels of abstraction. The system building modules can be represented in terms of their structure, their behavior or a combination of both, as appropriate. A set of data types is provided which is adequate to characterize the data handling entities utilized at the various levels. Conversion mechanisms exist that facilitate the interfacing of blocks. The language is used as input medium for a multi-level simulator for verification of hierarchical designs.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130518298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585812
J. Dussault, Chi-Chang Liaw, M. Tong
This paper describes a design tool called Functional Design System (FDS) that supports high level MOS LSI design. Designers can build circuits at the register transfer level by using a set of high level FDS primitives. FDS then automatically produces in seconds an accurate and efficient polycell implementation for these primitives. Therefore, the design cycle time can be reduced significantly. FDS is an integral part of a larger CAD system [1] which supports other aspects of the design cycle, namely, graphical design capture, simulation, test generation, and layout. The system has proved to be highly successful in helping designers to develop extremely reliable chips in a short time frame.
{"title":"A High Level Synthesis Tool for MOS Chip Design","authors":"J. Dussault, Chi-Chang Liaw, M. Tong","doi":"10.1109/DAC.1984.1585812","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585812","url":null,"abstract":"This paper describes a design tool called Functional Design System (FDS) that supports high level MOS LSI design. Designers can build circuits at the register transfer level by using a set of high level FDS primitives. FDS then automatically produces in seconds an accurate and efficient polycell implementation for these primitives. Therefore, the design cycle time can be reduced significantly. FDS is an integral part of a larger CAD system [1] which supports other aspects of the design cycle, namely, graphical design capture, simulation, test generation, and layout. The system has proved to be highly successful in helping designers to develop extremely reliable chips in a short time frame.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130848977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585876
T. Kozawa, Chihei Miura, H. Terai
A Combine and TOP down placement (CTOP) algorithm for determination of relative placement of blocks which are set of cells is presented. The objective functions of the CTOP algorithm are to minimize inter-block wiring space and dead space using a combine value P. P is defined as the combination of the connectivity and dead space factor. With use of the CTOP algorithm, chip size in our example is about 6% smaller than with manual block placement. In the experiment reported on here, we used the same automatic placement and routing program for intra-block design.
{"title":"Combine and Top Down Block Placement Algorithm for Hierarchical Logic VLSI Layout","authors":"T. Kozawa, Chihei Miura, H. Terai","doi":"10.1109/DAC.1984.1585876","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585876","url":null,"abstract":"A Combine and TOP down placement (CTOP) algorithm for determination of relative placement of blocks which are set of cells is presented. The objective functions of the CTOP algorithm are to minimize inter-block wiring space and dead space using a combine value P. P is defined as the combination of the connectivity and dead space factor. With use of the CTOP algorithm, chip size in our example is about 6% smaller than with manual block placement. In the experiment reported on here, we used the same automatic placement and routing program for intra-block design.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"598 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131739260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chin-Fu Chen, Chi-Yuan Lo, H. Nham, P. Subramaniam
This paper describes the second generation MOTIS mixed-mode simulator. In particular, It extends the current modeling capabilities to include resistors, floating capacitors, and bidirectional transmission gates. It employs a relaxation algorithm with local time-step control for timing simulation, and a switch level approach for unit delay simulation. It provides logic and timing verification for general MOS circuits in a mixed-mode environment. The new simulator is being used for production chips, and it is more accurate, flexible, and efficient than the existing MOTIS mixed-mode simulator.
{"title":"The Second Generation MOTIS Mixed-Mode Simulator","authors":"Chin-Fu Chen, Chi-Yuan Lo, H. Nham, P. Subramaniam","doi":"10.5555/800033.800767","DOIUrl":"https://doi.org/10.5555/800033.800767","url":null,"abstract":"This paper describes the second generation MOTIS mixed-mode simulator. In particular, It extends the current modeling capabilities to include resistors, floating capacitors, and bidirectional transmission gates. It employs a relaxation algorithm with local time-step control for timing simulation, and a switch level approach for unit delay simulation. It provides logic and timing verification for general MOS circuits in a mixed-mode environment. The new simulator is being used for production chips, and it is more accurate, flexible, and efficient than the existing MOTIS mixed-mode simulator.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128783144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The quality of placement and routing on gate arrays is commonly measured by average wire length. With regard to wire length, placement and routing are mutually competing tasks and the solution space for both is exponential. Estimates of measures of placement such as average wire length or, total wiring tracks prior to routing give some indication of the routability of the placement and, can be used to select another placement and repeat. The nature of these problems necessitates a probabilistic approach to the wirability analysis of integrated circuits. Stochastic models for wiring space estimation and the relation between wire length distribution and placement optimization have received attention recently [1], [6], [2], [5], [7], [3] and [4]. Much of the reported work on wire length distributions and placement of logic rests on empirical evidence that indicates that “well placed” chips exhibit Rent's Rule between the number of components and the number of corresponding external connections. Rent's Rule has been the basis of the heuristic arguments used to derive upper bounds on the average wire length and the form of the wire length distribution. Rent's Rule has the form T &equil; KC p (1) where T is the average number of external connections, C is the average number of components, K is number of connections per component and p is a positive constant. In [1], [2] and [4] the effect of placement on wire length distribution was introduced by assuming that a hierarchical partitioning scheme aimed at minimizing the average wire length results in a configuration that exhibits Rent's Rule. In [2] an upper bound r@@@@k for the average wire length between elements of different subsets of components of size k was derived, and using Rent's Rule to obtain the number of connections between such subsets, an upper bound on the average wire length was derived. In [3] the Pareto distribution is proposed for the distribution of wire lengths. Similar results were presented in [4]. In this paper we present a model that provides a mathematical basis for Rent's Rule and its relation to wire length distribution. It will be shown that Rent's Rule, an observed fact, is a manifestation of a more fundamental underlying process characterized by a function which leads directly to a general class of wire length distributions, the Weibull family. That is, Rent's Rule contains all the information about the distribution of wire lengths. Thus, estimates for the average wire length can be derived. Theory presented here is substantiated by simulation results and earlier research data.
{"title":"On the Relation between Wire Length Distributions and Placement of Logic on Master Slice ICs","authors":"S. Sastry, A. C. Parker","doi":"10.5555/800033.800891","DOIUrl":"https://doi.org/10.5555/800033.800891","url":null,"abstract":"The quality of placement and routing on gate arrays is commonly measured by average wire length. With regard to wire length, placement and routing are mutually competing tasks and the solution space for both is exponential. Estimates of measures of placement such as average wire length or, total wiring tracks prior to routing give some indication of the routability of the placement and, can be used to select another placement and repeat.\u0000 The nature of these problems necessitates a probabilistic approach to the wirability analysis of integrated circuits. Stochastic models for wiring space estimation and the relation between wire length distribution and placement optimization have received attention recently [1], [6], [2], [5], [7], [3] and [4]. Much of the reported work on wire length distributions and placement of logic rests on empirical evidence that indicates that “well placed” chips exhibit Rent's Rule between the number of components and the number of corresponding external connections. Rent's Rule has been the basis of the heuristic arguments used to derive upper bounds on the average wire length and the form of the wire length distribution. Rent's Rule has the form\u0000 T &equil; KC p (1)\u0000 where T is the average number of external connections, C is the average number of components, K is number of connections per component and p is a positive constant. In [1], [2] and [4] the effect of placement on wire length distribution was introduced by assuming that a hierarchical partitioning scheme aimed at minimizing the average wire length results in a configuration that exhibits Rent's Rule. In [2] an upper bound r@@@@k for the average wire length between elements of different subsets of components of size k was derived, and using Rent's Rule to obtain the number of connections between such subsets, an upper bound on the average wire length was derived. In [3] the Pareto distribution is proposed for the distribution of wire lengths. Similar results were presented in [4].\u0000 In this paper we present a model that provides a mathematical basis for Rent's Rule and its relation to wire length distribution. It will be shown that Rent's Rule, an observed fact, is a manifestation of a more fundamental underlying process characterized by a function which leads directly to a general class of wire length distributions, the Weibull family. That is, Rent's Rule contains all the information about the distribution of wire lengths. Thus, estimates for the average wire length can be derived. Theory presented here is substantiated by simulation results and earlier research data.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126485614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585834
Theodore Sabety, D. E. Shaw, B. Mathies
This paper describes a recently implemented program that very rapidly generates control paths for different variants of the constituent processing elements of a particular massively parallel machine, the NON-VON Supercomputer. The program, called PLATO, accepts as input a set of instruction opcodes, together with associated control information, and produces as output a functionally correct, highly area-efficient set of PLA's for the processing elements. One novel aspect of the program is its use of a channel routing algorithm to generate a Weinberger Array layout for the OR-plane of the PLA. By supporting extremely rapid generation of processing elements with different instruction sets, PLATO facilitates "rapid turnaround" architectural experimentation of a sort that would otherwise be impractical. Use of the program has already yielded major area and performance improvements in the NON-VON processing element. Many of the techniques employed in the PLATO system should prove applicable to the semi-automatic layout of processing elements for other multiprocessor machines.
{"title":"The Semi-Automatic Generation of Processing Element Control Paths for Highly Parallel Machines","authors":"Theodore Sabety, D. E. Shaw, B. Mathies","doi":"10.1109/DAC.1984.1585834","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585834","url":null,"abstract":"This paper describes a recently implemented program that very rapidly generates control paths for different variants of the constituent processing elements of a particular massively parallel machine, the NON-VON Supercomputer. The program, called PLATO, accepts as input a set of instruction opcodes, together with associated control information, and produces as output a functionally correct, highly area-efficient set of PLA's for the processing elements. One novel aspect of the program is its use of a channel routing algorithm to generate a Weinberger Array layout for the OR-plane of the PLA. By supporting extremely rapid generation of processing elements with different instruction sets, PLATO facilitates \"rapid turnaround\" architectural experimentation of a sort that would otherwise be impractical. Use of the program has already yielded major area and performance improvements in the NON-VON processing element. Many of the techniques employed in the PLATO system should prove applicable to the semi-automatic layout of processing elements for other multiprocessor machines.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131895330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585847
S. Su, Tonysheng Lin
Functional testing is becomilng more important due to the increasing complexity in digital LSI/VLSI devices. Various functional testing approaches have been proposed to meet this urgent need in LSI/VLSI testing. This paper presents the basic ideas behind deterministic functional testing and concisely overviews eight major functional testing techniques. Comparisons among these techniques and suggestions for future development are made to meet the challenges in this fast growing testing field.
{"title":"Functional Testing Techniques for Digital LSI/VLSI Systems","authors":"S. Su, Tonysheng Lin","doi":"10.1109/DAC.1984.1585847","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585847","url":null,"abstract":"Functional testing is becomilng more important due to the increasing complexity in digital LSI/VLSI devices. Various functional testing approaches have been proposed to meet this urgent need in LSI/VLSI testing. This paper presents the basic ideas behind deterministic functional testing and concisely overviews eight major functional testing techniques. Comparisons among these techniques and suggestions for future development are made to meet the challenges in this fast growing testing field.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114524028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585772
Charles H. Ng
The router described in this paper is part of a complete CAD system which aims at hierarchical designs of customized VLSI MOS circuits. It routes global signals as symbolic interconnect and is guaranteed to complete all routing in one pass. The router is fully automatic as well as highly interactive. It employs the novel idea of bouyancy and produces wires with a natural bus structure. The router is fully operational, and has been used in routing a number of real-world integrated circuits.
{"title":"A Symbolic-Interconnect Router for Custom IC Design","authors":"Charles H. Ng","doi":"10.1109/DAC.1984.1585772","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585772","url":null,"abstract":"The router described in this paper is part of a complete CAD system which aims at hierarchical designs of customized VLSI MOS circuits. It routes global signals as symbolic interconnect and is guaranteed to complete all routing in one pass. The router is fully automatic as well as highly interactive. It employs the novel idea of bouyancy and produces wires with a natural bus structure. The router is fully operational, and has been used in routing a number of real-world integrated circuits.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"232 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114991804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1984-06-25DOI: 10.1109/DAC.1984.1585856
K. Anderson, R. Powell
The HIGHLAND [1] integrated logic design system, for the design of gate array and standard cell IC's is described. While the main system features are reviewed, the major emphasis is on system software control and release issues.
{"title":"UTMC'S LSI CAD System - HIGHLAND","authors":"K. Anderson, R. Powell","doi":"10.1109/DAC.1984.1585856","DOIUrl":"https://doi.org/10.1109/DAC.1984.1585856","url":null,"abstract":"The HIGHLAND [1] integrated logic design system, for the design of gate array and standard cell IC's is described. While the main system features are reviewed, the major emphasis is on system software control and release issues.","PeriodicalId":188431,"journal":{"name":"21st Design Automation Conference Proceedings","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124751477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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