Pub Date : 1900-01-01DOI: 10.1109/edaps.2016.7893163
M. Tong
{"title":"Multiphysics/thermal modeling","authors":"M. Tong","doi":"10.1109/edaps.2016.7893163","DOIUrl":"https://doi.org/10.1109/edaps.2016.7893163","url":null,"abstract":"","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122113288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893151
Hua-hua Zhou, Linsheng Wu, Liang-Feng Qiu, J. Mao, M. Tang
A general method is proposed in this paper to extract the two-port coupling matrix of filtering antennas. By using the passivity and the realizability properties of a filter network, the rational polynomial forms of S-parameters can be obtained from the reflection and realized radiation efficiency of a filtering antenna. The coupling matrix is then obtained with transformation and optimization. After the coupling matrix is reestablished, the diagnosis and tuning of filtering antenna can easily be carried out. Our method has been validated with the successful tuning of a stacked patch antenna.
{"title":"Diagnosis and tuning of filtering antenna based on extracted coupling matrix","authors":"Hua-hua Zhou, Linsheng Wu, Liang-Feng Qiu, J. Mao, M. Tang","doi":"10.1109/EDAPS.2016.7893151","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893151","url":null,"abstract":"A general method is proposed in this paper to extract the two-port coupling matrix of filtering antennas. By using the passivity and the realizability properties of a filter network, the rational polynomial forms of S-parameters can be obtained from the reflection and realized radiation efficiency of a filtering antenna. The coupling matrix is then obtained with transformation and optimization. After the coupling matrix is reestablished, the diagnosis and tuning of filtering antenna can easily be carried out. Our method has been validated with the successful tuning of a stacked patch antenna.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117112847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893127
K. Park, Hosang Lee, W. Nah, J. Youn
Accurate estimation of an EMI characteristic of a given circuit at design stage is very difficult because of many uncertainties of parameters in the circuit. This is especially true when the symmetry of a circuit is broken in manufacturing, which was supposed to be in symmetry in the first place. When the symmetry is broken, quite a lot common mode radiation could be occurring, which is not easy to predict for a circuit designer at the design stage. In this paper, we propose a new simulation methodology for estimating common mode radiated emission from a transmission line using a generalized polynomial chaos (gPC), which is based stochastic approach, and show its validness to predict the common mode radiation from a transmission line.
{"title":"Stochastic estimation of common mode radiated emission from a transmission line","authors":"K. Park, Hosang Lee, W. Nah, J. Youn","doi":"10.1109/EDAPS.2016.7893127","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893127","url":null,"abstract":"Accurate estimation of an EMI characteristic of a given circuit at design stage is very difficult because of many uncertainties of parameters in the circuit. This is especially true when the symmetry of a circuit is broken in manufacturing, which was supposed to be in symmetry in the first place. When the symmetry is broken, quite a lot common mode radiation could be occurring, which is not easy to predict for a circuit designer at the design stage. In this paper, we propose a new simulation methodology for estimating common mode radiated emission from a transmission line using a generalized polynomial chaos (gPC), which is based stochastic approach, and show its validness to predict the common mode radiation from a transmission line.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126786175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893112
Youngwoo Kim, Kyungjun Cho, Subin Kim, Gapyeol Park, Joungho Kim
In this paper, we compare and analyze power/ground noise coupling in silicon, organic and glass interposers. We first compare the power/ground noise coupling of each interposer by analyzing transfer impedances of power distribution networks (PDNs). Due to low loss of the organic and glass substrates, at certain frequencies, transfer impedances increase dramatically and. In order to analyze the effects of the power/ground noise propagation in the PDN and coupling to through via channel we induced clock signals to each interposer's aggressor through via channel with data rate corresponds to the PDN (1,0)/(0,1) resonance frequency to load the power/ground noises in the PDN. We monitored the coupled voltages in the PDNs and compared eye-diagrams of the victim through via channels. Due to the low loss of the glass substrate, glass interposers turned out to be most vulnerable to the power/ground noise. We suppressed PDN transfer impedance of the glass interposer using decoupling capacitors and electromagnetic band gap structure.
{"title":"Power/ground noise coupling comparison and analysis in silicon, organic and glass interposers","authors":"Youngwoo Kim, Kyungjun Cho, Subin Kim, Gapyeol Park, Joungho Kim","doi":"10.1109/EDAPS.2016.7893112","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893112","url":null,"abstract":"In this paper, we compare and analyze power/ground noise coupling in silicon, organic and glass interposers. We first compare the power/ground noise coupling of each interposer by analyzing transfer impedances of power distribution networks (PDNs). Due to low loss of the organic and glass substrates, at certain frequencies, transfer impedances increase dramatically and. In order to analyze the effects of the power/ground noise propagation in the PDN and coupling to through via channel we induced clock signals to each interposer's aggressor through via channel with data rate corresponds to the PDN (1,0)/(0,1) resonance frequency to load the power/ground noises in the PDN. We monitored the coupled voltages in the PDNs and compared eye-diagrams of the victim through via channels. Due to the low loss of the glass substrate, glass interposers turned out to be most vulnerable to the power/ground noise. We suppressed PDN transfer impedance of the glass interposer using decoupling capacitors and electromagnetic band gap structure.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"127 16","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120935088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893150
I. Erdin, R. Achar, Kaya Erdin
The input-to-output transfer function of a buck converter is investigated including power transmission line parameters, accounting for printed circuit board (PCB) parasitics. A closed-form relation is developed for the transfer function to be used in small-signal analysis. Also, the effect of power transmission lines is demonstrated on control-to-output transfer function of the converter.
{"title":"Closed-form small signal model of a buck controller including power transmission lines","authors":"I. Erdin, R. Achar, Kaya Erdin","doi":"10.1109/EDAPS.2016.7893150","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893150","url":null,"abstract":"The input-to-output transfer function of a buck converter is investigated including power transmission line parameters, accounting for printed circuit board (PCB) parasitics. A closed-form relation is developed for the transfer function to be used in small-signal analysis. Also, the effect of power transmission lines is demonstrated on control-to-output transfer function of the converter.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121203036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893124
Hyesoo Kim, Junyong Park, Shinyoung Park, Jonghoon J. Kim, Joungho Kim, Dongho Ha, Michael Bae, Jong-Seok Shin
In this paper, we propose and analyze an equivalent RLGC model of silicone rubber socket with single-ended signaling. A silicone rubber socket consists of highly dense metal powders in elastic silicone rubber. When the silicone rubber is compressed, metal powders form a column which corresponds to a pad of package. Thus, it can be modeled as a pair of cylinders. We have successfully verified the proposed model using a 3D electromagnetic (EM) solver in frequency domain and the eye diagram measurement in time domain. As a result, the verified model can be used to determine whether socket is applicable to the test system in the simulation level concurrently with offering physical insight and reducing time spent 3D EM simulating socket.
{"title":"High-frequency modeling and signal integrity analysis of high-density silicone rubber socket","authors":"Hyesoo Kim, Junyong Park, Shinyoung Park, Jonghoon J. Kim, Joungho Kim, Dongho Ha, Michael Bae, Jong-Seok Shin","doi":"10.1109/EDAPS.2016.7893124","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893124","url":null,"abstract":"In this paper, we propose and analyze an equivalent RLGC model of silicone rubber socket with single-ended signaling. A silicone rubber socket consists of highly dense metal powders in elastic silicone rubber. When the silicone rubber is compressed, metal powders form a column which corresponds to a pad of package. Thus, it can be modeled as a pair of cylinders. We have successfully verified the proposed model using a 3D electromagnetic (EM) solver in frequency domain and the eye diagram measurement in time domain. As a result, the verified model can be used to determine whether socket is applicable to the test system in the simulation level concurrently with offering physical insight and reducing time spent 3D EM simulating socket.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114132807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893095
A. Raychowdhury
Fine grained spatiotemporal power management in SoCs require DC-DC converters and embedded voltage regulators that are compact, energy-efficient, and able to operate over a large dynamic range. Buck converters, switched capacitor converters and linear regulators have become key IP blocks to delivery power in diverse load circuits. In the first part of the talk, we will introduce the key design concepts and advances in these three converter/regulator topologies. Then we will focus on linear regulators as key enablers for dynamic voltage and frequency scaling (DVFS) in ultralow power SoCs. Linear regulators, including low-drop out regulators are the popular choice for on-die voltage regulation. Linear regulators have been traditionally designed for supply sensitive analog circuits which typically represent DC loads with small current transients and operate over a narrow operating range. However, an increasing number of power domains, decreasing decoupling capacitance per domain, large current transients and an ever expanding current/voltage dynamic range in digital circuits motivate the investigation of alternative topologies for linear regulators, including all-digital and hybrid analog/digital loops. In this talk we will present some of the recent work on linear regulators suitable for digital load circuits. We will describe models and Silicon measurements of all-digital and hybrid regulators that provide wide operating ranges and high current efficiencies across the entire range. This requires innovation in both linear and non-linear control topologies and their circuit implementations that can address key challenges in power management. We will introduce switched mode control, discrete time and continuous time systems as well as our recent work on unification of clocking and regulation for resilience to large dynamic variations.
{"title":"Tutorial II: Fine-grained power delivery and management in SoCs: Advances in control and circuit design","authors":"A. Raychowdhury","doi":"10.1109/EDAPS.2016.7893095","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893095","url":null,"abstract":"Fine grained spatiotemporal power management in SoCs require DC-DC converters and embedded voltage regulators that are compact, energy-efficient, and able to operate over a large dynamic range. Buck converters, switched capacitor converters and linear regulators have become key IP blocks to delivery power in diverse load circuits. In the first part of the talk, we will introduce the key design concepts and advances in these three converter/regulator topologies. Then we will focus on linear regulators as key enablers for dynamic voltage and frequency scaling (DVFS) in ultralow power SoCs. Linear regulators, including low-drop out regulators are the popular choice for on-die voltage regulation. Linear regulators have been traditionally designed for supply sensitive analog circuits which typically represent DC loads with small current transients and operate over a narrow operating range. However, an increasing number of power domains, decreasing decoupling capacitance per domain, large current transients and an ever expanding current/voltage dynamic range in digital circuits motivate the investigation of alternative topologies for linear regulators, including all-digital and hybrid analog/digital loops. In this talk we will present some of the recent work on linear regulators suitable for digital load circuits. We will describe models and Silicon measurements of all-digital and hybrid regulators that provide wide operating ranges and high current efficiencies across the entire range. This requires innovation in both linear and non-linear control topologies and their circuit implementations that can address key challenges in power management. We will introduce switched mode control, discrete time and continuous time systems as well as our recent work on unification of clocking and regulation for resilience to large dynamic variations.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131499233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893122
Qi Zhu, S. Venkataraman, C. Ye, A. Chandrasekhar
Xeon®-D[1] brings the high performance of Xeon® processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon®-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.
{"title":"Package design challenges and optimizations in density efficient (Intel® Xeon® processor D) SoC","authors":"Qi Zhu, S. Venkataraman, C. Ye, A. Chandrasekhar","doi":"10.1109/EDAPS.2016.7893122","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893122","url":null,"abstract":"Xeon®-D[1] brings the high performance of Xeon® processors into a dense, low-power System-on-Chip (SoC). This paper addresses the importance of cost-performance trade off optimization for the Xeon®-D package. It describes how to determine the low cost package factors (size, footprint, pin map and layer count) without compromising the performance of the system. 10GbE signal integrity design and HSD pin map optimization are discussed. Low power architecture and package power delivery features including FIVR are presented in the paper as well.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130750583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893140
Seungjin Lee, Sangyeol Oh, B. Shin, Jaehyuk Lim, Jaehoon Lee
Right-angle bended differential line using mushroom structure with asymmetric coupled line (ACL) is proposed to suppress the differential to common mode conversion. The mushroom structure and ACL can compensate for self-capacitances and self-inductances of shorter inner line, respectively. Simulated results show that the differential to common mode noise conversion can be maintained under −20dB from DC to 5.96 GHz. Also, transient analysis is conducted to validate the performance of proposed design in time domain, and shows significant suppression of common mode noise. The common mode noise of proposed design is reduced from 129mV to 36mV as compared with conventional right-angle bended differential line. Furthermore, measured results are compared with simulated results and show good agreements.
{"title":"Differential to common mode conversion suppression using mushroom structure with asymmetric coupled line","authors":"Seungjin Lee, Sangyeol Oh, B. Shin, Jaehyuk Lim, Jaehoon Lee","doi":"10.1109/EDAPS.2016.7893140","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893140","url":null,"abstract":"Right-angle bended differential line using mushroom structure with asymmetric coupled line (ACL) is proposed to suppress the differential to common mode conversion. The mushroom structure and ACL can compensate for self-capacitances and self-inductances of shorter inner line, respectively. Simulated results show that the differential to common mode noise conversion can be maintained under −20dB from DC to 5.96 GHz. Also, transient analysis is conducted to validate the performance of proposed design in time domain, and shows significant suppression of common mode noise. The common mode noise of proposed design is reduced from 129mV to 36mV as compared with conventional right-angle bended differential line. Furthermore, measured results are compared with simulated results and show good agreements.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131014031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893132
J. Ziegler, A. Zadehgol
Electrically small antennas have received much research attention and antenna designs have been developed that approach the Chu lower bound. One such antenna design is the spherical helix antenna which can achieve Q values that are 1.5 times the Chu limit. The spherical helix antenna presents a complex geometry that is a design challenge to implement, especially for use in printed circuit board assemblies. A novel hemispherical antenna design is developed and simulated that utilizes stacks of two-layer printed circuit boards to create the 3D hemispherical structure. The advantages of this approach are: the realization of complex antenna geometries using cost efficient printed circuit board technology and the ability to change substrate material to provide dielectric loading of the antenna, while achieving comparable performance with wire based designs.
{"title":"Design and simulation of a four-arm hemispherical helix antenna realized through a stacked printed circuit board structure","authors":"J. Ziegler, A. Zadehgol","doi":"10.1109/EDAPS.2016.7893132","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893132","url":null,"abstract":"Electrically small antennas have received much research attention and antenna designs have been developed that approach the Chu lower bound. One such antenna design is the spherical helix antenna which can achieve Q values that are 1.5 times the Chu limit. The spherical helix antenna presents a complex geometry that is a design challenge to implement, especially for use in printed circuit board assemblies. A novel hemispherical antenna design is developed and simulated that utilizes stacks of two-layer printed circuit boards to create the 3D hemispherical structure. The advantages of this approach are: the realization of complex antenna geometries using cost efficient printed circuit board technology and the ability to change substrate material to provide dielectric loading of the antenna, while achieving comparable performance with wire based designs.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133217508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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