Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874401
G. Signorini, C. Siviero, I. Stievano, S. Grivet-Talocia
High-speed differential interfaces implementing specific solutions for low-power consumption and low-EMI disturbances are vastly used in mobile platforms. In these devices, the slew rate is suitably controlled, the communication scheme alternatas data-bursts followed by power-saving states, the voltage swing and the common-mode level are reduced. To achieve these targets, a key role in voltage-mode output drivers is played by an internal voltage-regulator. The latter exhibits a rich dynamic behavior, with non-negligible effects on the transmitter outputs, that need to be carefully characterized. In this paper, a modeling strategy based on a few key enhancements of state-of-the-art solutions is presented, leading to compact and accurate models. The feasibility and strengths of the proposed approach are verified on a low-power high-speed voltage-mode driver.
{"title":"Enhanced macromodels of high-speed low-power differential drivers","authors":"G. Signorini, C. Siviero, I. Stievano, S. Grivet-Talocia","doi":"10.1109/EDAPS.2016.7874401","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874401","url":null,"abstract":"High-speed differential interfaces implementing specific solutions for low-power consumption and low-EMI disturbances are vastly used in mobile platforms. In these devices, the slew rate is suitably controlled, the communication scheme alternatas data-bursts followed by power-saving states, the voltage swing and the common-mode level are reduced. To achieve these targets, a key role in voltage-mode output drivers is played by an internal voltage-regulator. The latter exhibits a rich dynamic behavior, with non-negligible effects on the transmitter outputs, that need to be carefully characterized. In this paper, a modeling strategy based on a few key enhancements of state-of-the-art solutions is presented, leading to compact and accurate models. The feasibility and strengths of the proposed approach are verified on a low-power high-speed voltage-mode driver.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114433995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874413
Shaowu Huang, Beomtaek Lee
In this paper, a novel broadband equalizer optimization technique is introduced for digital system designs. Through effectively compensating both conductor loss and dielectric loss, this technique provides a new solution to find optimal equalizer for high speed signaling over printed circuit board (PCB) with continuous time linear equalizer (CTLE) as an application. Simulation results are presented to validate the technique.
{"title":"New broadband equalizer optimization technique for digital system designs","authors":"Shaowu Huang, Beomtaek Lee","doi":"10.1109/EDAPS.2016.7874413","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874413","url":null,"abstract":"In this paper, a novel broadband equalizer optimization technique is introduced for digital system designs. Through effectively compensating both conductor loss and dielectric loss, this technique provides a new solution to find optimal equalizer for high speed signaling over printed circuit board (PCB) with continuous time linear equalizer (CTLE) as an application. Simulation results are presented to validate the technique.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130408100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874432
Surender Singh, T. Kukal
Fiber skew is one of the most difficult problems to debug. This paper investigates the timing skew problem on high speed, high-definition multimedia interface (HDMI) channel due to the fiber weave effect of Printed circuit board (PCB). This skew causes an asymmetry between the signals in the two lines and converts some of the differential signal into common signal, thereby, distorting the rise time of the differential signal, causing ISI, resulting in the collapse of the eye, and leading to deterministic jitter. In this paper, a method is proposed to minimize intra pair skew and jitter induced by the fiber weave effect. It is a geometry based method to understand the physical degradations in the PCB. The proposed method verified by using the 3DFEM technique in the differential line.
{"title":"Timing skew enabler induced by fiber weave effect in high speed HDMI channel by angle routing technique in 3DFEM","authors":"Surender Singh, T. Kukal","doi":"10.1109/EDAPS.2016.7874432","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874432","url":null,"abstract":"Fiber skew is one of the most difficult problems to debug. This paper investigates the timing skew problem on high speed, high-definition multimedia interface (HDMI) channel due to the fiber weave effect of Printed circuit board (PCB). This skew causes an asymmetry between the signals in the two lines and converts some of the differential signal into common signal, thereby, distorting the rise time of the differential signal, causing ISI, resulting in the collapse of the eye, and leading to deterministic jitter. In this paper, a method is proposed to minimize intra pair skew and jitter induced by the fiber weave effect. It is a geometry based method to understand the physical degradations in the PCB. The proposed method verified by using the 3DFEM technique in the differential line.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"19 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874398
K. Han, Srikumar Sandeep, Bill Martin, M. Swaminathan
In this paper an algorithm is described for obtaining the response of Power Distribution Networks (PDN) arising in chip, package or pcb during an early design phase. Results are provided for power grids arising in silicon interposers to validate the approach.
{"title":"Modeling of power distribution networks for path finding","authors":"K. Han, Srikumar Sandeep, Bill Martin, M. Swaminathan","doi":"10.1109/EDAPS.2016.7874398","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874398","url":null,"abstract":"In this paper an algorithm is described for obtaining the response of Power Distribution Networks (PDN) arising in chip, package or pcb during an early design phase. Results are provided for power grids arising in silicon interposers to validate the approach.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116971955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-01DOI: 10.1109/EDAPS.2016.7874424
X. Fang, T. Makharashvili, A. Ruehli, J. Fan, J. Drewniak, B. Archambeault, M. Cocchini
Decoupling capacitors perform an important function in the impedance reduction of power distribution systems. Hence, they are a key part of an electrical model required for the design of such systems. In this paper, we construct circuit models for the capacitors which include the local environment such that the overall PDN model is simplified and it can be considered as decoupled macromodels.
{"title":"PEEC macromodels for above plane decoupling capacitors","authors":"X. Fang, T. Makharashvili, A. Ruehli, J. Fan, J. Drewniak, B. Archambeault, M. Cocchini","doi":"10.1109/EDAPS.2016.7874424","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7874424","url":null,"abstract":"Decoupling capacitors perform an important function in the impedance reduction of power distribution systems. Hence, they are a key part of an electrical model required for the design of such systems. In this paper, we construct circuit models for the capacitors which include the local environment such that the overall PDN model is simplified and it can be considered as decoupled macromodels.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"161 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125897889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-07DOI: 10.1109/EPEPS.2015.7347165
X. Qi, R. Mittal, S. Ji, S. Puligundla
Modern mobile platforms contain mainly active components in a small area with stringent power and cost targets. An integrated clock is needed for PLLs, component internal functions as well as transferring data among them. Due to the small mobile form factors, the noise coupling from power/ground and signals to the integrated clock circuitry becomes more evident impacting clock performance significantly. A method of signal and power integrity analysis and system optimization is proposed to design clocks in System-on-Chip (SoC), package and platform of mobile products such as wearables, phones and tablets. The measured results from high volume mobile systems show 30% clock jitter reduction from generation to generation using the frequency domain analysis and system optimization.
{"title":"Analysis and system optimization of high performance clocking for modern mobile platforms","authors":"X. Qi, R. Mittal, S. Ji, S. Puligundla","doi":"10.1109/EPEPS.2015.7347165","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347165","url":null,"abstract":"Modern mobile platforms contain mainly active components in a small area with stringent power and cost targets. An integrated clock is needed for PLLs, component internal functions as well as transferring data among them. Due to the small mobile form factors, the noise coupling from power/ground and signals to the integrated clock circuitry becomes more evident impacting clock performance significantly. A method of signal and power integrity analysis and system optimization is proposed to design clocks in System-on-Chip (SoC), package and platform of mobile products such as wearables, phones and tablets. The measured results from high volume mobile systems show 30% clock jitter reduction from generation to generation using the frequency domain analysis and system optimization.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122266232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-07DOI: 10.1109/EPEPS.2015.7347142
T. Yu, Jian Chen, Chiawen Shih
A practical approach for accurately modeling high-speed link structures is presented and named as the “cut and stitch” (C&S) methodology. To generate S-parameters for the whole system, C&S first cuts the structure into different parts with different electromagnetic (EM) features and also provides auto-generated ports at the cutting interfaces to do system connection later, then selects the proper EM solver for individual design partition's modeling, and finally automatically stitches all of the S-parameter models together. Numerical experiments show that the approach can achieve more than one order of the speedup ratio with the acceptable accuracy.
{"title":"Efficient methodology for modeling structure of high-speed long transmission lines","authors":"T. Yu, Jian Chen, Chiawen Shih","doi":"10.1109/EPEPS.2015.7347142","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347142","url":null,"abstract":"A practical approach for accurately modeling high-speed link structures is presented and named as the “cut and stitch” (C&S) methodology. To generate S-parameters for the whole system, C&S first cuts the structure into different parts with different electromagnetic (EM) features and also provides auto-generated ports at the cutting interfaces to do system connection later, then selects the proper EM solver for individual design partition's modeling, and finally automatically stitches all of the S-parameter models together. Numerical experiments show that the approach can achieve more than one order of the speedup ratio with the acceptable accuracy.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132705212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-07DOI: 10.1109/EPEPS.2015.7347135
Shaowu Huang, Beomtaek Lee
A new de-embedding technique is introduced in this paper with pre-established Look-Up Table (LUT) for accurate characterization of high speed interconnects, particularly for printed circuit board (PCB). The method de-embeds the test fixture effects from the measurement or/and simulation results. It improves the accuracy and reduces the PCB layout area comparing to one line method. It reduces the PCB layout area and improves the measurement efficiency comparing to two line method.
{"title":"Novel de-embedding method with look-up table for characterization of interconnects","authors":"Shaowu Huang, Beomtaek Lee","doi":"10.1109/EPEPS.2015.7347135","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347135","url":null,"abstract":"A new de-embedding technique is introduced in this paper with pre-established Look-Up Table (LUT) for accurate characterization of high speed interconnects, particularly for printed circuit board (PCB). The method de-embeds the test fixture effects from the measurement or/and simulation results. It improves the accuracy and reduces the PCB layout area comparing to one line method. It reduces the PCB layout area and improves the measurement efficiency comparing to two line method.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116669674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-07DOI: 10.1109/EPEPS.2015.7347158
Denis Oyaro, P. Triverio
We present a scalable method for the model order reduction of very large RC circuits. Such circuits arise in the modeling of on-chip power distribution networks. The method achieves moment matching with efficient Householder transformations and sparse matrix factorizations. It preserves passivity and generate sparse, efficient models. It overcomes the limited scalability of standard Krylov methods, that become inefficient beyond a few hundreds of ports. Numerical results demonstrate the superior performance of the proposed method in terms of reduction time and model efficiency. Scalability is demonstrated up to 1.2 million nodes and 2,400 ports.
{"title":"Fast model order reduction of RC networks with very large order and port count","authors":"Denis Oyaro, P. Triverio","doi":"10.1109/EPEPS.2015.7347158","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347158","url":null,"abstract":"We present a scalable method for the model order reduction of very large RC circuits. Such circuits arise in the modeling of on-chip power distribution networks. The method achieves moment matching with efficient Householder transformations and sparse matrix factorizations. It preserves passivity and generate sparse, efficient models. It overcomes the limited scalability of standard Krylov methods, that become inefficient beyond a few hundreds of ports. Numerical results demonstrate the superior performance of the proposed method in terms of reduction time and model efficiency. Scalability is demonstrated up to 1.2 million nodes and 2,400 ports.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133337672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-07DOI: 10.1109/EPEPS.2015.7347118
Sameer Shekhar, A. Jain
Optimal power delivery network design relies on decoupling capacitors that consume significant package and board real estate, which is becoming scarce due to shrinking chip sizes and overall system form factors. This paper addresses noise reduction via capacitor interconnection between different voltage domains to leverage decoupling capacitors across domains. Novel structures that integrate decoupling and interconnection capacitor are then proposed. The complete solution delivers more than 40% noise reduction per unit capacitor area. Simulation results are provided for illustration.
{"title":"Interconnected capacitors for effective power delivery noise suppression across domains","authors":"Sameer Shekhar, A. Jain","doi":"10.1109/EPEPS.2015.7347118","DOIUrl":"https://doi.org/10.1109/EPEPS.2015.7347118","url":null,"abstract":"Optimal power delivery network design relies on decoupling capacitors that consume significant package and board real estate, which is becoming scarce due to shrinking chip sizes and overall system form factors. This paper addresses noise reduction via capacitor interconnection between different voltage domains to leverage decoupling capacitors across domains. Novel structures that integrate decoupling and interconnection capacitor are then proposed. The complete solution delivers more than 40% noise reduction per unit capacitor area. Simulation results are provided for illustration.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127962978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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