Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893095
A. Raychowdhury
Fine grained spatiotemporal power management in SoCs require DC-DC converters and embedded voltage regulators that are compact, energy-efficient, and able to operate over a large dynamic range. Buck converters, switched capacitor converters and linear regulators have become key IP blocks to delivery power in diverse load circuits. In the first part of the talk, we will introduce the key design concepts and advances in these three converter/regulator topologies. Then we will focus on linear regulators as key enablers for dynamic voltage and frequency scaling (DVFS) in ultralow power SoCs. Linear regulators, including low-drop out regulators are the popular choice for on-die voltage regulation. Linear regulators have been traditionally designed for supply sensitive analog circuits which typically represent DC loads with small current transients and operate over a narrow operating range. However, an increasing number of power domains, decreasing decoupling capacitance per domain, large current transients and an ever expanding current/voltage dynamic range in digital circuits motivate the investigation of alternative topologies for linear regulators, including all-digital and hybrid analog/digital loops. In this talk we will present some of the recent work on linear regulators suitable for digital load circuits. We will describe models and Silicon measurements of all-digital and hybrid regulators that provide wide operating ranges and high current efficiencies across the entire range. This requires innovation in both linear and non-linear control topologies and their circuit implementations that can address key challenges in power management. We will introduce switched mode control, discrete time and continuous time systems as well as our recent work on unification of clocking and regulation for resilience to large dynamic variations.
{"title":"Tutorial II: Fine-grained power delivery and management in SoCs: Advances in control and circuit design","authors":"A. Raychowdhury","doi":"10.1109/EDAPS.2016.7893095","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893095","url":null,"abstract":"Fine grained spatiotemporal power management in SoCs require DC-DC converters and embedded voltage regulators that are compact, energy-efficient, and able to operate over a large dynamic range. Buck converters, switched capacitor converters and linear regulators have become key IP blocks to delivery power in diverse load circuits. In the first part of the talk, we will introduce the key design concepts and advances in these three converter/regulator topologies. Then we will focus on linear regulators as key enablers for dynamic voltage and frequency scaling (DVFS) in ultralow power SoCs. Linear regulators, including low-drop out regulators are the popular choice for on-die voltage regulation. Linear regulators have been traditionally designed for supply sensitive analog circuits which typically represent DC loads with small current transients and operate over a narrow operating range. However, an increasing number of power domains, decreasing decoupling capacitance per domain, large current transients and an ever expanding current/voltage dynamic range in digital circuits motivate the investigation of alternative topologies for linear regulators, including all-digital and hybrid analog/digital loops. In this talk we will present some of the recent work on linear regulators suitable for digital load circuits. We will describe models and Silicon measurements of all-digital and hybrid regulators that provide wide operating ranges and high current efficiencies across the entire range. This requires innovation in both linear and non-linear control topologies and their circuit implementations that can address key challenges in power management. We will introduce switched mode control, discrete time and continuous time systems as well as our recent work on unification of clocking and regulation for resilience to large dynamic variations.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131499233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893154
W. Chen, M. Tong
Electromagnetic (EM) modeling is essential to extract equivalent circuit parameters for interconnect structures in signal integrity. The modeling can be formulated by integral equation approach and surface integral equations (SIEs) are preferred whenever available. If conducting interconnects are lossy, the loss needs to be carefully considered for accurate modeling. Traditionally, the loss is approximately accounted for by a surface impedance for simplicity, but such an approximation may not be valid when the skin depth of current is large due to the small conductivity or low operating frequency of interconnects. We propose a different scheme to model the structures by treating the lossy interconnects as penetrable media and using a hybrid surface integral equations (HSIEs) to describe them. The HSIEs are solved with the method of moments (MoM), but we employ a dual basis function (DBF) to expand the magnetic current density so that the conditioning of system matrix can be greatly improved. A numerical example is presented to demonstrate the scheme and good results have been obtained.
{"title":"Electromagnetic modeling for lossy interconnect structures based on hybrid surface integral equations","authors":"W. Chen, M. Tong","doi":"10.1109/EDAPS.2016.7893154","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893154","url":null,"abstract":"Electromagnetic (EM) modeling is essential to extract equivalent circuit parameters for interconnect structures in signal integrity. The modeling can be formulated by integral equation approach and surface integral equations (SIEs) are preferred whenever available. If conducting interconnects are lossy, the loss needs to be carefully considered for accurate modeling. Traditionally, the loss is approximately accounted for by a surface impedance for simplicity, but such an approximation may not be valid when the skin depth of current is large due to the small conductivity or low operating frequency of interconnects. We propose a different scheme to model the structures by treating the lossy interconnects as penetrable media and using a hybrid surface integral equations (HSIEs) to describe them. The HSIEs are solved with the method of moments (MoM), but we employ a dual basis function (DBF) to expand the magnetic current density so that the conditioning of system matrix can be greatly improved. A numerical example is presented to demonstrate the scheme and good results have been obtained.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123877748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893096
A. Kouki
Unlike digital designs where very complex circuits can be designed with minimal designer worries about the details of the physical technology, RF circuit and systems designs and techniques have seen very little evolution over the years and remain largely manual requiring extensive user intervention and considerable expertise. While digital hardware circuitry can be intelligently reconfigured and programed to implement multiple functions, RF circuits and modules typically have limited to no reconfigurabitly nor programmability. In this talk, RF hardware abstraction concepts are discussed and a framework for their integration in a revised design cycle that enables higher levels of automation is presented. The future application of these concepts and techniques to the automated design of intelligent RF modules is also highlighted.
{"title":"Tutorial III: RF hardware abstraction for design automation of intelligent RF modules award","authors":"A. Kouki","doi":"10.1109/EDAPS.2016.7893096","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893096","url":null,"abstract":"Unlike digital designs where very complex circuits can be designed with minimal designer worries about the details of the physical technology, RF circuit and systems designs and techniques have seen very little evolution over the years and remain largely manual requiring extensive user intervention and considerable expertise. While digital hardware circuitry can be intelligently reconfigured and programed to implement multiple functions, RF circuits and modules typically have limited to no reconfigurabitly nor programmability. In this talk, RF hardware abstraction concepts are discussed and a framework for their integration in a revised design cycle that enables higher levels of automation is presented. The future application of these concepts and techniques to the automated design of intelligent RF modules is also highlighted.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128794318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893145
Ta-Yeh Lin, T. Chiu, D. Chang
A high gain V-band on-chip 2×2 dual-polarization dielectric resonator antenna (DRA) array in silicon substrate based on Integrated Passive Device (IPD) technology is presented in the paper. In the proposed structure, dielectric resonator (DR) was fed by using wire-bond structures for bandwidth and antenna efficiency improvement. The simulation and measurement regarding the DRA element reflection coefficient and isolation are conducted for design validation. The simulated results show that the antenna can operate in V-band, and the impedance bandwidth with |S11| less than −10 dB is from 55.7 GHz to 65.8 GHz. The peak gain is 10.3 dBi. The proposed design is well suited for System-in-Package millimeter-wave radio front-ends.
{"title":"Design of a V-band 2 × 2 dual-polarization dielectric resonator antenna array","authors":"Ta-Yeh Lin, T. Chiu, D. Chang","doi":"10.1109/EDAPS.2016.7893145","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893145","url":null,"abstract":"A high gain V-band on-chip 2×2 dual-polarization dielectric resonator antenna (DRA) array in silicon substrate based on Integrated Passive Device (IPD) technology is presented in the paper. In the proposed structure, dielectric resonator (DR) was fed by using wire-bond structures for bandwidth and antenna efficiency improvement. The simulation and measurement regarding the DRA element reflection coefficient and isolation are conducted for design validation. The simulated results show that the antenna can operate in V-band, and the impedance bandwidth with |S11| less than −10 dB is from 55.7 GHz to 65.8 GHz. The peak gain is 10.3 dBi. The proposed design is well suited for System-in-Package millimeter-wave radio front-ends.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117193189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893121
Hong Shi, S. Tan, G. Refai-Ahmed, S. Ramalingam, Jae-Gyung Ahn
The recent market demand to high power 16nm FPGA has challenged package design to an unprecedented level. Specifically, logic tense applications require significantly greater dynamic current than previous generations. This paper describes recent advancements in high power FPGA package design for current-carrying capability. Firstly, new design methodologies are introduced that can link physical design for optimal current distribution directly to failure rate as a result of electro-migration (EM) in stated lifetime. Secondly, a specific design case is analyzed with the new method to show how BGA pin pattern can impact maximal current carrying capability.
{"title":"High power FPGA package design to maximize current-carrying capability","authors":"Hong Shi, S. Tan, G. Refai-Ahmed, S. Ramalingam, Jae-Gyung Ahn","doi":"10.1109/EDAPS.2016.7893121","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893121","url":null,"abstract":"The recent market demand to high power 16nm FPGA has challenged package design to an unprecedented level. Specifically, logic tense applications require significantly greater dynamic current than previous generations. This paper describes recent advancements in high power FPGA package design for current-carrying capability. Firstly, new design methodologies are introduced that can link physical design for optimal current distribution directly to failure rate as a result of electro-migration (EM) in stated lifetime. Secondly, a specific design case is analyzed with the new method to show how BGA pin pattern can impact maximal current carrying capability.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125366536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/edaps.2016.7893129
J. Schutt-Ainé, M. Swaminathan, G. Tech
{"title":"Poster session and industry reception","authors":"J. Schutt-Ainé, M. Swaminathan, G. Tech","doi":"10.1109/edaps.2016.7893129","DOIUrl":"https://doi.org/10.1109/edaps.2016.7893129","url":null,"abstract":"","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121856134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/edaps.2016.7893148
Tzong-Lin Wu
{"title":"TL modeling","authors":"Tzong-Lin Wu","doi":"10.1109/edaps.2016.7893148","DOIUrl":"https://doi.org/10.1109/edaps.2016.7893148","url":null,"abstract":"","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126471680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893126
Y. Ye, D. Spina, T. Dhaene, L. Knockaert, G. Antonini
In this paper, a stochastic modeling approach is proposed for time-domain variability analysis of general linear and passive systems with uncertain parameters. Starting from the polynomial chaos (PC) expansion of the scattering parameters, the Galerkin projections (GP) method is adopted to build an augmented scattering matrix which describes the relationship between the corresponding PC coefficients of the input and output port signals. The Vector Fitting (VF) algorithm is then used to obtain a stable and passive state-space model of such augmented matrix. As a result, a stochastic system is described by an equivalent deterministic macro model and the time-domain variability analysis can be performed by means of one time-domain simulation. The feasibility, efficiency and accuracy of the proposed technique are verified by comparison with conventional Monte Carlo (MC) approach for a suitable numerical example.
{"title":"Macromodeling of general linear systems under stochastic variations","authors":"Y. Ye, D. Spina, T. Dhaene, L. Knockaert, G. Antonini","doi":"10.1109/EDAPS.2016.7893126","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893126","url":null,"abstract":"In this paper, a stochastic modeling approach is proposed for time-domain variability analysis of general linear and passive systems with uncertain parameters. Starting from the polynomial chaos (PC) expansion of the scattering parameters, the Galerkin projections (GP) method is adopted to build an augmented scattering matrix which describes the relationship between the corresponding PC coefficients of the input and output port signals. The Vector Fitting (VF) algorithm is then used to obtain a stable and passive state-space model of such augmented matrix. As a result, a stochastic system is described by an equivalent deterministic macro model and the time-domain variability analysis can be performed by means of one time-domain simulation. The feasibility, efficiency and accuracy of the proposed technique are verified by comparison with conventional Monte Carlo (MC) approach for a suitable numerical example.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130538635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893094
E. Rosenbaum
The IC packaging technology has a surprisingly large influence on an IC's electrostatic discharge (ESD) robustness at both the component and system levels. For charge device model (CDM) component-level ESD, the package determines the amount of energy dissipated in the die, and for both system and component-level ESD, the package determines the current return path. This tutorial will explore those phenomena and demonstrate how the on-chip ESD protection network design should be mindful of the package design. The effect of 3D integration will also be addressed.
{"title":"Tutorial I: Influence of IC packaging technology on ESD robustness of components","authors":"E. Rosenbaum","doi":"10.1109/EDAPS.2016.7893094","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893094","url":null,"abstract":"The IC packaging technology has a surprisingly large influence on an IC's electrostatic discharge (ESD) robustness at both the component and system levels. For charge device model (CDM) component-level ESD, the package determines the amount of energy dissipated in the die, and for both system and component-level ESD, the package determines the current return path. This tutorial will explore those phenomena and demonstrate how the on-chip ESD protection network design should be mindful of the package design. The effect of 3D integration will also be addressed.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124708535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893157
M. Rahmani, M. Mazzola
This paper addresses calculation and simulation of Electromagnetic Interference (EMI) on the electronic boards. Keysight EMPro Finite Difference Time Domain (FDTD) simulator is utilized for simulation. The simulated radiated emission is studied due to level variations of excitation voltage and the spatial coordinates (angle) of simulated point regarded to the board. The simulation results are compared to the Federall Communications Commission (FCC) Part 15 Class B at three meters limit.
{"title":"Modeling of electromagnetic interference in electronic boards using finite difference time domain method","authors":"M. Rahmani, M. Mazzola","doi":"10.1109/EDAPS.2016.7893157","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893157","url":null,"abstract":"This paper addresses calculation and simulation of Electromagnetic Interference (EMI) on the electronic boards. Keysight EMPro Finite Difference Time Domain (FDTD) simulator is utilized for simulation. The simulated radiated emission is studied due to level variations of excitation voltage and the spatial coordinates (angle) of simulated point regarded to the board. The simulation results are compared to the Federall Communications Commission (FCC) Part 15 Class B at three meters limit.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114949351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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