Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893166
Jie Tong, G. Zhu, J. Hu, W. Yin, Liang Lin, Liang Zhou
This paper presents the study of electro-thermo-mechanical responses of bonding wire arrays used for the design of lateral double-diffused MOSFET-based RF amplifier. We at first show a series of ruggedness measurements of bonding wire arrays with a mismatch control system and an IR microscopy used for accurately predicting their surface temperatures. Further, an in-house time-domain finite element solver is employed for simulating the electro-thermo-mechanical responses of bonding wire arrays and their highest temperatures are captured and validated in comparison with those of commercial simulator COMSOL. Finally, an improved design of the bonding wire array is proposed and validated experimentally so as to get both uniform current and temperature distributions, and therefore, a significant improvement of the electrical performance of LDMOSFET RF PA is achieved as we expected.
{"title":"Study on electro-thermo-mechanical responses of bonding wires arrays used for the package design of LDMOSFET-based RF Amplifier","authors":"Jie Tong, G. Zhu, J. Hu, W. Yin, Liang Lin, Liang Zhou","doi":"10.1109/EDAPS.2016.7893166","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893166","url":null,"abstract":"This paper presents the study of electro-thermo-mechanical responses of bonding wire arrays used for the design of lateral double-diffused MOSFET-based RF amplifier. We at first show a series of ruggedness measurements of bonding wire arrays with a mismatch control system and an IR microscopy used for accurately predicting their surface temperatures. Further, an in-house time-domain finite element solver is employed for simulating the electro-thermo-mechanical responses of bonding wire arrays and their highest temperatures are captured and validated in comparison with those of commercial simulator COMSOL. Finally, an improved design of the bonding wire array is proposed and validated experimentally so as to get both uniform current and temperature distributions, and therefore, a significant improvement of the electrical performance of LDMOSFET RF PA is achieved as we expected.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130200498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893116
Dongke Zhu, Erping Li, Cheng Ping, Xiao-Li Yang, Yong-sheng Li, Huichun Yu, Bin Li
The effects of shorting vias on suppressing common-mode radiation in different frequency range are investigated based on a typical wire-bonded ball grid array (WB-BGA) package. Conventional shorting vias provide a short return path for common-mode currents so as to reduce the radiation effectively at low frequencies. However, the suppression is limited at higher frequencies due to the excess parasitic inductance. Therefore, a novel concept of absorptive shorting vias is presented for suppressing radiation in high frequency range.
{"title":"Investigation of shorting vias for suppressing common-mode radiation in different frequency range","authors":"Dongke Zhu, Erping Li, Cheng Ping, Xiao-Li Yang, Yong-sheng Li, Huichun Yu, Bin Li","doi":"10.1109/EDAPS.2016.7893116","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893116","url":null,"abstract":"The effects of shorting vias on suppressing common-mode radiation in different frequency range are investigated based on a typical wire-bonded ball grid array (WB-BGA) package. Conventional shorting vias provide a short return path for common-mode currents so as to reduce the radiation effectively at low frequencies. However, the suppression is limited at higher frequencies due to the excess parasitic inductance. Therefore, a novel concept of absorptive shorting vias is presented for suppressing radiation in high frequency range.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126897502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/EDAPS.2016.7893123
A. Lingambudi, S. Vijay, W. Becker, Michael Pardeik
DIMMs built with DDR4 (Double Data Rate 4th-generation) SDRAM (Synchronous Dynamic Random-Access Memory) are the current memory components used on HPC (High Performance Computing) systems. The DDR4 signal interfaces operate up to a 3200 Mbps data rate and at 1.2 V. This is a higher frequency at a lower voltage, therefore lower power, than the third generation DDR3 DIMMs. The higher frequency and lower voltage results in decreased timing margins. The characterization of the timing margins and power usage is of significantly increased importance in DDR4. In this paper, a methodology for experimentally quantifying timing margins and power is applied at bounding voltage and frequency corners to plan, design, and architect HPC systems optimized for power consumption and with timing margin.
{"title":"Timing margin analysis and Power measurement with DDR4 memory","authors":"A. Lingambudi, S. Vijay, W. Becker, Michael Pardeik","doi":"10.1109/EDAPS.2016.7893123","DOIUrl":"https://doi.org/10.1109/EDAPS.2016.7893123","url":null,"abstract":"DIMMs built with DDR4 (Double Data Rate 4th-generation) SDRAM (Synchronous Dynamic Random-Access Memory) are the current memory components used on HPC (High Performance Computing) systems. The DDR4 signal interfaces operate up to a 3200 Mbps data rate and at 1.2 V. This is a higher frequency at a lower voltage, therefore lower power, than the third generation DDR3 DIMMs. The higher frequency and lower voltage results in decreased timing margins. The characterization of the timing margins and power usage is of significantly increased importance in DDR4. In this paper, a methodology for experimentally quantifying timing margins and power is applied at bounding voltage and frequency corners to plan, design, and architect HPC systems optimized for power consumption and with timing margin.","PeriodicalId":191549,"journal":{"name":"2016 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114986727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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