P. Leray, S. Halder, G. Lorusso, B. Baudemprez, O. Inoue, Y. Okagawa
Overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic scanners use high-order corrections or correction per exposure to reduce the residual overlay. It is not enough in traditional feedback of overlay measurement by using ADI wafer because overlay error depends on other process (etching process and film stress, etc.). It needs high accuracy overlay measurement by using AEI wafer. WIS (Wafer Induced Shift) is the main issue for optical overlay, IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). We design dedicated SEM overlay targets for dual damascene process of N10 by i-ArF multi-patterning. The pattern is same as device-pattern locally. Optical overlay tools select segmented pattern to reduce the WIS. However segmentation has limit, especially the via-pattern, for keeping the sensitivity and accuracy. We evaluate difference between the viapattern and relaxed pitch gratings which are similar to optical overlay target at AEI. CDSEM can estimate asymmetry property of target from image of pattern edge. CDSEM can estimate asymmetry property of target from image of pattern edge. We will compare full map of SEM overlay to full map of optical overlay for high order correction ( correctables and residual fingerprints).
{"title":"Hybrid overlay metrology for high order correction by using CDSEM","authors":"P. Leray, S. Halder, G. Lorusso, B. Baudemprez, O. Inoue, Y. Okagawa","doi":"10.1117/12.2222777","DOIUrl":"https://doi.org/10.1117/12.2222777","url":null,"abstract":"Overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic scanners use high-order corrections or correction per exposure to reduce the residual overlay. It is not enough in traditional feedback of overlay measurement by using ADI wafer because overlay error depends on other process (etching process and film stress, etc.). It needs high accuracy overlay measurement by using AEI wafer. WIS (Wafer Induced Shift) is the main issue for optical overlay, IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). We design dedicated SEM overlay targets for dual damascene process of N10 by i-ArF multi-patterning. The pattern is same as device-pattern locally. Optical overlay tools select segmented pattern to reduce the WIS. However segmentation has limit, especially the via-pattern, for keeping the sensitivity and accuracy. We evaluate difference between the viapattern and relaxed pitch gratings which are similar to optical overlay target at AEI. CDSEM can estimate asymmetry property of target from image of pattern edge. CDSEM can estimate asymmetry property of target from image of pattern edge. We will compare full map of SEM overlay to full map of optical overlay for high order correction ( correctables and residual fingerprints).","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128686971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. L. Gödecke, S. Peterhänsel, K. Frenner, W. Osten
We propose a measurement technique which enables the precise determination of side wall angles (SWAs) with absolute values below 1°. Our simulations show that a differentiation between asymmetric SWAs is also possible. The grating structure under investigation has a grating period on the order of a few micrometers. Each grating line consists of a fine sub-grating with 40 nm period and 20 nm critical dimension. Our approach is based on coherent high-NA Fourier scatterometry, extended by a lateral scan over the sample. Additionally, a 180°-shearing element allows for coherent superposition of the higher diffraction orders.
{"title":"Measurement of asymmetric side wall angles by coherent scanning Fourier scatterometry","authors":"M. L. Gödecke, S. Peterhänsel, K. Frenner, W. Osten","doi":"10.1117/12.2218824","DOIUrl":"https://doi.org/10.1117/12.2218824","url":null,"abstract":"We propose a measurement technique which enables the precise determination of side wall angles (SWAs) with absolute values below 1°. Our simulations show that a differentiation between asymmetric SWAs is also possible. The grating structure under investigation has a grating period on the order of a few micrometers. Each grating line consists of a fine sub-grating with 40 nm period and 20 nm critical dimension. Our approach is based on coherent high-NA Fourier scatterometry, extended by a lateral scan over the sample. Additionally, a 180°-shearing element allows for coherent superposition of the higher diffraction orders.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127303134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Wojdyla, A. Donoghue, M. Benk, P. Naulleau, K. Goldberg
EUV lithography uses reflective photomasks to print features on a wafer through the formation of an aerial image. The aerial image is influenced by the mask’s substrate and pattern roughness and by photon shot noise, which collectively affect the line-width on wafer prints, with an impact on local critical dimension uniformity (LCDU). We have used SHARP, an actinic mask-imaging microscope, to study line-width roughness (LWR) in aerial images at sub-nanometer resolution. We studied the impact of photon density and the illumination partial coherence on recorded images, and found that at low coherence settings, the line-width roughness is dominated by photon noise, while at high coherence setting, the effect of speckle becomes more prominent, dominating photon noise for exposure levels of 4 photons/nm2 at threshold on the mask size.
{"title":"Aerial imaging study of the mask-induced line-width roughness of EUV lithography masks","authors":"A. Wojdyla, A. Donoghue, M. Benk, P. Naulleau, K. Goldberg","doi":"10.1117/12.2219513","DOIUrl":"https://doi.org/10.1117/12.2219513","url":null,"abstract":"EUV lithography uses reflective photomasks to print features on a wafer through the formation of an aerial image. The aerial image is influenced by the mask’s substrate and pattern roughness and by photon shot noise, which collectively affect the line-width on wafer prints, with an impact on local critical dimension uniformity (LCDU). We have used SHARP, an actinic mask-imaging microscope, to study line-width roughness (LWR) in aerial images at sub-nanometer resolution. We studied the impact of photon density and the illumination partial coherence on recorded images, and found that at low coherence settings, the line-width roughness is dominated by photon noise, while at high coherence setting, the effect of speckle becomes more prominent, dominating photon noise for exposure levels of 4 photons/nm2 at threshold on the mask size.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"9776 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129466793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Chi, Chi-Chun Liu, Luciana Meli, K. Schmidt, Yongan Xu, Ekmini Anuja DeSilva, M. Sanchez, R. Farrell, Hongyun Cottle, Daiji Kawamura, L. Singh, Tsuyoshi Furukawa, K. Lai, J. Pitera, D. Sanders, D. Hetzer, A. Metz, N. Felix, J. Arnold, M. Colburn
Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.
{"title":"DSA via hole shrink for advanced node applications","authors":"C. Chi, Chi-Chun Liu, Luciana Meli, K. Schmidt, Yongan Xu, Ekmini Anuja DeSilva, M. Sanchez, R. Farrell, Hongyun Cottle, Daiji Kawamura, L. Singh, Tsuyoshi Furukawa, K. Lai, J. Pitera, D. Sanders, D. Hetzer, A. Metz, N. Felix, J. Arnold, M. Colburn","doi":"10.1117/12.2219706","DOIUrl":"https://doi.org/10.1117/12.2219706","url":null,"abstract":"Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121373108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Kato, J. Konishi, M. Ikota, S. Yamaguchi, Y. Seino, Hironobu Sato, Y. Kasahara, T. Azuma
Directed self-assembly (DSA) applying chemical epitaxy is one of the promising lithographic solutions for next generation semiconductor device manufacturing. Especially, DSA lithography using coordinated line epitaxy (COOL) process is obviously one of candidates which could be the first generation of DSA applying PS-b-PMMA block copolymer (BCP) for sub-15nm dense line patterning . DSA can enhance the pitch resolutions, and can mitigate CD errors to the values much smaller than those of the originally exposed guiding patterns. On the other hand, local line placement error often results in a worse value, with distinctive trends depending on the process conditions. To address this issue, we introduce an enhanced measurement technology of DSA line patterns with distinguishing their locations in order to evaluate nature of edge placement and roughness corresponding to individual pattern locations by using images of CD-SEM. Additionally correlations among edge roughness of each line and each space are evaluated and discussed. This method can visualize features of complicated roughness easily to control COOL process. As a result, we found the followings. (1) Line placement error and line placement roughness of DSA were slightly different each other depending on their relative position to the chemical guide patterns. (2) In middle frequency area of PSD (Power Spectral Density) analysis graphs, it was observed that shapes were sensitively changed by process conditions of chemical stripe guide size and anneals temperature. (3) Correlation coefficient analysis using PSD was able to clarify characteristics of latent defect corresponding to physical and chemical property of BCP materials.
{"title":"Advanced CD-SEM metrology for qualification of DSA patterns using coordinated line epitaxy (COOL) process","authors":"T. Kato, J. Konishi, M. Ikota, S. Yamaguchi, Y. Seino, Hironobu Sato, Y. Kasahara, T. Azuma","doi":"10.1117/12.2218605","DOIUrl":"https://doi.org/10.1117/12.2218605","url":null,"abstract":"Directed self-assembly (DSA) applying chemical epitaxy is one of the promising lithographic solutions for next generation semiconductor device manufacturing. Especially, DSA lithography using coordinated line epitaxy (COOL) process is obviously one of candidates which could be the first generation of DSA applying PS-b-PMMA block copolymer (BCP) for sub-15nm dense line patterning . DSA can enhance the pitch resolutions, and can mitigate CD errors to the values much smaller than those of the originally exposed guiding patterns. On the other hand, local line placement error often results in a worse value, with distinctive trends depending on the process conditions. To address this issue, we introduce an enhanced measurement technology of DSA line patterns with distinguishing their locations in order to evaluate nature of edge placement and roughness corresponding to individual pattern locations by using images of CD-SEM. Additionally correlations among edge roughness of each line and each space are evaluated and discussed. This method can visualize features of complicated roughness easily to control COOL process. As a result, we found the followings. (1) Line placement error and line placement roughness of DSA were slightly different each other depending on their relative position to the chemical guide patterns. (2) In middle frequency area of PSD (Power Spectral Density) analysis graphs, it was observed that shapes were sensitively changed by process conditions of chemical stripe guide size and anneals temperature. (3) Correlation coefficient analysis using PSD was able to clarify characteristics of latent defect corresponding to physical and chemical property of BCP materials.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131423188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Morita, M. Kanno, Ryousuke Yamamoto, N. Sasao, Shinobu Sugimura
In next generation lithography to make sub-15nm pattern, Directed self-assembly (DSA) and Nano-imprint lithography (NIL) are proposed. The current DSA process is complicated and it is difficult to decrease width and line edge roughness of a guide pattern for sub-15nm patterning. In the case of NIL, it is difficult to make the master template having sub- 15nm pattern. This paper describes cost-effective lithography process for making sub-15nm pattern using DSA on a guide pattern replicated by Nano-imprinting (NIL + DSA). Simple process for making sub-15nm pattern is proposed. The quartz templates are made and line/space patterns of half pitch (hp) 12nm and hp9.5nm are obtained by NIL + DSA.
{"title":"Sub-15nm patterning technology using directed self-assembly on nano-imprinting guide","authors":"S. Morita, M. Kanno, Ryousuke Yamamoto, N. Sasao, Shinobu Sugimura","doi":"10.1117/12.2219141","DOIUrl":"https://doi.org/10.1117/12.2219141","url":null,"abstract":"In next generation lithography to make sub-15nm pattern, Directed self-assembly (DSA) and Nano-imprint lithography (NIL) are proposed. The current DSA process is complicated and it is difficult to decrease width and line edge roughness of a guide pattern for sub-15nm patterning. In the case of NIL, it is difficult to make the master template having sub- 15nm pattern. This paper describes cost-effective lithography process for making sub-15nm pattern using DSA on a guide pattern replicated by Nano-imprinting (NIL + DSA). Simple process for making sub-15nm pattern is proposed. The quartz templates are made and line/space patterns of half pitch (hp) 12nm and hp9.5nm are obtained by NIL + DSA.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121492960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu-Jen Fan, M. Mellish, J. Chun, S. McWilliams, C. Montgomery, W. Montgomery
EUV lithographers have continued to reduce the barriers to high Volume Manufacturing (HVM) introduction. Tool, mask and photoresist manufacturers have made excellent progress on several fronts, including resolution of many EUV source related issues, resists for early imaging characterization, and defect inspection tooling. In this discussion, we will focus on photoresist development. For many years, the team at SUNY Polytechnic Institute (SUNY Poly) has provided results from a neutral photoresist benchmarking study, which has been quite useful in establishing the limits of currently available photoresist systems [1-5]. New photoresist systems are being developed with improving resolution, but they also have lower coated thicknesses. In an effort to continue to point out potential lithographic problem areas, SUNY Poly has been evaluating the ‘etch compatibility’ of the best performing photoresists available in order to determine if the decreasing aspect ratios would prove a detriment to etch performance. In this paper, we will show data from our most recent benchmark study. We will also include smoothing process results, as well as some post-etch results obtained using the NXE:3300B resident on the SUNY Poly campus.
{"title":"Benchmarking study of EUV resists for NXE:3300B","authors":"Yu-Jen Fan, M. Mellish, J. Chun, S. McWilliams, C. Montgomery, W. Montgomery","doi":"10.1117/12.2222065","DOIUrl":"https://doi.org/10.1117/12.2222065","url":null,"abstract":"EUV lithographers have continued to reduce the barriers to high Volume Manufacturing (HVM) introduction. Tool, mask and photoresist manufacturers have made excellent progress on several fronts, including resolution of many EUV source related issues, resists for early imaging characterization, and defect inspection tooling. In this discussion, we will focus on photoresist development. For many years, the team at SUNY Polytechnic Institute (SUNY Poly) has provided results from a neutral photoresist benchmarking study, which has been quite useful in establishing the limits of currently available photoresist systems [1-5]. New photoresist systems are being developed with improving resolution, but they also have lower coated thicknesses. In an effort to continue to point out potential lithographic problem areas, SUNY Poly has been evaluating the ‘etch compatibility’ of the best performing photoresists available in order to determine if the decreasing aspect ratios would prove a detriment to etch performance. In this paper, we will show data from our most recent benchmark study. We will also include smoothing process results, as well as some post-etch results obtained using the NXE:3300B resident on the SUNY Poly campus.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133883848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hironobu Sato, Y. Kasahara, N. Kihara, Y. Seino, K. Miyagi, S. Minegishi, H. Kubota, Katsutoshi Kobayashi, H. Kanai, K. Kodera, Yoshiaki Kawamonzen, M. Shiraishi, H. Yamano, S. Nomura, T. Azuma, T. Hayakawa
Si-rich poly((polyhedral oligomeric silsesquioxane) methacrylate)-b-poly(trifluoroethyl methacrylate) (PMAPOSS-b- PTFEMA) was used to form 8-nm half-pitch line and space (L/S) pattern via grapho-epitaxy. Vertical alignment of the lamellae was achieved without using either a neutral layer or top-coating material. Because PMAPOSS-b-PTFEMA forms vertical lamellae on a variety of substrates, we used two types of physical guide structures for grapho-epitaxy; one was a substrate guide and the other was a guide with an embedded under layer. On the substrate guide structure, a fine L/S pattern was obtained with trench widths equal to 3–7 periods of the lamella spacing of the block copolymer, Lo. However, on the embedded under layer guide structure, L/S pattern was observed only with 3 Lo and 4 Lo in trench width. Cross-sectional transmission electron microscope images revealed that a thick PMAPOSS layer was formed under the PMAPOSS-b-PTFEMA L/S pattern. Pattern transfer of the PMAPOSS-b-PTFEMA L/S pattern was prevented by a thick PMAPOSS layer. To achieve pattern transfer to the under layer, optimization of the surface properties is necessary.
{"title":"Grapho-epitaxial sub-10nm line and space patterning using lamellar-forming Si-containing block copolymer","authors":"Hironobu Sato, Y. Kasahara, N. Kihara, Y. Seino, K. Miyagi, S. Minegishi, H. Kubota, Katsutoshi Kobayashi, H. Kanai, K. Kodera, Yoshiaki Kawamonzen, M. Shiraishi, H. Yamano, S. Nomura, T. Azuma, T. Hayakawa","doi":"10.1117/12.2218758","DOIUrl":"https://doi.org/10.1117/12.2218758","url":null,"abstract":"Si-rich poly((polyhedral oligomeric silsesquioxane) methacrylate)-b-poly(trifluoroethyl methacrylate) (PMAPOSS-b- PTFEMA) was used to form 8-nm half-pitch line and space (L/S) pattern via grapho-epitaxy. Vertical alignment of the lamellae was achieved without using either a neutral layer or top-coating material. Because PMAPOSS-b-PTFEMA forms vertical lamellae on a variety of substrates, we used two types of physical guide structures for grapho-epitaxy; one was a substrate guide and the other was a guide with an embedded under layer. On the substrate guide structure, a fine L/S pattern was obtained with trench widths equal to 3–7 periods of the lamella spacing of the block copolymer, Lo. However, on the embedded under layer guide structure, L/S pattern was observed only with 3 Lo and 4 Lo in trench width. Cross-sectional transmission electron microscope images revealed that a thick PMAPOSS layer was formed under the PMAPOSS-b-PTFEMA L/S pattern. Pattern transfer of the PMAPOSS-b-PTFEMA L/S pattern was prevented by a thick PMAPOSS layer. To achieve pattern transfer to the under layer, optimization of the surface properties is necessary.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128858459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Seino, Hironobu Sato, Y. Kasahara, S. Minegishi, K. Miyagi, H. Kubota, H. Kanai, K. Kodera, M. Shiraishi, N. Kihara, Yoshiaki Kawamonzen, T. Tobana, Katsutoshi Kobayashi, H. Yamano, T. Azuma, S. Nomura
Our target at EIDEC is to study the feasibility of directed self-assembly (DSA) technology for semiconductor device manufacturing through electrical yield verification by development of such as process, material, metrology, simulation and design for DSA. We previously developed a grapho/chemo-hybrid coordinated line epitaxial process for sub-15-nm line-and-space (L/S) patterning using polystyrene-block-poly(methyl methacrylate) lamellar block copolymers (BCPs)1– 3. Electrical yield verification results showed that a 30% open yield was successfully achieved with a metal wire line length of 700 μm 4. In the next stage of the evaluation, a sub-10-nm L/S DSA patterning process based on graphoepitaxial DSA of 20-nm lamellar period organic BCPs was developed based on neutral layer and guide space width optimization. At a 30-nm guide height, problems such as BCP overflow and DSA line shorts were observed after the dry development. At a 60-nm guide height, grid-like short defects were observed under dry development shallow etch conditions and sub-10-nm L/S patterns were formed under optimized etch conditions with a suitable BCP film thickness margin. The process performance was evaluated in terms of defects and critical dimension measurements using an electron beam inspection system and critical dimension-scanning electron microscope metrology. The main DSA defects were short defects, and the spatial roughness appeared to be caused by the periodic pitches of these short defects and the guide roughness. We successfully demonstrated the fabrication of sub-10-nm metal wires consists of L/S, pad, connect and cut patterns with controlled alignment and stack structure through lithography, etching and CMP process on a 300- mm wafer using the fully integrated DSA process and damascene processing.
{"title":"Sub-10nm lines and spaces patterning using grapho-epitaxial directed self-assembly of lamellar block copolymers","authors":"Y. Seino, Hironobu Sato, Y. Kasahara, S. Minegishi, K. Miyagi, H. Kubota, H. Kanai, K. Kodera, M. Shiraishi, N. Kihara, Yoshiaki Kawamonzen, T. Tobana, Katsutoshi Kobayashi, H. Yamano, T. Azuma, S. Nomura","doi":"10.1117/12.2218787","DOIUrl":"https://doi.org/10.1117/12.2218787","url":null,"abstract":"Our target at EIDEC is to study the feasibility of directed self-assembly (DSA) technology for semiconductor device manufacturing through electrical yield verification by development of such as process, material, metrology, simulation and design for DSA. We previously developed a grapho/chemo-hybrid coordinated line epitaxial process for sub-15-nm line-and-space (L/S) patterning using polystyrene-block-poly(methyl methacrylate) lamellar block copolymers (BCPs)1– 3. Electrical yield verification results showed that a 30% open yield was successfully achieved with a metal wire line length of 700 μm 4. In the next stage of the evaluation, a sub-10-nm L/S DSA patterning process based on graphoepitaxial DSA of 20-nm lamellar period organic BCPs was developed based on neutral layer and guide space width optimization. At a 30-nm guide height, problems such as BCP overflow and DSA line shorts were observed after the dry development. At a 60-nm guide height, grid-like short defects were observed under dry development shallow etch conditions and sub-10-nm L/S patterns were formed under optimized etch conditions with a suitable BCP film thickness margin. The process performance was evaluated in terms of defects and critical dimension measurements using an electron beam inspection system and critical dimension-scanning electron microscope metrology. The main DSA defects were short defects, and the spatial roughness appeared to be caused by the periodic pitches of these short defects and the guide roughness. We successfully demonstrated the fabrication of sub-10-nm metal wires consists of L/S, pad, connect and cut patterns with controlled alignment and stack structure through lithography, etching and CMP process on a 300- mm wafer using the fully integrated DSA process and damascene processing.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115805437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Böhme, C. Girardot, J. Garnier, J. Arias‐Zapata, S. Arnaud, R. Tiron, O. Marconot, D. Buttard, M. Zelsmann
In this work, we present completely industry adapted processes for high-chi PS-PDMS block copolymers. DSA was performed on trenches fabricated within standard photolithography stacks and pattern transfer was made by using etching processes similar to those used for gate etching in industry. We propose the alignment of two different PS-PDMS (45.5kg/mol, 16kg/mol) solely by thermal annealing. By adding plasticizer molecules in the high molecular weight BCP (45.5k), we have not only avoided solvent vapor annealing but also reduced significantly the processing time. The properties of the guiding lines and the quality of the final BCP hard mask (CD uniformity, LWR, LER) were investigated.
{"title":"A route for industry compatible directed self-assembly of high-chi PS-PDMS block copolymers","authors":"S. Böhme, C. Girardot, J. Garnier, J. Arias‐Zapata, S. Arnaud, R. Tiron, O. Marconot, D. Buttard, M. Zelsmann","doi":"10.1117/12.2219312","DOIUrl":"https://doi.org/10.1117/12.2219312","url":null,"abstract":"In this work, we present completely industry adapted processes for high-chi PS-PDMS block copolymers. DSA was performed on trenches fabricated within standard photolithography stacks and pattern transfer was made by using etching processes similar to those used for gate etching in industry. We propose the alignment of two different PS-PDMS (45.5kg/mol, 16kg/mol) solely by thermal annealing. By adding plasticizer molecules in the high molecular weight BCP (45.5k), we have not only avoided solvent vapor annealing but also reduced significantly the processing time. The properties of the guiding lines and the quality of the final BCP hard mask (CD uniformity, LWR, LER) were investigated.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126364707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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