S. Levi, I. Schwarzband, R. Kris, O. Adan, Elly Shi, Ying Zhang, Kevin A. Zhou
Self-Aligned Quadruple Patterning (SAQP) is targeted to support the sub 10nm technology nodes. It is consisted of several process steps starting with lithography and Etch to define the pattern backbone. Followed by additional set of processes based on thin-films deposition and etch that quadruple the number of patterns, shrinking pattern and pitch sizes. Pattern roughness is derived from the physical and chemical characteristics of these process steps. It is changing with each of the SAQP process steps, based on material stack and the etch process characteristics. Relative to a sub 10 nm pattern sizes pattern, edge roughness can significantly impact pattern physical dimensions. Unless controlled it can increase the variability of device electrical performance, and reduce yield. In this paper we present the SAQP process steps and roughness characterization, performed with Power Spectral Density (PSD) methodology. Experimental results demonstrates the ability of PSD analysis to sensitively reflect detailed characterization of process roughness, guiding process development improvements, and enabling roughness monitoring for production.
{"title":"Edge roughness characterization of advanced patterning processes using power spectral density analysis (PSD)","authors":"S. Levi, I. Schwarzband, R. Kris, O. Adan, Elly Shi, Ying Zhang, Kevin A. Zhou","doi":"10.1117/12.2220814","DOIUrl":"https://doi.org/10.1117/12.2220814","url":null,"abstract":"Self-Aligned Quadruple Patterning (SAQP) is targeted to support the sub 10nm technology nodes. It is consisted of several process steps starting with lithography and Etch to define the pattern backbone. Followed by additional set of processes based on thin-films deposition and etch that quadruple the number of patterns, shrinking pattern and pitch sizes. Pattern roughness is derived from the physical and chemical characteristics of these process steps. It is changing with each of the SAQP process steps, based on material stack and the etch process characteristics. Relative to a sub 10 nm pattern sizes pattern, edge roughness can significantly impact pattern physical dimensions. Unless controlled it can increase the variability of device electrical performance, and reduce yield. In this paper we present the SAQP process steps and roughness characterization, performed with Power Spectral Density (PSD) methodology. Experimental results demonstrates the ability of PSD analysis to sensitively reflect detailed characterization of process roughness, guiding process development improvements, and enabling roughness monitoring for production.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"299 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132520200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Amrit K. Narasimhan, Steven Grzeskowiak, Jonathan Ostrander, Jonathon Schad, E. Rebeyev, M. Neisser, L. Ocola, G. Denbeaux, R. Brainard
In extreme ultraviolet (EUV) lithography, 92 eV photons are used to expose photoresists. Typical EUV resists are organic-based and chemically amplified using photoacid generators (PAGs). Upon exposure, PAGs produce acids which catalyze reactions that result in changes in solubility. In EUV lithography, photo- and secondary electrons (energies of 10- 80 eV) play a large role in PAG acid-production. Several mechanisms for electron-PAG interactions (e.g. electron trapping, and hole-initiated chemistry) have been proposed. The aim of this study is to explore another mechanism – internal excitation – in which a bound PAG electron can be excited by receiving energy from another energetic electron, causing a reaction that produces acid. This paper explores the mechanism of internal excitation through the analogous process of electron-induced fluorescence, in which an electron loses energy by transferring that energy to a molecule and that molecule emits a photon rather than decomposing. We will show and quantify electron-induced fluorescence of several fluorophores in polymer films to mimic resist materials, and use this information to refine our proposed mechanism. Relationships between the molecular structure of fluorophores and fluorescent quantum yield may aid in the development of novel PAGs for EUV lithography.
{"title":"Studying electron-PAG interactions using electron-induced fluorescence","authors":"Amrit K. Narasimhan, Steven Grzeskowiak, Jonathan Ostrander, Jonathon Schad, E. Rebeyev, M. Neisser, L. Ocola, G. Denbeaux, R. Brainard","doi":"10.1117/12.2219850","DOIUrl":"https://doi.org/10.1117/12.2219850","url":null,"abstract":"In extreme ultraviolet (EUV) lithography, 92 eV photons are used to expose photoresists. Typical EUV resists are organic-based and chemically amplified using photoacid generators (PAGs). Upon exposure, PAGs produce acids which catalyze reactions that result in changes in solubility. In EUV lithography, photo- and secondary electrons (energies of 10- 80 eV) play a large role in PAG acid-production. Several mechanisms for electron-PAG interactions (e.g. electron trapping, and hole-initiated chemistry) have been proposed. The aim of this study is to explore another mechanism – internal excitation – in which a bound PAG electron can be excited by receiving energy from another energetic electron, causing a reaction that produces acid. This paper explores the mechanism of internal excitation through the analogous process of electron-induced fluorescence, in which an electron loses energy by transferring that energy to a molecule and that molecule emits a photon rather than decomposing. We will show and quantify electron-induced fluorescence of several fluorophores in polymer films to mimic resist materials, and use this information to refine our proposed mechanism. Relationships between the molecular structure of fluorophores and fluorescent quantum yield may aid in the development of novel PAGs for EUV lithography.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122746909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we presented the filtration effects on block copolymers (BCP) that are commonly used in directed self-assembly lithographic (DSAL) imaging schemes. Specifically we focused on filtration effects on micro-contaminants such as metal ions and metal induced gels. Gel removal efficiency studies carried out with HDPE, Nylon and PTFE filters pointed out that Nylon 6,6 membrane is the most effective in removing gels in block copolymer (BCP) solutions. Metal removal efficiency studies were conducted using multistep filtrations such as repetitive filtration of single membrane material and combination of different type of membranes. Results showed that a combination of Nylon-6,6 and ion-exchange filters is highly effective in reducing metals such as Li, Mg and Al to > 99.99% efficiency. The mechanism of metal removal efficiency is discussed in detail.
{"title":"Filtration on block copolymer solution used in directed self assembly lithography","authors":"T. Umeda, T. Takakura, S. Tsuzuki","doi":"10.1117/12.2219423","DOIUrl":"https://doi.org/10.1117/12.2219423","url":null,"abstract":"In this paper, we presented the filtration effects on block copolymers (BCP) that are commonly used in directed self-assembly lithographic (DSAL) imaging schemes. Specifically we focused on filtration effects on micro-contaminants such as metal ions and metal induced gels. Gel removal efficiency studies carried out with HDPE, Nylon and PTFE filters pointed out that Nylon 6,6 membrane is the most effective in removing gels in block copolymer (BCP) solutions. Metal removal efficiency studies were conducted using multistep filtrations such as repetitive filtration of single membrane material and combination of different type of membranes. Results showed that a combination of Nylon-6,6 and ion-exchange filters is highly effective in reducing metals such as Li, Mg and Al to > 99.99% efficiency. The mechanism of metal removal efficiency is discussed in detail.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"1037 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116271502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Eri Hirahara, M. Paunescu, O. Polishchuk, E. Jeong, Edward Ng, J. Shan, Jian Yin, Jihoon Kim, Yi Cao, Jin Li, Sungeun Hong, D. Baskaran, Guanyang Lin
To extend directed self-assembly (DSA) of poly(styrene-b-methyl methacrylate) (PS-b-PMMA) for higher resolution, placement accuracy and potentially improved pattern line edge roughness (LER), we have developed a next-generation material platform of organic high-χ block copolymers (“HC series”, AZEMBLYTM EXP PME-3000 series). The new material platform has a built-in orientation control mechanism which enables block copolymer domains to vertically selforient without topcoat/additive or delicate solvent vapor annealing. Furthermore, sub-10 nm lines and spaces (L/S) patterning by two major chemoepitaxy DSA, LiNe and SMARTTM processes, was successfully implemented on 12” wafer substrates by using the PME-3000 lamellar series. The results revealed that the new material platform is compatible with the existing PS-b-PMMA-based chemical prepatterns and standard protocols. We also introduced the built-in orientation control strategy to the conventional PS-b-PMMA system, producing a new generation of PS-b-PMMA materials with facile orientation control. The modified PS-b-PMMA (m-PS-b-PMMA) performed LiNe flow DSA yielding a comparable CD process window with improved LER/LWR/SWR after the L/S patterns were transferred into a Si substrate.
{"title":"Directed self-assembly materials for high resolution beyond PS-b-PMMA","authors":"Eri Hirahara, M. Paunescu, O. Polishchuk, E. Jeong, Edward Ng, J. Shan, Jian Yin, Jihoon Kim, Yi Cao, Jin Li, Sungeun Hong, D. Baskaran, Guanyang Lin","doi":"10.1117/12.2220424","DOIUrl":"https://doi.org/10.1117/12.2220424","url":null,"abstract":"To extend directed self-assembly (DSA) of poly(styrene-b-methyl methacrylate) (PS-b-PMMA) for higher resolution, placement accuracy and potentially improved pattern line edge roughness (LER), we have developed a next-generation material platform of organic high-χ block copolymers (“HC series”, AZEMBLYTM EXP PME-3000 series). The new material platform has a built-in orientation control mechanism which enables block copolymer domains to vertically selforient without topcoat/additive or delicate solvent vapor annealing. Furthermore, sub-10 nm lines and spaces (L/S) patterning by two major chemoepitaxy DSA, LiNe and SMARTTM processes, was successfully implemented on 12” wafer substrates by using the PME-3000 lamellar series. The results revealed that the new material platform is compatible with the existing PS-b-PMMA-based chemical prepatterns and standard protocols. We also introduced the built-in orientation control strategy to the conventional PS-b-PMMA system, producing a new generation of PS-b-PMMA materials with facile orientation control. The modified PS-b-PMMA (m-PS-b-PMMA) performed LiNe flow DSA yielding a comparable CD process window with improved LER/LWR/SWR after the L/S patterns were transferred into a Si substrate.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134376272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We explored the metal removal efficiency of Nylon 6,6 and HDPE (High Density Polyethylene) membrane based filters, in solvents of varying degree of polarity such as Cyclohexanone and 70:30 mixture of PGME (Propylene Glycol Monomethyl Ether) and PGMEA (Propylene Glycol Monomethyl Ether), In all the solvents tested, Nylon 6,6 membrane filtration was found to be significantly more effective in removing metals than HDPE membranes, regardless of their respective membrane pore sizes. Hydrophilic interaction chromatography (HILIC) mechanism was invoked to rationalize metal removal efficiency dependence on solvent hydrophobicity.
{"title":"Metal reduction at point-of-use filtration","authors":"T. Umeda, S. Daikoku, R. Varanasi, S. Tsuzuki","doi":"10.1117/12.2218400","DOIUrl":"https://doi.org/10.1117/12.2218400","url":null,"abstract":"We explored the metal removal efficiency of Nylon 6,6 and HDPE (High Density Polyethylene) membrane based filters, in solvents of varying degree of polarity such as Cyclohexanone and 70:30 mixture of PGME (Propylene Glycol Monomethyl Ether) and PGMEA (Propylene Glycol Monomethyl Ether), In all the solvents tested, Nylon 6,6 membrane filtration was found to be significantly more effective in removing metals than HDPE membranes, regardless of their respective membrane pore sizes. Hydrophilic interaction chromatography (HILIC) mechanism was invoked to rationalize metal removal efficiency dependence on solvent hydrophobicity.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123553043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Leon Verstappen, E. Mos, Peter H Wardenier, H. Megens, Emil Schmitt-Weaver, K. Bhattacharyya, O. Adam, G. Grzela, Joost van Heijst, Lotte Willems, Jochem Wildenberg, Velislava Ignatova, Albert Chen, Frank Elich, B. Rajasekharan, Lydia Vergaij-Huizer, Brian Lewis, M. Kea, J. Mulkens
Multi-patterning lithography at the 10-nm and 7-nm nodes is driving the allowed overlay error down to extreme low values. Advanced high order overlay correction schemes are needed to control the process variability. Additionally the increase of the number of split layers results in an exponential increase of metrology complexity of the total overlay and alignment tree. At the same time, the process stack includes more hard-mask steps and becomes more and more complex, with as consequence that the setup and verification of the overlay metrology recipe becomes more critical. All of the above require a holistic approach that addresses total overlay optimization from process design to process setup and control in volume manufacturing. In this paper we will present the holistic overlay control flow designed for 10-nm and 7-nm nodes and illustrate the achievable ultimate overlay performance for a logic and DRAM use case. As figure 1 illustrates we will explain the details of the steps in the holistic flow. Overlay accuracy is the driver for target design and metrology tool optimization like wavelength and polarization. We will show that it is essential to include processing effects like etching and CMP which can result in a physical asymmetry of the bottom grating of diffraction based overlay targets. We will introduce a new method to create a reference overlay map, based on metrology data using multiple wavelengths and polarization settings. A similar approach is developed for the wafer alignment step. The overlay fingerprint correction using linear or high order correction per exposure (CPE) has a large amount of parameters. It is critical to balance the metrology noise with the ultimate correction model and the related metrology sampling scheme. Similar approach is needed for the wafer align step. Both for overlay control as well as alignment we have developed methods which include efficient use of metrology time, available for an in the litho-cluster integrated metrology use. These methods include a novel set models that efficiently describe different process fingerprints. We will explain the methods and show the benefits for logic and DRAM use cases.
{"title":"Holistic overlay control for multi-patterning process layers at the 10nm and 7nm nodes","authors":"Leon Verstappen, E. Mos, Peter H Wardenier, H. Megens, Emil Schmitt-Weaver, K. Bhattacharyya, O. Adam, G. Grzela, Joost van Heijst, Lotte Willems, Jochem Wildenberg, Velislava Ignatova, Albert Chen, Frank Elich, B. Rajasekharan, Lydia Vergaij-Huizer, Brian Lewis, M. Kea, J. Mulkens","doi":"10.1117/12.2230390","DOIUrl":"https://doi.org/10.1117/12.2230390","url":null,"abstract":"Multi-patterning lithography at the 10-nm and 7-nm nodes is driving the allowed overlay error down to extreme low values. Advanced high order overlay correction schemes are needed to control the process variability. Additionally the increase of the number of split layers results in an exponential increase of metrology complexity of the total overlay and alignment tree. At the same time, the process stack includes more hard-mask steps and becomes more and more complex, with as consequence that the setup and verification of the overlay metrology recipe becomes more critical. All of the above require a holistic approach that addresses total overlay optimization from process design to process setup and control in volume manufacturing. In this paper we will present the holistic overlay control flow designed for 10-nm and 7-nm nodes and illustrate the achievable ultimate overlay performance for a logic and DRAM use case. As figure 1 illustrates we will explain the details of the steps in the holistic flow. Overlay accuracy is the driver for target design and metrology tool optimization like wavelength and polarization. We will show that it is essential to include processing effects like etching and CMP which can result in a physical asymmetry of the bottom grating of diffraction based overlay targets. We will introduce a new method to create a reference overlay map, based on metrology data using multiple wavelengths and polarization settings. A similar approach is developed for the wafer alignment step. The overlay fingerprint correction using linear or high order correction per exposure (CPE) has a large amount of parameters. It is critical to balance the metrology noise with the ultimate correction model and the related metrology sampling scheme. Similar approach is needed for the wafer align step. Both for overlay control as well as alignment we have developed methods which include efficient use of metrology time, available for an in the litho-cluster integrated metrology use. These methods include a novel set models that efficiently describe different process fingerprints. We will explain the methods and show the benefits for logic and DRAM use cases.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121917600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Yaegashi, K. Oyama, A. Hara, Sakurako Natori, Shohei Yamauchi, Masatoshi Yamato, K. Koike
One of the practical candidates to produce 7nm node logic devices is to use the multiple patterning with 193-immersion exposure. For the multiple patterning, it is important to evaluate the relation between the number of mask layer and the minimum pitch systematically to judge the device manufacturability. Although the number of the time of patterning, namely LE(Litho-Etch) ^ x-time, and overlay steps have to be reduced, there are some challenges in miniaturization of hole size below 20nm. Various process fluctuations on contact hole have a direct impact on device performance. According to the technical trend, 12nm diameter hole on 30nm-pitch hole will be needed on 7nm node. Extreme ultraviolet lithography (EUV) and Directed self-assembly (DSA) are attracting considerable attention to obtain small feature size pattern, however, 193-immersion still has the potential to extend optical lithography cost-effectively for sub-7nm node. The objective of this work is to study the process variation challenges and resolution in post-processing for the CD-bias control to meet sub-20nm diameter contact hole. Another pattern modulation is also demonstrated during post-processing step for hole shrink. With the realization that pattern fidelity and pattern placement management will limit scaling long before devices and interconnects fail to perform intrinsically, the talk will also outline how circle edge roughness (CER) and Local-CD uniformity can correct efficiency. On the other hand, 1D Gridded-Design-Rules layout (1D layout) has simple rectangular shapes. Also, we have demonstrated CD-bias modification on short trench pattern to cut grating line for its fabrication.
{"title":"Considerations for fine hole patterning for the 7nm node","authors":"H. Yaegashi, K. Oyama, A. Hara, Sakurako Natori, Shohei Yamauchi, Masatoshi Yamato, K. Koike","doi":"10.1117/12.2218774","DOIUrl":"https://doi.org/10.1117/12.2218774","url":null,"abstract":"One of the practical candidates to produce 7nm node logic devices is to use the multiple patterning with 193-immersion exposure. For the multiple patterning, it is important to evaluate the relation between the number of mask layer and the minimum pitch systematically to judge the device manufacturability. Although the number of the time of patterning, namely LE(Litho-Etch) ^ x-time, and overlay steps have to be reduced, there are some challenges in miniaturization of hole size below 20nm. Various process fluctuations on contact hole have a direct impact on device performance. According to the technical trend, 12nm diameter hole on 30nm-pitch hole will be needed on 7nm node. Extreme ultraviolet lithography (EUV) and Directed self-assembly (DSA) are attracting considerable attention to obtain small feature size pattern, however, 193-immersion still has the potential to extend optical lithography cost-effectively for sub-7nm node. The objective of this work is to study the process variation challenges and resolution in post-processing for the CD-bias control to meet sub-20nm diameter contact hole. Another pattern modulation is also demonstrated during post-processing step for hole shrink. With the realization that pattern fidelity and pattern placement management will limit scaling long before devices and interconnects fail to perform intrinsically, the talk will also outline how circle edge roughness (CER) and Local-CD uniformity can correct efficiency. On the other hand, 1D Gridded-Design-Rules layout (1D layout) has simple rectangular shapes. Also, we have demonstrated CD-bias modification on short trench pattern to cut grating line for its fabrication.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"34 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113981017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Noya, Y. Hama, Maki Ishii, S. Nakasugi, T. Kudo, M. Padmanaban
Spin-on-carbon hard mask (SOC HM) has been used in semiconductor manufacturing since 45nm node as an alternative carbon hard mask process to chemical vapor deposition (CVD). As advancement of semiconductor to 2X nm nodes and beyond, multiple patterning technology is used and planarization of topography become more important and challenging ever before. In order to develop next generation SOC, one of focuses is planarization of topography. SOC with different concepts for improved planarization and the influence of thermal flow temperature, crosslink, film shrinkage, baking conditions on planarization and filling performance are described in this paper.
{"title":"Planarization of topography with spin-on carbon hard mask","authors":"G. Noya, Y. Hama, Maki Ishii, S. Nakasugi, T. Kudo, M. Padmanaban","doi":"10.1117/12.2218504","DOIUrl":"https://doi.org/10.1117/12.2218504","url":null,"abstract":"Spin-on-carbon hard mask (SOC HM) has been used in semiconductor manufacturing since 45nm node as an alternative carbon hard mask process to chemical vapor deposition (CVD). As advancement of semiconductor to 2X nm nodes and beyond, multiple patterning technology is used and planarization of topography become more important and challenging ever before. In order to develop next generation SOC, one of focuses is planarization of topography. SOC with different concepts for improved planarization and the influence of thermal flow temperature, crosslink, film shrinkage, baking conditions on planarization and filling performance are described in this paper.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131428350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Amblard, Sarah Purdy, R. Cooper, Marjory Hockaday
The overall quality and processing capability of lithographic materials are critical for ensuring high device yield and performance at sub-20nm technology nodes in a high volume manufacturing environment. Insufficient process margin and high line width roughness (LWR) cause poor manufacturing control, while high defectivity causes product failures. In this paper, we focus on the most critical layer of a sub-20nm technology node LSI device, and present an improved method for characterizing both lithographic and post-patterning defectivity performance of state-of-the-art immersion photoresists. Multiple formulations from different suppliers were used and compared. Photoresists were tested under various process conditions, and multiple lithographic metrics were investigated (depth of focus, exposure dose latitude, line width roughness, etc.). Results were analyzed and combined using an innovative approach based on advanced software, providing clearer results than previously available. This increased detail enables more accurate performance comparisons among the different photoresists. Post-patterning defectivity was also quantified, with defects reviewed and classified using state-of-the-art inspection tools. Correlations were established between the lithographic and post-patterning defectivity performances for each material, and overall ranking was established among the photoresists, enabling the selection of the best performer for implementation in a high volume manufacturing environment.
{"title":"An improved method for characterizing photoresist lithographic and defectivity performance for sub-20nm node lithography","authors":"G. Amblard, Sarah Purdy, R. Cooper, Marjory Hockaday","doi":"10.1117/12.2219375","DOIUrl":"https://doi.org/10.1117/12.2219375","url":null,"abstract":"The overall quality and processing capability of lithographic materials are critical for ensuring high device yield and performance at sub-20nm technology nodes in a high volume manufacturing environment. Insufficient process margin and high line width roughness (LWR) cause poor manufacturing control, while high defectivity causes product failures. In this paper, we focus on the most critical layer of a sub-20nm technology node LSI device, and present an improved method for characterizing both lithographic and post-patterning defectivity performance of state-of-the-art immersion photoresists. Multiple formulations from different suppliers were used and compared. Photoresists were tested under various process conditions, and multiple lithographic metrics were investigated (depth of focus, exposure dose latitude, line width roughness, etc.). Results were analyzed and combined using an innovative approach based on advanced software, providing clearer results than previously available. This increased detail enables more accurate performance comparisons among the different photoresists. Post-patterning defectivity was also quantified, with defects reviewed and classified using state-of-the-art inspection tools. Correlations were established between the lithographic and post-patterning defectivity performances for each material, and overall ranking was established among the photoresists, enabling the selection of the best performer for implementation in a high volume manufacturing environment.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134305041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, as next-generation lithography, various exposure techniques have been studied such as Extreme Ultraviolet Lithography (EUVL), Directed Self Assembly (DSA) and multiple patterning processes. In particular, EUVL is the most promising candidate for the high volume manufacturing below N7 node. However, there are many problems to be solved such as materials, through put of the exposure tool and mask defect. With respect to the DSA, the fine patterning with block copolymer has been studied. But the DSA process also has the several problems such as the complicated process flow in chemo process, quality of the block copolymer and defect. On the other hand, although the multiple patterning has been applied the device manufacturing for several years, there are some problems such as significant increase in cost due to increasing of the process steps and the overlay accuracy at the multiple process steps. Therefore, Pattern Trimming Materials (PTM) and Pattern Shrink Materials (PSM) were developed for miniaturization using the current exposure technology. The PTM is applied on a resist pattern produced in a Positive Tone Development (PTD) process and trim the resist pattern. It is possible to control the trimming amount by changing the formulation and the baking process. It has been confirmed that the effectiveness of PTM is not only for the L/S pattern, but also for the 2D pattern like pillar pattern. At the same time, it is confirmed that the PTM can improve the Line Width Roughness (LWR) and Local Critical Dimension Uniformity (LCDU). On the other hand, the PSM is applied on the pattern prepared in a Negative Tone Imaging (NTI) process and then it can shrink the resist pattern after baking. We adopted the new concept for pattern shrinkage process which dramatically improved LCDU with the hole shrinkage. In this paper, we demonstrated the L/S and pillar pattern trimming by PTM and the C/H shrink by PSM with ArF immersion (ArF im) condition and EUV condition. In the future, PTM and PSM are expected to be applied in not only ArF im patterning process but also in EUVL.
{"title":"Novel pattern trimming and shrink material (PTM (PTD) and PSM (NTI)) for ArF/EUV extension","authors":"Tokio Nishita, Rikimaru Sakamoto","doi":"10.1117/12.2218826","DOIUrl":"https://doi.org/10.1117/12.2218826","url":null,"abstract":"In recent years, as next-generation lithography, various exposure techniques have been studied such as Extreme Ultraviolet Lithography (EUVL), Directed Self Assembly (DSA) and multiple patterning processes. In particular, EUVL is the most promising candidate for the high volume manufacturing below N7 node. However, there are many problems to be solved such as materials, through put of the exposure tool and mask defect. With respect to the DSA, the fine patterning with block copolymer has been studied. But the DSA process also has the several problems such as the complicated process flow in chemo process, quality of the block copolymer and defect. On the other hand, although the multiple patterning has been applied the device manufacturing for several years, there are some problems such as significant increase in cost due to increasing of the process steps and the overlay accuracy at the multiple process steps. Therefore, Pattern Trimming Materials (PTM) and Pattern Shrink Materials (PSM) were developed for miniaturization using the current exposure technology. The PTM is applied on a resist pattern produced in a Positive Tone Development (PTD) process and trim the resist pattern. It is possible to control the trimming amount by changing the formulation and the baking process. It has been confirmed that the effectiveness of PTM is not only for the L/S pattern, but also for the 2D pattern like pillar pattern. At the same time, it is confirmed that the PTM can improve the Line Width Roughness (LWR) and Local Critical Dimension Uniformity (LCDU). On the other hand, the PSM is applied on the pattern prepared in a Negative Tone Imaging (NTI) process and then it can shrink the resist pattern after baking. We adopted the new concept for pattern shrinkage process which dramatically improved LCDU with the hole shrinkage. In this paper, we demonstrated the L/S and pillar pattern trimming by PTM and the C/H shrink by PSM with ArF immersion (ArF im) condition and EUV condition. In the future, PTM and PSM are expected to be applied in not only ArF im patterning process but also in EUVL.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124797998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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