In recent years, as next-generation lithography, various exposure techniques have been studied such as Extreme Ultraviolet Lithography (EUVL), Directed Self Assembly (DSA) and multiple patterning processes. In particular, EUVL is the most promising candidate for the high volume manufacturing below N7 node. However, there are many problems to be solved such as materials, through put of the exposure tool and mask defect. With respect to the DSA, the fine patterning with block copolymer has been studied. But the DSA process also has the several problems such as the complicated process flow in chemo process, quality of the block copolymer and defect. On the other hand, although the multiple patterning has been applied the device manufacturing for several years, there are some problems such as significant increase in cost due to increasing of the process steps and the overlay accuracy at the multiple process steps. Therefore, Pattern Trimming Materials (PTM) and Pattern Shrink Materials (PSM) were developed for miniaturization using the current exposure technology. The PTM is applied on a resist pattern produced in a Positive Tone Development (PTD) process and trim the resist pattern. It is possible to control the trimming amount by changing the formulation and the baking process. It has been confirmed that the effectiveness of PTM is not only for the L/S pattern, but also for the 2D pattern like pillar pattern. At the same time, it is confirmed that the PTM can improve the Line Width Roughness (LWR) and Local Critical Dimension Uniformity (LCDU). On the other hand, the PSM is applied on the pattern prepared in a Negative Tone Imaging (NTI) process and then it can shrink the resist pattern after baking. We adopted the new concept for pattern shrinkage process which dramatically improved LCDU with the hole shrinkage. In this paper, we demonstrated the L/S and pillar pattern trimming by PTM and the C/H shrink by PSM with ArF immersion (ArF im) condition and EUV condition. In the future, PTM and PSM are expected to be applied in not only ArF im patterning process but also in EUVL.
{"title":"Novel pattern trimming and shrink material (PTM (PTD) and PSM (NTI)) for ArF/EUV extension","authors":"Tokio Nishita, Rikimaru Sakamoto","doi":"10.1117/12.2218826","DOIUrl":"https://doi.org/10.1117/12.2218826","url":null,"abstract":"In recent years, as next-generation lithography, various exposure techniques have been studied such as Extreme Ultraviolet Lithography (EUVL), Directed Self Assembly (DSA) and multiple patterning processes. In particular, EUVL is the most promising candidate for the high volume manufacturing below N7 node. However, there are many problems to be solved such as materials, through put of the exposure tool and mask defect. With respect to the DSA, the fine patterning with block copolymer has been studied. But the DSA process also has the several problems such as the complicated process flow in chemo process, quality of the block copolymer and defect. On the other hand, although the multiple patterning has been applied the device manufacturing for several years, there are some problems such as significant increase in cost due to increasing of the process steps and the overlay accuracy at the multiple process steps. Therefore, Pattern Trimming Materials (PTM) and Pattern Shrink Materials (PSM) were developed for miniaturization using the current exposure technology. The PTM is applied on a resist pattern produced in a Positive Tone Development (PTD) process and trim the resist pattern. It is possible to control the trimming amount by changing the formulation and the baking process. It has been confirmed that the effectiveness of PTM is not only for the L/S pattern, but also for the 2D pattern like pillar pattern. At the same time, it is confirmed that the PTM can improve the Line Width Roughness (LWR) and Local Critical Dimension Uniformity (LCDU). On the other hand, the PSM is applied on the pattern prepared in a Negative Tone Imaging (NTI) process and then it can shrink the resist pattern after baking. We adopted the new concept for pattern shrinkage process which dramatically improved LCDU with the hole shrinkage. In this paper, we demonstrated the L/S and pillar pattern trimming by PTM and the C/H shrink by PSM with ArF immersion (ArF im) condition and EUV condition. In the future, PTM and PSM are expected to be applied in not only ArF im patterning process but also in EUVL.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124797998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Weihong Gao, Xuefeng Zeng, Peter Lin, Yan Pan, Ho Young Song, Hoang Nguyen, Na Cai, Zhijin Chen, Khurram Zafar
A novel classification methodology is constructed for Electron Beam (E-Beam) die-to-database (D2DB) inspection results on contact and via layers. It is a design guided defects classification flow that helps to pin-point true defects from a large amount of false alarm defects. Die-to-database E-beam inspection has remarkable features that can help find systematic defects such as Damaged Via and Missing Via; which will be reported as DVC (Dark Voltage Contrast) defects. However, the D2DB result usually reports millions of defects that lie on both ‘active via’ and ‘floating via’, the former being defects-of-interest (DOI), and the latter being of little significance. The indiscriminant mixture of DOI (on active vias) and nuisance (on floating vias) is a challenge in the use of D2DB for finding systematic via defects. We overcome this challenge by overlaying the E-beam defect location onto the design layout file (GDS or OASIS) and tracing the path of the via to determine whether or not it connects to the active or diffusion layer. Our proposed flow uses Net Tracing Classification (NTC) feature in Anchor Hotspot Solution (AHS) to classify all the reported DVC defects into different groups, according to the electrical connectivity of the contact. This classification involves multiple interconnected process layers. All the reported DVC defects will be classified into three groups: (1) Real DVC defects, in which the net traces down to active layer; (2) False DVC type 1, in which the net traces down to gate (which is always dark); (3) False DVC type 2, in which the net traces down to floating metal (which is always dark as well). This enhanced defect classification is greatly helpful in separating real DVC contact/via defects from false alarms. It has a secondary benefit of reducing the total number of defects, which is helpful for subsequent in-depth data analysis. In addition, the verified real DVC locations can be used to generate care areas for E-Beam die-to-die (D2D) inspection, which can effectively improve throughput and reduce the turn-around-time (TAT). In this paper, we will discuss a use case at the Vx layer.
{"title":"Net tracing and classification analysis on E-beam die-to-database inspection","authors":"Weihong Gao, Xuefeng Zeng, Peter Lin, Yan Pan, Ho Young Song, Hoang Nguyen, Na Cai, Zhijin Chen, Khurram Zafar","doi":"10.1117/12.2235347","DOIUrl":"https://doi.org/10.1117/12.2235347","url":null,"abstract":"A novel classification methodology is constructed for Electron Beam (E-Beam) die-to-database (D2DB) inspection results on contact and via layers. It is a design guided defects classification flow that helps to pin-point true defects from a large amount of false alarm defects. Die-to-database E-beam inspection has remarkable features that can help find systematic defects such as Damaged Via and Missing Via; which will be reported as DVC (Dark Voltage Contrast) defects. However, the D2DB result usually reports millions of defects that lie on both ‘active via’ and ‘floating via’, the former being defects-of-interest (DOI), and the latter being of little significance. The indiscriminant mixture of DOI (on active vias) and nuisance (on floating vias) is a challenge in the use of D2DB for finding systematic via defects. We overcome this challenge by overlaying the E-beam defect location onto the design layout file (GDS or OASIS) and tracing the path of the via to determine whether or not it connects to the active or diffusion layer. Our proposed flow uses Net Tracing Classification (NTC) feature in Anchor Hotspot Solution (AHS) to classify all the reported DVC defects into different groups, according to the electrical connectivity of the contact. This classification involves multiple interconnected process layers. All the reported DVC defects will be classified into three groups: (1) Real DVC defects, in which the net traces down to active layer; (2) False DVC type 1, in which the net traces down to gate (which is always dark); (3) False DVC type 2, in which the net traces down to floating metal (which is always dark as well). This enhanced defect classification is greatly helpful in separating real DVC contact/via defects from false alarms. It has a secondary benefit of reducing the total number of defects, which is helpful for subsequent in-depth data analysis. In addition, the verified real DVC locations can be used to generate care areas for E-Beam die-to-die (D2D) inspection, which can effectively improve throughput and reduce the turn-around-time (TAT). In this paper, we will discuss a use case at the Vx layer.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122629759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Doise, J. Bekaert, B. T. Chan, Sungeun Hong, Guanyang Lin, R. Gronheid
Directed self-assembly (DSA) of block copolymers (BCP) is considered a promising patterning approach for the 7 nm node and beyond. Specifically, a grapho-epitaxy process using a cylindrical phase BCP may offer an efficient solution for patterning randomly distributed contact holes with sub-resolution pitches, such as found in via and cut mask levels. In any grapho-epitaxy process, the pattern density impacts the template fill (local BCP thickness inside the template) and may cause defects due to respectively over- or underfilling of the template. In order to tackle this issue thoroughly, the parameters that determine template fill and the influence of template fill on the resulting pattern should be investigated. In this work, using three process flow variations (with different template surface energy), template fill is experimentally characterized as a function of pattern density and film thickness. The impact of these parameters on template fill is highly dependent on the process flow, and thus pre-pattern surface energy. Template fill has a considerable effect on the pattern transfer of the DSA contact holes into the underlying layer. Higher fill levels give rise to smaller contact holes and worse critical dimension uniformity. These results are important towards DSA-aware design and show that fill is a crucial parameter in grapho-epitaxy DSA.
{"title":"Influence of template fill in graphoepitaxy DSA","authors":"J. Doise, J. Bekaert, B. T. Chan, Sungeun Hong, Guanyang Lin, R. Gronheid","doi":"10.1117/12.2219580","DOIUrl":"https://doi.org/10.1117/12.2219580","url":null,"abstract":"Directed self-assembly (DSA) of block copolymers (BCP) is considered a promising patterning approach for the 7 nm node and beyond. Specifically, a grapho-epitaxy process using a cylindrical phase BCP may offer an efficient solution for patterning randomly distributed contact holes with sub-resolution pitches, such as found in via and cut mask levels. In any grapho-epitaxy process, the pattern density impacts the template fill (local BCP thickness inside the template) and may cause defects due to respectively over- or underfilling of the template. In order to tackle this issue thoroughly, the parameters that determine template fill and the influence of template fill on the resulting pattern should be investigated. In this work, using three process flow variations (with different template surface energy), template fill is experimentally characterized as a function of pattern density and film thickness. The impact of these parameters on template fill is highly dependent on the process flow, and thus pre-pattern surface energy. Template fill has a considerable effect on the pattern transfer of the DSA contact holes into the underlying layer. Higher fill levels give rise to smaller contact holes and worse critical dimension uniformity. These results are important towards DSA-aware design and show that fill is a crucial parameter in grapho-epitaxy DSA.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128871898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Koike, A. Hara, Sakurako Natori, Shohei Yamauchi, Masatoshi Yamato, K. Oyama, H. Yaegashi
Gridded design rules[1] is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line and space pattern by using multiple patterning techniques such as self-aligned multiple patterning (SAMP) and litho-etch- litho-etch (LELE)[2][3][5] . On the other hand, Line cut process has some error parameters such as pattern defect, placement error, roughness and X-Y CD bias with the decreasing scale. Especially roughness and X-Y CD bias are paid attention because it cause cut error and pattern defect. In this case, we applied some smoothing process to care hole roughness[4]. Each smoothing process showed different effect on X-Y CD bias. In this paper, we will report the pattern controllability comparison of trench and block + inverse. It include X-Y CD bias, roughness and process usability. Furthermore we will discuss optimum method focused on X-Y CD bias when we use additional process such as smoothing and shrink etching .
{"title":"CD bias control on hole pattern","authors":"K. Koike, A. Hara, Sakurako Natori, Shohei Yamauchi, Masatoshi Yamato, K. Oyama, H. Yaegashi","doi":"10.1117/12.2218961","DOIUrl":"https://doi.org/10.1117/12.2218961","url":null,"abstract":"Gridded design rules[1] is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line and space pattern by using multiple patterning techniques such as self-aligned multiple patterning (SAMP) and litho-etch- litho-etch (LELE)[2][3][5] . On the other hand, Line cut process has some error parameters such as pattern defect, placement error, roughness and X-Y CD bias with the decreasing scale. Especially roughness and X-Y CD bias are paid attention because it cause cut error and pattern defect. In this case, we applied some smoothing process to care hole roughness[4]. Each smoothing process showed different effect on X-Y CD bias. In this paper, we will report the pattern controllability comparison of trench and block + inverse. It include X-Y CD bias, roughness and process usability. Furthermore we will discuss optimum method focused on X-Y CD bias when we use additional process such as smoothing and shrink etching .","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"9779 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130252315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Sekiguchi, Y. Matsumoto, H. Tanaka, T. Horiuchi, Yoshihisa Sensu, S. Takei, M. Hanabata
Novolak resists have been widely used in IC production and are still used in the production of flat panel displays (FPDs) and MEMS. However, with the advent of high-definition products, FPDs increasingly face requirements for finer dimensions. These trends have generated requirements for higher sensitivity, higher resolution, and wider process margin for novolak resists. Using a lithography simulator with the goal of improving the performance of novolak resists, we examined various approaches to improving resist materials. This report discusses efforts to improve resolution and sensitivity using highly fractionated novolak resins and adding low molecular weight phenol resins.
{"title":"Enhancing the Novolak resin resist resolution by adding phenol to fractionated resin","authors":"A. Sekiguchi, Y. Matsumoto, H. Tanaka, T. Horiuchi, Yoshihisa Sensu, S. Takei, M. Hanabata","doi":"10.1117/12.2218948","DOIUrl":"https://doi.org/10.1117/12.2218948","url":null,"abstract":"Novolak resists have been widely used in IC production and are still used in the production of flat panel displays (FPDs) and MEMS. However, with the advent of high-definition products, FPDs increasingly face requirements for finer dimensions. These trends have generated requirements for higher sensitivity, higher resolution, and wider process margin for novolak resists. Using a lithography simulator with the goal of improving the performance of novolak resists, we examined various approaches to improving resist materials. This report discusses efforts to improve resolution and sensitivity using highly fractionated novolak resins and adding low molecular weight phenol resins.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134022493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Toriumi, Y. Sato, R. Kumai, Y. Yamashita, K. Tsukiyama, T. Itani
We characterized EIDEC metal resist for EUV lithography by various measurement methods. The low-voltage aberration-corrected scanning transmission electron microscopy combined with electron energy-loss spectroscopy showed the morphology of metal resists in nanometer regions and enabled studying the distribution of resist component in the resist film. The zirconium oxide metal resist kept the core-shell structure in the resist films and the titanium oxide metal resist showed the aggregation in the film. X-ray diffractometry and ab initio molecular dynamics simulation showed the amorphous structure with short-range order of the zirconium oxide metal resist. X-ray Photoelectron spectroscopy of the zirconium oxide-methacrylic acid metal resist showed the decomposition of the shell molecules and the increase of electron density at zirconium atoms after the EUV exposure. Infrared (IR) spectra indicated that the shell molecules made the various bindings to the metal core and the specific vibrational mode of shell molecules showed the divergent responsivity to the irradiation wavenumber of the IR Free electron laser.
{"title":"Characterization of 'metal resist' for EUV lithography","authors":"M. Toriumi, Y. Sato, R. Kumai, Y. Yamashita, K. Tsukiyama, T. Itani","doi":"10.1117/12.2219030","DOIUrl":"https://doi.org/10.1117/12.2219030","url":null,"abstract":"We characterized EIDEC metal resist for EUV lithography by various measurement methods. The low-voltage aberration-corrected scanning transmission electron microscopy combined with electron energy-loss spectroscopy showed the morphology of metal resists in nanometer regions and enabled studying the distribution of resist component in the resist film. The zirconium oxide metal resist kept the core-shell structure in the resist films and the titanium oxide metal resist showed the aggregation in the film. X-ray diffractometry and ab initio molecular dynamics simulation showed the amorphous structure with short-range order of the zirconium oxide metal resist. X-ray Photoelectron spectroscopy of the zirconium oxide-methacrylic acid metal resist showed the decomposition of the shell molecules and the increase of electron density at zirconium atoms after the EUV exposure. Infrared (IR) spectra indicated that the shell molecules made the various bindings to the metal core and the specific vibrational mode of shell molecules showed the divergent responsivity to the irradiation wavenumber of the IR Free electron laser.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123371140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Peng-xin Liu, Leiwu Zheng, M. Ma, Qian Zhao, Yongfa Fan, Qiang Q. Zhang, Mu Feng, Xin Guo, Tom Wallow, K. Gronlund, R. Goossens, Gary Zhang, Yen-Wen Lu
Strong resist shrinkage effects have been widely observed in resist profiles after negative tone development (NTD) and therefore must be taken into account in computational lithography applications. However, existing lithography simulation tools, especially those designed for full-chip applications, lack resist shrinkage modeling capabilities because they are not needed until only recently when NTD processes begin to replace the conventional positive tone development (PTD) processes where resist shrinkage effects are negligible. In this work we describe the development of a physical resist shrinkage (PRS) model for full-chip lithography simulations and present its accuracy evaluation against experimental data.
{"title":"A physical resist shrinkage model for full-chip lithography simulations","authors":"Peng-xin Liu, Leiwu Zheng, M. Ma, Qian Zhao, Yongfa Fan, Qiang Q. Zhang, Mu Feng, Xin Guo, Tom Wallow, K. Gronlund, R. Goossens, Gary Zhang, Yen-Wen Lu","doi":"10.1117/12.2239243","DOIUrl":"https://doi.org/10.1117/12.2239243","url":null,"abstract":"Strong resist shrinkage effects have been widely observed in resist profiles after negative tone development (NTD) and therefore must be taken into account in computational lithography applications. However, existing lithography simulation tools, especially those designed for full-chip applications, lack resist shrinkage modeling capabilities because they are not needed until only recently when NTD processes begin to replace the conventional positive tone development (PTD) processes where resist shrinkage effects are negligible. In this work we describe the development of a physical resist shrinkage (PRS) model for full-chip lithography simulations and present its accuracy evaluation against experimental data.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115195619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Yao, S. Mullen, E. Wolfer, D. Mckenzie, D. Rahman, JoonYeon Cho, M. Padmanaban, C. Petermann, Sungeun Hong, Y. Her
Metal oxide or metal nitride films are used as hard mask materials in semiconductor industry for patterning purposes due to their excellent etch resistances against the plasma etches. Chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques are usually used to deposit the metal containing materials on substrates or underlying films, which uses specialized equipment and can lead to high cost-of-ownership and low throughput. We have reported novel spin-on coatings that provide simple and cost effective method to generate metal oxide films possessing good etch selectivity and can be removed by chemical agents. In this paper, new spin-on Al oxide and Zr oxide hard mask formulations are reported. The new metal oxide formulations provide higher metal content compared to previously reported material of specific metal oxides under similar processing conditions. These metal oxide films demonstrate ultra-high etch selectivity and good pattern transfer capability. The cured films can be removed by various chemical agents such as developer, solvents or wet etchants/strippers commonly used in the fab environment. With high metal MHM material as an underlayer, the pattern transfer process is simplified by reducing the number of layers in the stack and the size of the nano structure is minimized by replacement of a thicker film ACL. Therefore, these novel AZ® spinon metal oxide hard mask materials can potentially be used to replace any CVD or ALD metal, metal oxide, metal nitride or spin-on silicon-containing hard mask films in 193 nm or EUV process.
{"title":"Spin-on metal oxide materials with high etch selectivity and wet strippability","authors":"H. Yao, S. Mullen, E. Wolfer, D. Mckenzie, D. Rahman, JoonYeon Cho, M. Padmanaban, C. Petermann, Sungeun Hong, Y. Her","doi":"10.1117/12.2220293","DOIUrl":"https://doi.org/10.1117/12.2220293","url":null,"abstract":"Metal oxide or metal nitride films are used as hard mask materials in semiconductor industry for patterning purposes due to their excellent etch resistances against the plasma etches. Chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques are usually used to deposit the metal containing materials on substrates or underlying films, which uses specialized equipment and can lead to high cost-of-ownership and low throughput. We have reported novel spin-on coatings that provide simple and cost effective method to generate metal oxide films possessing good etch selectivity and can be removed by chemical agents. In this paper, new spin-on Al oxide and Zr oxide hard mask formulations are reported. The new metal oxide formulations provide higher metal content compared to previously reported material of specific metal oxides under similar processing conditions. These metal oxide films demonstrate ultra-high etch selectivity and good pattern transfer capability. The cured films can be removed by various chemical agents such as developer, solvents or wet etchants/strippers commonly used in the fab environment. With high metal MHM material as an underlayer, the pattern transfer process is simplified by reducing the number of layers in the stack and the size of the nano structure is minimized by replacement of a thicker film ACL. Therefore, these novel AZ® spinon metal oxide hard mask materials can potentially be used to replace any CVD or ALD metal, metal oxide, metal nitride or spin-on silicon-containing hard mask films in 193 nm or EUV process.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114896664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wataru Shibayama, Shuhei Shigaki, S. Takeda, R. Onishi, M. Nakajima, Rikimaru Sakamoto
ArF lithography is still major process to develop N7/N5 devices. Especially in resist materials, DOF, roughness and CD uniformity are the biggest key parameters in fine pitches. To improve these issues, we newly propose to apply Dry Development Rinse Process (DDRP) and Materials (DDRM) as the ArF extension approach. In EUV lithography, DDRP is already one of the approaches to achieve high resolution. However, the performance of DDRP for ArF lithography was never demonstrated in detail. In this paper, we especially focus to improve DOF, CD uniformity and roughness by applying DDRP for ArF generation. Finally we succeeded to enhance every parameter at the same time by controlling DDRM etching condition. This new DDRP technology can be the promising approach for ArF extension stages in N7/N5 and beyond.
{"title":"Novel ArF extension technique by applying Dry Development Rinse Process (DDRP) and Materials (DDRM)","authors":"Wataru Shibayama, Shuhei Shigaki, S. Takeda, R. Onishi, M. Nakajima, Rikimaru Sakamoto","doi":"10.1117/12.2219521","DOIUrl":"https://doi.org/10.1117/12.2219521","url":null,"abstract":"ArF lithography is still major process to develop N7/N5 devices. Especially in resist materials, DOF, roughness and CD uniformity are the biggest key parameters in fine pitches. To improve these issues, we newly propose to apply Dry Development Rinse Process (DDRP) and Materials (DDRM) as the ArF extension approach. In EUV lithography, DDRP is already one of the approaches to achieve high resolution. However, the performance of DDRP for ArF lithography was never demonstrated in detail. In this paper, we especially focus to improve DOF, CD uniformity and roughness by applying DDRP for ArF generation. Finally we succeeded to enhance every parameter at the same time by controlling DDRM etching condition. This new DDRP technology can be the promising approach for ArF extension stages in N7/N5 and beyond.","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122619589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Oyama, A. Hara, K. Koike, Masatoshi Yamato, Shohei Yamauchi, Sakurako Natori, H. Yaegashi
The continuously scaling of complex device geometries is driving by the self-aligned multiple patterning techniques. Depending on such simplified LS scaling, FinFET design rule has been accelerated to unidirectional design layout. [1] In particular Fin, Gate and Metal layers are based on grating with cutting/blocking scheme, these process have become high volume manufacturing techniques in N14 and beyond.[2,3] On the other hand, immersions based pitch scaling of contact hole, via and cutmask processes are required multiple lithography and etching passes.[4] Overlay management is not only the overlay accuracy of layer to layer, to determine the placement error and patterning fidelity in single layer. In this work, focusing on the placement in hole pattern, total placement error budget will be discussed from the viewpoints of metrology, inspection, Mask, OPC and wafer processing. In addition, hole shrink and hole healing techniques have more significant factors in terms of design-process technology co-optimization for N7 and beyond.[5]
{"title":"Contact/Via placement management for N7 logic and beyond","authors":"K. Oyama, A. Hara, K. Koike, Masatoshi Yamato, Shohei Yamauchi, Sakurako Natori, H. Yaegashi","doi":"10.1117/12.2218976","DOIUrl":"https://doi.org/10.1117/12.2218976","url":null,"abstract":"The continuously scaling of complex device geometries is driving by the self-aligned multiple patterning techniques. Depending on such simplified LS scaling, FinFET design rule has been accelerated to unidirectional design layout. [1] In particular Fin, Gate and Metal layers are based on grating with cutting/blocking scheme, these process have become high volume manufacturing techniques in N14 and beyond.[2,3] On the other hand, immersions based pitch scaling of contact hole, via and cutmask processes are required multiple lithography and etching passes.[4] Overlay management is not only the overlay accuracy of layer to layer, to determine the placement error and patterning fidelity in single layer. In this work, focusing on the placement in hole pattern, total placement error budget will be discussed from the viewpoints of metrology, inspection, Mask, OPC and wafer processing. In addition, hole shrink and hole healing techniques have more significant factors in terms of design-process technology co-optimization for N7 and beyond.[5]","PeriodicalId":193904,"journal":{"name":"SPIE Advanced Lithography","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116527023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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