Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569628
Jeonghoon Lee, Shinil Chang, Jaehwan Lee, Jisun Ryu, Kihyeok Ha, Yongchang Choi, Young-Hwa Kim, Sanghyun Hwang, Hongju Song, Kiwon Choi, Sangyoub Lee
Summary form only given. This paper presents a direct conversion Korean standard T-DMB SoC tuner using a 65nm low power CMOS technology with the best feature of size, power and BoM ever reported. A digital F/E enhanced function is implemented to reduce analog signal processing empowered by oversampled A/D converter, digital channel selection filter and lots of digital calibration blocks. And the designed LNA excludes all required inductors. Thus high voltage gain and low current consumption are achieved due to their high Q factor. A single-to-differential signaling down-conversion mixer is also announced which has well balanced output characteristic. A DC/DC converter is adopted as well for the further low power consuming. The tunable clock frequency scheme of DC/DC buck converter can prevent a degradation of sensitivity performances which is planed value to escape the channel center frequency. This reported SoC tuner consumes only 28mA at maximum gain mode. And -103.5dBm of sensitivity and 48dBc of N±1 adjacent-channel selectivity are achieved also with only 5 external LC components. This SoC occupies 2.5×2.5mm2 die and WLCSP chip size.
{"title":"A T-DMB mobile TV SoC tuner with compact size, low power and BoM in 65nm CMOS","authors":"Jeonghoon Lee, Shinil Chang, Jaehwan Lee, Jisun Ryu, Kihyeok Ha, Yongchang Choi, Young-Hwa Kim, Sanghyun Hwang, Hongju Song, Kiwon Choi, Sangyoub Lee","doi":"10.1109/RFIC.2013.6569628","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569628","url":null,"abstract":"Summary form only given. This paper presents a direct conversion Korean standard T-DMB SoC tuner using a 65nm low power CMOS technology with the best feature of size, power and BoM ever reported. A digital F/E enhanced function is implemented to reduce analog signal processing empowered by oversampled A/D converter, digital channel selection filter and lots of digital calibration blocks. And the designed LNA excludes all required inductors. Thus high voltage gain and low current consumption are achieved due to their high Q factor. A single-to-differential signaling down-conversion mixer is also announced which has well balanced output characteristic. A DC/DC converter is adopted as well for the further low power consuming. The tunable clock frequency scheme of DC/DC buck converter can prevent a degradation of sensitivity performances which is planed value to escape the channel center frequency. This reported SoC tuner consumes only 28mA at maximum gain mode. And -103.5dBm of sensitivity and 48dBc of N±1 adjacent-channel selectivity are achieved also with only 5 external LC components. This SoC occupies 2.5×2.5mm2 die and WLCSP chip size.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130291113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569623
A. Imani, H. Hashemi
A sensitive low-noise frequency/phase discriminator and its applications in phase noise measurement and phase noise cancellation are presented. The discriminator uses a high quality factor thin Film Bulk Acoustic Resonator (FBAR) in a notch filter configuration with common-mode traps to reduce the low-frequency noise up-conversion. The performance of the notch filter, the discriminator transfer function, output noise, and phase noise floor are measured and compared with simulations. A feed-back feed-forward phase noise cancellation scheme is proposed based on the frequency/phase discriminator. Two chips were fabricated in 0.13 μm CMOS technology integrating the discriminator and the phase noise cancellation schemes, respectively. The 1.5 GHz discriminator shows phase noise floor of -128 dBc/Hz at 20 kHz,-142 dBc/Hz at 100 kHz, -162 dBc/Hz at 1 MHz and-166 dBc/Hz at 4 MHz, while consuming 26 mW of power. The measured phase noise of the feedback cancellation circuitry reaches the phase noise floor of the discriminator, verifying the proposed concepts.
{"title":"A low-noise FBAR-CMOS frequency/phase discriminator for phase noise measurement and cancellation","authors":"A. Imani, H. Hashemi","doi":"10.1109/RFIC.2013.6569623","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569623","url":null,"abstract":"A sensitive low-noise frequency/phase discriminator and its applications in phase noise measurement and phase noise cancellation are presented. The discriminator uses a high quality factor thin Film Bulk Acoustic Resonator (FBAR) in a notch filter configuration with common-mode traps to reduce the low-frequency noise up-conversion. The performance of the notch filter, the discriminator transfer function, output noise, and phase noise floor are measured and compared with simulations. A feed-back feed-forward phase noise cancellation scheme is proposed based on the frequency/phase discriminator. Two chips were fabricated in 0.13 μm CMOS technology integrating the discriminator and the phase noise cancellation schemes, respectively. The 1.5 GHz discriminator shows phase noise floor of -128 dBc/Hz at 20 kHz,-142 dBc/Hz at 100 kHz, -162 dBc/Hz at 1 MHz and-166 dBc/Hz at 4 MHz, while consuming 26 mW of power. The measured phase noise of the feedback cancellation circuitry reaches the phase noise floor of the discriminator, verifying the proposed concepts.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134522273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569581
K. Datta, J. Roderick, H. Hashemi
Design equations and performance limits of stacked Class-E power amplifiers at mm-waves, including the limitations imposed by device parasitics, are presented in this paper. As a proof of concept of this parasitic aware mm-wave Class-E design methodology and to demonstrate the beyond BVCEO Class-E operation in a stacked architecture at mm-wave frequencies, a Q-band, single ended, two-stage, double-stacked, Class-E power amplifier is designed in a 0.13 μm SiGe HBT BiCMOS process. The measured performance of the fabricated chip show 23.4 dBm maximum output power at 34.9% peak power added efficiency (PAE), and 14.6 dB of power gain across 5 GHz centered around 41 GHz for a supply voltage of 4 V. The total chip area including the pads is 0.8 mm × 1.28 mm.
{"title":"Analysis, design and implementation of mm-Wave SiGe stacked Class-E power amplifiers","authors":"K. Datta, J. Roderick, H. Hashemi","doi":"10.1109/RFIC.2013.6569581","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569581","url":null,"abstract":"Design equations and performance limits of stacked Class-E power amplifiers at mm-waves, including the limitations imposed by device parasitics, are presented in this paper. As a proof of concept of this parasitic aware mm-wave Class-E design methodology and to demonstrate the beyond BVCEO Class-E operation in a stacked architecture at mm-wave frequencies, a Q-band, single ended, two-stage, double-stacked, Class-E power amplifier is designed in a 0.13 μm SiGe HBT BiCMOS process. The measured performance of the fabricated chip show 23.4 dBm maximum output power at 34.9% peak power added efficiency (PAE), and 14.6 dB of power gain across 5 GHz centered around 41 GHz for a supply voltage of 4 V. The total chip area including the pads is 0.8 mm × 1.28 mm.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132874816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569543
Seitaro Kawai, R. Minami, Yuki Tsukui, Y. Takeuchi, Hiroki Asada, Ahmed Musa, Rui Murakami, Takahiro Sato, Qinghong Bu, Ning Li, M. Miyahara, K. Okada, A. Matsuzawa
This paper presents a digitally-calibrated 60-GHz direct-conversion transceiver. To improve the error vector magnitude (EVM) performance over the wide bandwidth, a digital calibration technique is applied. The 60-GHz transceiver implemented by 65 nm CMOS achieves the maximum data rates of 20 Gb/s in 16QAM mode. The transmitter and receiver consume 351 mW and 238 mW from 1.2 V supply, respectively. As a 60-GHz transceiver, the best Tx-to-Rx EVM performance of -26.2 dB is achieved for 16QAM 7Gb/s data rate.
{"title":"A digitally-calibrated 20-Gb/s 60-GHz direct-conversion transceiver in 65-nm CMOS","authors":"Seitaro Kawai, R. Minami, Yuki Tsukui, Y. Takeuchi, Hiroki Asada, Ahmed Musa, Rui Murakami, Takahiro Sato, Qinghong Bu, Ning Li, M. Miyahara, K. Okada, A. Matsuzawa","doi":"10.1109/RFIC.2013.6569543","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569543","url":null,"abstract":"This paper presents a digitally-calibrated 60-GHz direct-conversion transceiver. To improve the error vector magnitude (EVM) performance over the wide bandwidth, a digital calibration technique is applied. The 60-GHz transceiver implemented by 65 nm CMOS achieves the maximum data rates of 20 Gb/s in 16QAM mode. The transmitter and receiver consume 351 mW and 238 mW from 1.2 V supply, respectively. As a 60-GHz transceiver, the best Tx-to-Rx EVM performance of -26.2 dB is achieved for 16QAM 7Gb/s data rate.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"26 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127650085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569570
Farid Shirinfar, M. Nariman, T. Sowlati, M. Rofougaran, R. Rofougaran, S. Pamarti
Clustering and multi-core transformer coupling techniques are presented to improve phase noise, tuning range, and reliability of a mm-wave VCO. A proofof-concept design targeting the WiGig protocol is shown. Each cluster of VCOs covers one channel resulting in better phase noise performance. Multicores of VCOs with uncorrelated noise are combined using transformers to further enhance phase noise and combat the voltage swing reliability issues. Furthermore, due to realization of multiple inductive elements in parallel instead of one small inductor, this approach bypasses Q-degradation of small inductors (<;50pH). The VCO achieves a phase noise of -101.8dBc/Hz at 1MHz offset with over 12.6% tuning range (50.7GHz to 57.5GHz) and an FOM of -183dB/Hz.
{"title":"A multichannel, multicore mm-Wave clustered VCO with phase noise, tuning range, and lifetime reliability enhancements","authors":"Farid Shirinfar, M. Nariman, T. Sowlati, M. Rofougaran, R. Rofougaran, S. Pamarti","doi":"10.1109/RFIC.2013.6569570","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569570","url":null,"abstract":"Clustering and multi-core transformer coupling techniques are presented to improve phase noise, tuning range, and reliability of a mm-wave VCO. A proofof-concept design targeting the WiGig protocol is shown. Each cluster of VCOs covers one channel resulting in better phase noise performance. Multicores of VCOs with uncorrelated noise are combined using transformers to further enhance phase noise and combat the voltage swing reliability issues. Furthermore, due to realization of multiple inductive elements in parallel instead of one small inductor, this approach bypasses Q-degradation of small inductors (<;50pH). The VCO achieves a phase noise of -101.8dBc/Hz at 1MHz offset with over 12.6% tuning range (50.7GHz to 57.5GHz) and an FOM of -183dB/Hz.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126127361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569611
A. Joseph, A. Botula, J. Slinkman, R. Wolf, R. Phelps, M. Abou-Khalil, J. Ellis-Monaghan, S. Moss, M. Jaffe
In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.
{"title":"Power handling capability of an SOI RF switch","authors":"A. Joseph, A. Botula, J. Slinkman, R. Wolf, R. Phelps, M. Abou-Khalil, J. Ellis-Monaghan, S. Moss, M. Jaffe","doi":"10.1109/RFIC.2013.6569611","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569611","url":null,"abstract":"In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of various parameters, such as, switch stack height, channel length, Gate and Body bias, and process parameters. Overall, we find that the Pmax can be improved by reducing stack imbalance as well as device leakage currents, namely, GIDL.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122382339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569522
Q. Ma, D. Leenaerts, R. Mahmoudi
A fully integrated 2-channel Ka-band True Time Delay (TTD) phase shifter with 12ps continuous changing delay time has been realized in a 0.25μm SiGe:C BiCMOS technology. A delay variation cancellation technique is proposed, resulting in less than 0.8ps delay variation over a 20-40GHz frequency span, meanwhile maintaining a constant input impedance. In the high (low) power mode, the measured input 1dB compression point and input IP3 are +9.7dBm (+3.6dBm) and +18dBm (+13dBm) at 30GHz with an averaged power consumption per channel of 145mW (33mW) for the same TTD performance. The size of the core phase shifter is less than 0.1mm2.
{"title":"A 12ps true-time-delay phase shifter with 6.6% delay variation at 20–40GHz","authors":"Q. Ma, D. Leenaerts, R. Mahmoudi","doi":"10.1109/RFIC.2013.6569522","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569522","url":null,"abstract":"A fully integrated 2-channel Ka-band True Time Delay (TTD) phase shifter with 12ps continuous changing delay time has been realized in a 0.25μm SiGe:C BiCMOS technology. A delay variation cancellation technique is proposed, resulting in less than 0.8ps delay variation over a 20-40GHz frequency span, meanwhile maintaining a constant input impedance. In the high (low) power mode, the measured input 1dB compression point and input IP3 are +9.7dBm (+3.6dBm) and +18dBm (+13dBm) at 30GHz with an averaged power consumption per channel of 145mW (33mW) for the same TTD performance. The size of the core phase shifter is less than 0.1mm2.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132378955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569511
Teruo Jyo, T. Kuroda, H. Ishikuro
This paper presents a low-power LNA for a inductive-coupling tranceiver. Intermittently operating technique to turn on LNA only at the moment when the pulse signal appears is used to reduce power consumption. To optimally control the On-time of LNA, pulse width detector based on self-oversampling TDC is used and compensate the PVT variations of On-time width and of pulse signal width. The fabricated test chip in 65nm CMOS occupies 0.06mm2 and achieved the intermittently operating frequency at the range from 60 to 400Mbps. The power consumption is 0.42mW at 400Mbps and the supply voltage of 0.7V which corresponds to 37% power reduction from the power consumption without optimal On-Time Controller.
{"title":"A 0.7V intermittently operating LNA with optimal on-time controller for pulse-based inductive-coupling transceiver","authors":"Teruo Jyo, T. Kuroda, H. Ishikuro","doi":"10.1109/RFIC.2013.6569511","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569511","url":null,"abstract":"This paper presents a low-power LNA for a inductive-coupling tranceiver. Intermittently operating technique to turn on LNA only at the moment when the pulse signal appears is used to reduce power consumption. To optimally control the On-time of LNA, pulse width detector based on self-oversampling TDC is used and compensate the PVT variations of On-time width and of pulse signal width. The fabricated test chip in 65nm CMOS occupies 0.06mm2 and achieved the intermittently operating frequency at the range from 60 to 400Mbps. The power consumption is 0.42mW at 400Mbps and the supply voltage of 0.7V which corresponds to 37% power reduction from the power consumption without optimal On-Time Controller.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125543362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569589
M. Elkhouly, Y. Mao, S. Glisic, C. Meliani, F. Ellinger, J. Scheytt
A 240 GHz direct conversion IQ receiver manufactured in 0.13 SiGe BiCMOS technology with fT/fmax of 300/500 GHz is presented. The receiver consists of a four stage LNA, an active power divider, an LO IQ generation network, and direct down-conversion fundamental mixers. The integrated IQ receiver yields a conversion gain of 18 dB, an 18 dB simulated DSB NF, and a 3 dB bandwidth of 25 GHz. The required 245 GHz LO power is in the order of -10 dBm. The receiver exhibits an IQ amplitude and phase imbalance of 1 dB and 3° respectively. It draws 135 mA from the 3.5 V supply and 20 mA from 2 V.
{"title":"A 240 GHz direct conversion IQ receiver in 0.13 μm SiGe BiCMOS technology","authors":"M. Elkhouly, Y. Mao, S. Glisic, C. Meliani, F. Ellinger, J. Scheytt","doi":"10.1109/RFIC.2013.6569589","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569589","url":null,"abstract":"A 240 GHz direct conversion IQ receiver manufactured in 0.13 SiGe BiCMOS technology with fT/fmax of 300/500 GHz is presented. The receiver consists of a four stage LNA, an active power divider, an LO IQ generation network, and direct down-conversion fundamental mixers. The integrated IQ receiver yields a conversion gain of 18 dB, an 18 dB simulated DSB NF, and a 3 dB bandwidth of 25 GHz. The required 245 GHz LO power is in the order of -10 dBm. The receiver exhibits an IQ amplitude and phase imbalance of 1 dB and 3° respectively. It draws 135 mA from the 3.5 V supply and 20 mA from 2 V.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114241595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-02DOI: 10.1109/RFIC.2013.6569595
Arnaud Werquin, A. Frappé, A. Kaiser
A two-path digital power amplifier (DPA) in 1.2V 65nm CMOS is presented. This highly reconfigurable and frequency agile block is designed to be used as an envelope modulator in a wideband multi-standard polar transmitter. Each path is composed of a 12-bit DPA ensuring the modulation of the envelope of the RF signal. The DPAs are controlled by envelope code words (ECW) at different sample rates. This diversity strongly attenuates the images produced by the direct digital to RF conversion, avoiding passive filtering. The baseband sample rate conversion can easily be reconfigured. The proposed front-end can manage spurious emissions depending on the standard, the carrier frequency and the required power. The DPAs also integrate active input impedance compensation cells in order to limit the input impedance modulation when switching the DPA cells. The two-path DPA covers a 0.9-1.9 GHz bandwidth with 16.7dBm output 1dB compression point and 12.4% PAE. 64-QAM presents -28dB EVM while active area occupies 1 × 0.25 mm2.
{"title":"A multi-path multi-rate CMOS polar DPA for wideband multi-standard RF transmitters","authors":"Arnaud Werquin, A. Frappé, A. Kaiser","doi":"10.1109/RFIC.2013.6569595","DOIUrl":"https://doi.org/10.1109/RFIC.2013.6569595","url":null,"abstract":"A two-path digital power amplifier (DPA) in 1.2V 65nm CMOS is presented. This highly reconfigurable and frequency agile block is designed to be used as an envelope modulator in a wideband multi-standard polar transmitter. Each path is composed of a 12-bit DPA ensuring the modulation of the envelope of the RF signal. The DPAs are controlled by envelope code words (ECW) at different sample rates. This diversity strongly attenuates the images produced by the direct digital to RF conversion, avoiding passive filtering. The baseband sample rate conversion can easily be reconfigured. The proposed front-end can manage spurious emissions depending on the standard, the carrier frequency and the required power. The DPAs also integrate active input impedance compensation cells in order to limit the input impedance modulation when switching the DPA cells. The two-path DPA covers a 0.9-1.9 GHz bandwidth with 16.7dBm output 1dB compression point and 12.4% PAE. 64-QAM presents -28dB EVM while active area occupies 1 × 0.25 mm2.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125288198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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